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Datasheet
Datasheet
Datasheet
Rev.3.00
Revision Date: Jan. 18, 2008
Rev. 3.00 Jan. 18, 2008 Page ii of lxii
Notes regarding these materials
1. This document is provided for reference purposes only so that Renesas customers may select the appropriate
Renesas products for their use. Renesas neither makes warranties or representations with respect to the
accuracy or completeness of the information contained in this document nor grants any license to any
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out of the use of any information in this document, including, but not limited to, product data, diagrams, charts,
programs, algorithms, and application circuit examples.
3. You should not use the products or the technology described in this document for the purpose of military
applications such as the development of weapons of mass destruction or for the purpose of any other military
use. When exporting the products or technology described herein, you should follow the applicable export
control laws and regulations, and procedures required by such laws and regulations.
4. All information included in this document such as product data, diagrams, charts, programs, algorithms, and
application circuit examples, is current as of the date this document is issued. Such information, however, is
subject to change without any prior notice. Before purchasing or using any Renesas products listed in this
document, please confirm the latest product information with a Renesas sales office. Also, please pay regular
and careful attention to additional and different information to be disclosed by Renesas such as that disclosed
through our website. (http://www.renesas.com )
5. Renesas has used reasonable care in compiling the information included in this document, but Renesas
assumes no liability whatsoever for any damages incurred as a result of errors or omissions in the information
included in this document.
6. When using or otherwise relying on the information in this document, you should evaluate the information in
light of the total system before deciding about the applicability of such information to the intended application.
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particular application and specifically disclaims any liability arising out of the application and use of the
information in this document or Renesas products.
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products are not designed, manufactured or tested for applications or otherwise in systems the failure or
malfunction of which may cause a direct threat to human life or create a risk of human injury or which require
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(1) artificial life support devices or systems
(2) surgical implantations
(3) healthcare intervention (e.g., excision, administration of medication, etc.)
(4) any other purposes that pose a direct threat to human life
Renesas shall have no liability for damages arising out of the uses set forth in the above and purchasers who
elect to use Renesas products in any of the foregoing applications shall indemnify and hold harmless Renesas
Technology Corp., its affiliated companies and their officers, directors, and employees against any and all
damages arising out of such applications.
9. You should use the products described herein within the range specified by Renesas, especially with respect
to the maximum rating, operating supply voltage range, movement power voltage range, heat radiation
characteristics, installation and other product characteristics. Renesas shall have no liability for malfunctions or
damages arising out of the use of Renesas products beyond such specified ranges.
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characteristics such as the occurrence of failure at a certain rate and malfunctions under certain use
conditions. Please be sure to implement safety measures to guard against the possibility of physical injury, and
injury or damage caused by fire in the event of the failure of a Renesas product, such as safety design for
hardware and software including but not limited to redundancy, fire control and malfunction prevention,
appropriate treatment for aging degradation or any other applicable measures. Among others, since the
evaluation of microcomputer software alone is very difficult, please evaluate the safety of the final products or
system manufactured by you.
11. In case Renesas products listed in this document are detached from the products to which the Renesas
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document, Renesas semiconductor products, or if you have any other inquiries.
1. Treatment of NC Pins
Note: Do not connect anything to the NC pins.
The NC (not connected) pins are either not connected to any of the internal circuitry or are
used as test pins or to reduce noise. If something is connected to the NC pins, the
operation of the LSI is not guaranteed.
7. List of Registers
8. Electrical Characteristics
9. Appendix
10. Main Revisions and Additions in this Edition (only for revised versions)
The list of revisions is a summary of points that have been revised or added to earlier versions.
This does not include all of the revised contents. For details, see the actual locations in this
manual.
11. Index
Target Users: This manual was written for users who will be using this LSI in the design of
application systems. Users of this manual are expected to understand the
fundamentals of electrical circuits, logical circuits, and microcomputers.
Objective: This manual was written to explain the hardware functions and electrical
characteristics of this LSI to the above users.
Refer to the SH-3/SH-3E/SH3-DSP Software Manual for a detailed description of
the instruction set.
• Product names
The following products are covered in this manual.
Related Manuals: The latest versions of all related manuals are available from our web site.
Please ensure you have the latest versions of all documents you require.
http://www.renesas.com/
Application note:
All trademarks and registered trademarks are the property of their respective owners.
Section 1 Overview..................................................................................................1
1.1 Features.................................................................................................................................. 1
1.2 Block Diagram ..................................................................................................................... 10
1.3 Pin Assignments................................................................................................................... 10
1.3.1 Pin Assignments ..................................................................................................... 10
1.3.2 Pin Functions .......................................................................................................... 25
Section 2 CPU........................................................................................................37
2.1 Processing States and Processing Modes ............................................................................. 37
2.1.1 Processing States..................................................................................................... 37
2.1.2 Processing Modes ................................................................................................... 38
2.2 Memory Map ....................................................................................................................... 39
2.2.1 Virtual Address Space............................................................................................. 39
2.2.2 External Memory Space.......................................................................................... 40
2.3 Register Descriptions ........................................................................................................... 42
2.3.1 General Registers.................................................................................................... 45
2.3.2 System Registers..................................................................................................... 46
2.3.3 Program Counter..................................................................................................... 47
2.3.4 Control Registers .................................................................................................... 48
2.4 Data Formats........................................................................................................................ 51
2.4.1 Register Data Format .............................................................................................. 51
2.4.2 Memory Data Formats ............................................................................................ 52
2.5 Features of CPU Core Instructions ...................................................................................... 54
2.5.1 Instruction Execution Method................................................................................. 54
2.5.2 CPU Instruction Addressing Modes ....................................................................... 56
2.5.3 Instruction Formats ................................................................................................. 60
2.6 Instruction Set ...................................................................................................................... 63
2.6.1 Instruction Set Based on Functions......................................................................... 63
2.6.2 Operation Code Map............................................................................................... 77
Section 1 Overview
Table 1.1 SH7720/SH7721 Features......................................................................................... 2
Table 1.2 Product Lineup (SH7720 Group).............................................................................. 8
Table 1.3 Product Lineup (SH7721 Group).............................................................................. 9
Table 1.4 List of Pin Assignments .......................................................................................... 13
Table 1.5 SH7720/SH7721 Pin Functions .............................................................................. 25
Section 2 CPU
Table 2.1 Virtual Address Space............................................................................................. 40
Table 2.2 Register Initial Values............................................................................................. 43
Table 2.3 Addressing Modes and Effective Addresses for CPU Instructions......................... 56
Table 2.4 CPU Instruction Formats ........................................................................................ 60
Table 2.5 CPU Instruction Types............................................................................................ 63
Table 2.6 Data Transfer Instructions....................................................................................... 67
Table 2.7 Arithmetic Operation Instructions .......................................................................... 69
Table 2.8 Logic Operation Instructions .................................................................................. 71
Table 2.9 Shift Instructions..................................................................................................... 72
Table 2.10 Branch Instructions ................................................................................................. 73
Table 2.11 System Control Instructions.................................................................................... 74
Table 2.12 Operation Code Map............................................................................................... 77
Section 3 DSP Operating Unit
Table 3.1 CPU Processing Modes .......................................................................................... 83
Table 3.2 Virtual Address Space............................................................................................. 84
Table 3.3 Operation of SR Bits in Each Processing Mode ..................................................... 87
Table 3.4 RS and RE Setting Rule.......................................................................................... 93
Table 3.5 Repeat Control Instructions .................................................................................... 93
Table 3.6 Repeat Control Macros ........................................................................................... 94
Table 3.7 DSP Mode Extended System Control Instructions ................................................. 96
Table 3.8 PC Value during Repeat Control (When RC[11:0] ≥ 2) ......................................... 99
Table 3.9 Extended System Control Instructions in DSP Mode ........................................... 103
Table 3.10 Overview of Data Transfer Instructions................................................................ 106
Table 3.11 Modulo Addressing Control Instructions.............................................................. 108
Table 3.12 Double Data Transfer Instruction Formats ........................................................... 111
Table 3.13 Single Data Transfer Instruction Formats ............................................................. 112
Table 3.14 Destination Register in DSP Instructions.............................................................. 114
Table 3.15 Source Register in DSP Operations ...................................................................... 115
Section 1 Overview
1.1 Features
This LSI is a single-chip RISC microprocessor that integrates a 32-bit RISC-type Super H
architecture CPU with a digital signal processing (DSP) extension as its core, together with a
large-capacity 32-kbyte cache memory, a 16-kbyte X/Y memory, and an interrupt controller.
High-speed data transfers can be performed by an on-chip direct memory access controller
(DMAC), and an external memory access support function enables direct connection to different
kinds of memory. This LSI also supports a stereo audio recording and playback function, a USB
host controller, a function controller, an LCD controller, a PCMCIA interface, an A/D converter,
and a D/A converter.
The USB host controller and LCD controller have bus master functions, so that data supplied from
an external memory (area 3) can be freely processed. Since the USB host controller, in particular,
conforms to Open HCI standards, it is extremely easy to transfer data from the PC of a device
driver or other devices. Also, low-power operation suitable for battery operation is possible
because the LCD controller continues to display even in sleep mode.
A powerful built-in power management function keeps power consumption low, even during high-
speed operation. This LSI is ideal for electronics devices, which require both high speed and low
power consumption.
The SH7720 group integrates an SSL (Secure Socket Layer) accelerator that performs RSA
(Rivest-Shamir-Adleman) operations and DES (Data Encryption Standard) and Triple-DES
encryption/decryption, while the SH7721 group does not have the SSL accelerator. Each group
consists of several models which includes or does not include an SD host interface (SDHI) to be
suited to a variety of applications. See table 1.2 and 1.3, Product Lineup, for the models including
(or not including) the SDHI.
Note: For the detailed specifications of the SDHI and SSL, contact the Renesas representatives
in your region.
Item Features
CPU • Renesas Technology Original SuperH architecture
• Upper compatibility with SH-1, SH-2, and SH3-DSP at object code level
• 32-bit internal data bus
• General-register
Sixteen 32-bit general registers (eight 32-bit shadow registers)
Five 32-bit control registers
Four 32-bit system registers
• RISC type instruction set
Instruction length: 16-bit fixed length for improved code efficiency
Load/store architecture
Delayed branch instruction
Instruction set based on C language
• Instruction execution time: One instruction/cycle for basic instructions
• Logical address space: 4 Gbytes
• Space identifier ASID: 8 bits, 256 logical address spaces
• Five-stage pipeline
DSP operating • Mixture of 16-bit and 32-bit instructions
unit • 32-/40-bit internal data bus
• Multiplier, ALU, barrel shifter, and DSP register
• 16-bit x 16-bit → 32-bit one cycle multiplier
• Large-capacity DSP data register file
Six 32-bit data registers
Two 40-bit data registers
• Extended Harvard architecture for DSP data buses
Two data buses
One instruction bus
• Up to four parallel operations: ALU, multiply, two loads, and store
• Two address units to generating addresses for two memory access
• DSP data addressing modes: Increment, index register addition (with or
without modulo addressing)
• Zero-overhead repeat loop control
• Conditional execution instructions
• User DSP mode and privileged DSP mode
Item Features
Memory • 4-Gbyte address space, 256 address spaces (8-bit ASID)
management unit • Page unit sharing
(MMU) • Supports multiple page sizes: 1 kbyte or 4 kbytes
• 128-entry, 4-way set associative TLB
• Specifies replacement way by software and supports random replacement
algorithm
• Address assignment allows direct access to TLB contents
Cache memory • 32-kbyte cache mixing instructions and data
• 512-entry, 4-way set associative, 16-byte block length
• Write-back, write-through, least recent used (LRU) replacement algorithm
• Single-stage write-back buffer
X/Y memory • User-selectable mapping mechanism
Fixed mapping for mission-critical realtime applications
Automatic mapping through TLB for easy to use
• Three independent read/write ports
8-/16-/32-bit access from CPU
Up to two 16-bit accesses from DSP
8-/16-/32-bit access from DMAC
• 8-kbyte RAM for X and Y memory individual (4 kbytes × 4)
Interrupt • Seven external interrupt pins (NMI, IRQ5 to IRQ0)
controller (INTC) NMI: Fall/rise selectable
IRQ: Fall/rise/high level/low level selectable
• On-chip peripheral interrupt: Sets priority for each module
Bus state • Physical address space is provided to support areas of up to 64 Mbytes and
controller (BSC) 32 Mbytes.
• Each area allows independent setting of the following functions:
Bus size (8, 16, or 32 bits). An access wait cycle count with a different
size to be supported is provided for each area.
Number of access wait cycles. Some areas can be inserted wait cycles
independently in read access and write access.
Sets of idle wait cycle (for the same or different area)
Supports SRAM, page mode ROM, SDRAM, and pseudo SRAM (ready
for page mode) by specifying memory to be connected to each area.
Outputs chip select signals to corresponding areas, such as CS0, CS2 to
CS4, CS5A/CS5B, and CS6A/CS6B
Item Features
Direct memory • Number of channels: Six channels (two channels support external requests)
access controller
• Address space: 4 Gbytes on architecture
(DMAC)
• Data transfer length: Bytes, words (2 bytes), longwords (4 bytes), 16 bytes
(longword × 4)
• Maximum number of transfer times: 16,777,216 times
• Address mode: Single address mode or dual address mode selectable
• Transfer request: Selectable from external request, on-chip peripheral
module request, and auto request
• Bus mode: Selectable from cycle steal mode (normal mode and intermittent
mode) and burst mode
• Priority: Selectable from channel priority fixed mode and round robin mode
• Interrupt request: Supports interrupt request to CPU at the end of data
transfer
• External request detection: Selectable from DREQ input low/high level
detection and rising/falling detection
• Transfer request acceptance signal: DACK and TEND can be set an active
level
Clock pulse • Clock mode: Input clock selectable from external clock (EXTAL or CKIO)
generator (CPG) and crystal resonator
• Generates three types of clocks
CPU clock: Maximum 133.34 MHz
Bus clock: Maximum 66.67 MHz
Peripheral clock: Maximum 33.34 MHz
• Supports power-down mode
Sleep mode
Standby mode
Module standby mode (X/Y memory standby enabled)
• One-channel watchdog timer
Watchdog timer • One-channel watchdog timer (WDT)
(WDT)
• Interrupt request: WDT only
Timer unit (TMU) • Internal three-channel 32-bit timer
• Auto-reload type 32-bit down counter
• Internal prescaler for Pφ
• Interrupt request
Item Features
16-bit timer pulse • Four-channel 16-bit timer
unit (TPU)
• PWM mode
• Four types of counter input clocks
• Phase counting mode (two channels)
Compare match • Internal six-channel 32-bit counter (16-/32-bit switchable)
timer (CMT)
• Selectable prescaling for Pφ
• Internal full-channel compare match function
• With interrupt request and DMAC request
Realtime clock • Built-in clock, calendar functions, and alarm functions
(RTC)
• On-chip 32-kHz crystal oscillator circuit with a maximum resolution (cycle
interrupt) of 1/256 second
Serial • Includes a 64-byte FIFO for transmission and another for reception
communication
• Supports high-speed UART for Bluetooth
interface with
FIFO • Internal prescaler for Pφ
(SCIF0, SCIF1) • With interrupt request and DMAC request
Infrared data • Conforms to the IrDA 1.0 system
association
• Asynchronous serial communication
module (IrDA)
• On-chip 64-stage FIFO buffers for transmission and reception
I C bus interface •
2
Supports multi master transmission/reception
(IIC)
Serial I/O with • Includes a 64-byte FIFO for transmission and another for reception
FIFO
• Supports 8-/16-/16-bit stereo sound input/output
(SIOF0, SIOF1)
• Sampling rate clock input selectable from Pφ and external pin
• Includes a prescaler for Pφ
• Interrupt requests and DMAC requests
Analog front end • STLC7550 can directly be connected
interface (AFEIF)
• Data access arrangement function
• 128-word transmit FIFO
• 128-word receive FIFO
Item Features
USB host • Conforms to OHCI Rev. 1.0
controller (USBH)
• USB Rev. 1.1 compatible
• 127 endpoints
• Support interrupt/bulk/control/isochronous mode
• Bus master controller (can access area 3 and synchronous DRAM)
• Two ports with analog transceiver (one is common with USB function
controller)
• External clock input function
USB function • Conforms to OHCI Rev. 1.0
controller (USBF)
• Six endpoints
• Support interrupt/bulk/control/isochronous mode
• One port with analog transceiver (common with USB function controller),
12 Mbps only
• External clock input function
LCD controller • From 16 × 1 to 1024 × 1024 pixels can be supported
(LCDC)
• 4/8/15/16 bpp (bit per pixel) color pallet
• 1/2/4/6 bpp (bit per pixel) gray scale
• 8-bit frame rate controller
• TFT/DSTN/STN panels
• Signal polarity setting function
• Hardware panel rotation
• Power control function
• Selectable clock source (LCLK, Bclk, or Pclk)
A/D converter • 10 bits ± 4 LSB, four channels
(ADC)
• Conversion time: 15 µs
• Input range: 0 to AVCC (max. 3.6 V)
D/A converter • 8 bits ± 4 LSB, two channels
(DAC)
• Conversion time: 10 µs
• Output range: 0 to AVCC (max. 3.6 V)
PC card • Complies with the PCMCIA Rev.2.1/JEIDA Version 4.2
controller (PCC)
• Supports the IC memory card interface and I/O card interface
Item Features
SIM card • Single channel ready for ISO7816-3 data protocol (T = 0, T = 1)
interface (SIM)
• Asynchronous half-duplex character transmission protocol
• Data length of 8 bits
• Generates and checks a parity bit
• Number of output clocks per 1 etu selectable
• Direct convention/inverse convention selectable
• Internal prescaler for Pφ
• Clock polarity changeable at idle time (low or high)
• With interrupt request and DMAC request
MultiMedia Card • Complies with The MultiMedia Card System Specification Version 3.1
interface
• Supports MMC mode
(MMCIF)
• 16.5-Mbps bit rate (max) for the card interface (Pφ = 33 MHz)
• Incorporates sixty-four 16-bit data-transfer FIFOs
• Interrupt and DMA request
• Module standby function
SD host interface • Supports SDHC (SD High Capacity) and SDIO
(SDHI)
Supports Part 1 Physical Layer Ver.1.01 to 2.0 of SD Specification, but
Note: Only for not supported for High-Speed
models with the
SDHI Supports Part E1 SDIO Ver. 1.00 to 2.00 of SD Specification
• SD memory/IO card interface (1 bit/4 bits SD bus)
• SD clock frequency ≤ 1/2 peripheral clock frequency
• Error check function: CRC7 (command/response), CRC16 (data)
• MMC (MultiMedia Card) access
• Interrupt request and DAMC transfer request (SD_BUF read/write)
• Card detection function
• Write protect
SSL accelerator • RSA encryption
(SSL)
• Supported operations: addition, subtraction, multiplication, power operation
Note: SH7720
• DES and Triple-DES encryption/decryption
group only
Item Features
User break • Two break channels
controller (UBC)
• All of address, data value, access type, and data size can be set as break
conditions.
• Supports sequential break function
User debugging • Supports E10A emulator
interface (H-UDI)
• Realtime branch trace
• 1-kbyte on-chip memory for executing high-speed emulation program
Power Supply
Voltage
Operating
Model I/O Internal Frequency Product Code Package SSL SDHI
Power Supply
Voltage
Operating
Model I/O Internal Frequency Product Code Package SSL SDHI
CPU bus
X bus
Y bus
Cache Memory
X/Y memory Cache access
memory management
Instruction/data for controller (CCN)
(32 kbytes) unit (MMU)
CPU/DSP (16 kbytes)
Internal bus Internal bus
Serial communication Serial communication Analog front end Compare 16-bit A/D D/A
576-byte USB function controller
interface 0 with FIFO interface 1 with FIFO I2C match timer pulse converter converter
128-byte FIFO SRAM interface (AFEIF) 1-kbyte FIFO (USBF)
128-byte FIFO (SCIF1) timer (CMT) unit (TPU) (ADC) (DAC)
(SCIF0/IrDA)
LCD_DATA15/ LCD_DATA11/ LCD_DATA7/ LCD_DATA3/ LCD_FLM/ LCD_M_DISP/ SIOF0_MCLK/ USB2_pwr_en/ AN2/PTF3 USB2_M USB1_P USB1_M AVcc_USB VccQ
Vcc_PLL2 MD2 XTAL RESETM MD4 DA1/PTF6
B PINT15/PTD7 PTD3 PTC7 PTC3 PTE0 PTE4 PTS3 PTH1
USB1d_TXDPLS/
Vcc_PLL1 MD1 MD5 EXTAL MD3 LCD_DATA12/ LCD_DATA9/ LCD_DATA6/ LCD_DATA2/ LCD_DON/ SIOF0_SYNC/ SIOF0_TxD/ SIOF0_SCK/ AFE_SCLK/IOIS16/ USB1_ovr_current/ EXTAL_USB
ADTRG/PTF0 AN3/PTF4 USB2_P AVcc PCC_IOIS16/
C PINT12/PTD4 PTD1 PTC6 PTC2 PTE1 PTS4 PTS2 PTS0 USBF_VBUS
PTG4
USB1d_DMNS/ USB1d_SUSPEND/ USB1d_TXENL/
STATUS0/ LCD_DATA14/ LCD_DATA10/ LCD_DATA8/ LCD_DATA4/ LCD_DATA0/ LCD_CL1/ SIOF0_RxD/ PINT11/
VssQ1 MD0 D31/PTB7 Vss Vcc USB2_ovr_current DA0/PTF5 AN1/PTF2 AFE_RLYCNT/ REFOUT/ XTAL_USB PINT8/
D PTH2 PINT14/PTD6 PTD2 PTD0 PTC4 PTC0 PTE3 PTS1
PCC_BVD2/PTG3 IRQOUT/PTP4 PCC_CD1/PTG0
Figure 1.2
USB1d_RCV/ USB1d_TXSE0/
USB1d_SPEED/
IRQ5/AFE_FS/ IRQ4/
E VccQ1 Vss_PLL2 Vss_PLL1 D30/PTB6 PINT9/PCC_CD2/ AFE_TXOUT/ VssQ
PCC_REG/ PCC_DRV/
PTG1
PTG6 PTG5
MMC_VDDON/ AFE_RDET/ USB1d_DPLS/
D24/PTB0 D29/PTB5 D28/PTB4 D27/PTB3 SCIF1_CTS/ PINT10/
F LCD_VEPWC/ IIC_SDA/ AFE_HC1/ VccQ
INDEX TPU_TO3/PTV4 PTE5 PCC_BVD1/PTG2
MMC_ODMOD/ AFE_RXIN/ SIM_CLK/
VssQ1 D26/PTB2 D25/PTB1 Vcc Vss SCIF1_RTS/ SCIF1_SCK/
G LCD_VCPWC/ IIC_SCL/
TPU_TO2/PTV3 PTE6 SD_DAT3/PTV0
Rev. 3.00
VccQ1 A11 A13 A15 AUDSYNC/
R ASEMD0 TRST/PTL7 VccQ
PTJ0
PINT7/
ASEBRKAK/
A16 A6 A5 A12 TMS/PTL6 TCK/PTL3 PCC_RESET/
T PTJ5
PTK3
PINT6/
VssQ1 A9 A4 A10 D11 D8 D4 D1 Vcc Vss BACK BS A19/PTR1 A22/PTR4 A24/PTR6 DACK0/ DREQ1/PTM7 TDI/PTL4 PCC_RDY/ TDO/PTL5
U PINT1/PTM4 PTK2
PINT4/
Section 1
VssQ1 VccQ1 D13 VssQ1 VccQ1 D5 VssQ1 VccQ1 CS6A/CE2B VssQ1 VssQ1 CS0 RD VssQ1 VccQ1 VssQ1 VccQ1 DACK1/PTM5 CA Vcc_RTC
Y
Overview
REJ09B0033-0300
Page 11 of 1458
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21
Section 1
USB1d_DMNS/
Rev. 3.00
LCD_DATA14/ LCD_DATA10/ LCD_DATA8/ LCD_DATA4/ LCD_DATA0/ SIOF0_SYNC/ SIOF0_TxD/ SIOF0_SCK/ PINT11/
MD1 VssQ EXTAL MD4 RESETM VssQ AVss AN0/PTF1 USB2_M USB1_P AVcc_USB USB1_M
A PINT14/PTD6 PTD2 PTD0 PTC4 PTC0 PTS4 PTS2 PTS0 AFE_RLYCNT/
PCC_BVD2/PTG3
REJ09B0033-0300
AFE_RDET/ USB1d_SUSPEND/
LCD_DATA15/ REFOUT/IRQOUT/
C D31/PTB7 IIC_SDA/
PINT15/PTD7 PTP4
PTE5
Overview
Figure 1.3
LCD_DATA7/ LCD_DATA5/ LCD_DATA1/ LCD_FLM/ LCD_CL1/ SIOF0_MCLK/ USB2_pwr_en/ ADTRG/
E Vss_PLL2 D29/PTB5 Vcc_PLL2 D25/PTB1 VssQ VccQ LCD_CLK VccQ AFE_SCLK/IOIS16/ VccQ EXTAL_USB
PTC7 PTC5 PTC1 PTE0 PTE3 PTS3 PTH1 PTF0
PCC_IOIS16/PTG4
MMC_VDDON/ USB1d_DPLS/ USB1d_TXENL/
SCIF1_CTS/ PINT10/AFE_HC1/ PINT8/
F VssQ1 D26/PTB2 Vss_PLL1 D22/PTA6 LCD_VEPWC/ XTAL_USB PCC_BVD1/PTG2 PCC_CD1/
TPU_TO3/PTV4 /PTG0
USB1d_SPEED/ AFE_RXIN/
G VccQ1 D24/PTB0 D30/PTB6 Vss Vss PINT9/ IIC_SCL/ VssQ
INDEX PCC_CD2/PTG1 PTE6
SIM_RST/ MMC_ODMOD/ SIM_D/
SD_WP/ SCIF1_RTS/ VccQ SCIF1_TxD/
D23/PTA7 VssQ1 D27/PTB3 D19/PTA3 LCD_VCPWC/
Page 12 of 1458
H SCIF1_RxD/PTV1 SD_CD/PTV2
TPU_TO2/PTV3
SIOF1_MCLK/ SIM_CLK/ SIOF1_SYNC/
SCIF1_SCK/
J VccQ1 D20/PTA4 Vcc D18/PTA2 SD_DAT1/ Vcc SD_DAT3/ SD_DAT2/
TPU_TI3B/PTU3 PTV0 PTU4
MMC_CMD/ SCIF0_CTS/ MMC_DAT/ MMC_CLK/
SIOF1_RxD/ SIOF1_TxD/ SIOF1_SCK/
K VssQ1 D17/PTA1 D21/PTA5 CKIO SH7330 SD_CMD/ TPU_TO1/ SD_DAT0/ SD_CLK/
TPU_TI2B/PTU1 PTT4 TPU_TI3A/PTU2 TPU_TI2A/PTU0
PLBG0256KA-A SCIF0_RTS/ SCIF0_TxD/ SCIF0_RxD/
VccQ1 CAS/PTH5 D16/PTA0 RD/WR TPU_TO0/ VccQ
L (BP-256C/CV) IrTX/PTT2 IrRX/PTT1
PTT3
WE2/ WE3/
(Top view) IRQ0/IRL0/ IRQ3/IRL3/ IRQ1/IRL1/
DQMUL/ RAS/PTH6 DQMUU/ CKE/PTH4 VssQ
M PTP0 PTP3 PTP1
ICIORD ICIOWR
WE1/
WE0/ VssQ1 Vcc SCIF0_SCK/ AUDATA1/ NMI
N DQMLU/ Vss
DQMLL PTT0 PTJ2
WE
AUDATA3/ AUDATA0/
R A15 A13 VssQ1 Vss PTJ4
TRST/PTL7 ASEMD0
PTJ1
PINT7/
WAIT/
U VccQ1 A8 A7 D15 VssQ1 VccQ1 CS6A/CE2B CS5A/CE2A VccQ1 BACK BS A20/PTR2 A22/PTR4 A24/PTR6 VccQ VccQ TMS/PTL6 PCC_RESET/
PCC_WAIT
PTK3
DACK0/ PINT6/
CS6B/CE1B/ A19/PTR1 TEND1/PINT3/ ASEBRKAK/
A6 A5 VccQ1 VccQ1 D13 D10 D7 D3 Vss BREQ A23/PTR5 PINT1/ RESETP VssQ PCC_RDY/
V PTM0 PTM3 PTJ5
PTM4 PTK2
DREQ0/ PINT4/
CS5B/CE1A/ TEND0/PINT2/ PINT0/
VssQ1 A3 VssQ1 D14 D11 D8 D6 D2 D0 CS0 RD VssQ1 VccQ1 A25/PTR7 CA EXTAL_RTC Vss_RTC PCC_VS1/
Y PTM1 PTM2 PTM6 PTK0
PINT5/
DACK1/
AA A1 A2 A10 A0/PTR0 D15 D12 D9 D4 D1 Vcc VssQ1 CS4 A18 A21/PTR3 VssQ1 VccQ1 VccQ_RTC XTAL_RTC Vcc_RTC PCC_VS2/
PTM5
PTK1
Section 1 Overview
Section 2 CPU
This LSI supports four types of processing states: a reset state, an exception handling state, a
program execution state, and a low-power consumption state, according to the CPU processing
states.
In the reset state, the CPU is reset. The LSI supports two types of resets: power-on reset and
manual reset. For details on resets, refer to section 7, Exception Handling.
In power-on reset, the registers and internal statuses of all LSI on-chip modules are initialized. In
manual reset, the register contents of a part of the LSI on-chip modules are retained. For details,
refer to section 37, List of Registers. The CPU internal statuses and registers are initialized both in
power-on reset and manual reset. After initialization, the program branches to address
H'A0000000 to pass control to the reset processing program to be executed.
In the exception handling state, the CPU processing flow is changed temporarily by a general
exception or interrupt exception processing. The program counter (PC) and status register (SR) are
saved in the save program counter (SPC) and save status register (SSR), respectively. The program
branches to an address obtained by adding a vector offset to the vector base register (VBR) and
passes control to the exception processing program defined by the user to be executed. For details
on reset, refer to section 7, Exception Handling.
The CPU stops operation to reduce power consumption. The power-down mode can be entered by
executing the SLEEP instruction. For details on the power-down mode, refer to section 13, Power-
Down Modes.
This LSI supports two processing modes: user mode and privileged mode. These processing
modes can be determined by the processing mode bit (MD) in the status register (SR). If the MD
bit is cleared to 0, the user mode is selected. If the MD bit is set to 1, the privileged mode is
selected. The CPU enters the privileged mode by a transition to reset state or exception handling
state. In the privileged mode, any registers and resources in address spaces can be accessed.
Clearing the MD bit in the SR to 0 puts the CPU in the user mode. In the user mode, some of the
registers, including SR, and some of the address spaces cannot be accessed by the user program
and system control instructions cannot be executed. This function effectively protects the system
resources from the user program. To change the processing mode from user to privileged mode, a
transition to exception handling state is required.
Note: To call a service routine used in privileged mode from user mode, the LSI supports an
unconditional trap instruction (TRAPA). When a transition from user mode to privileged
mode occurs, the contents of the SR and PC are saved. A program execution in user mode
can be resumed by restoring the contents of the SR and PC. To return from an exception
processing program, the LSI supports an RTE instruction.
Exception
handling
Multiple routine starts SLEEP instruction
exceptions An exception
is accepted
Low-power
Exception handling state
An exception consumption state
is accepted
The LSI supports 32-bit virtual addresses and accesses system resources using the 4-Gbytes of
virtual address space. User programs and data are accessed from the virtual address space. The
virtual address space is divided into several areas as shown in table 2.1.
This area is called the P0 area when the CPU is in privileged mode and the U0 area when in user
mode. For the P0 and U0 areas, access using the cache is enabled. The P0 and U0 areas are
handled as address translatable areas.
If the CPU is in user mode, only the U0 area can be accessed. If P1, P2, P3, or P4 is accessed in
user mode, a transition to an address error exception occurs.
(2) P1 Area
The P1 area is defined as a cacheable but non-address translatable area. Normally, programs
executed at high speed in privileged mode, such as exception processing handlers, which are at the
core of the operating system (OS), are assigned to the P1 area.
(3) P2 Area
The P2 area is defined as a non-cacheable but non-address translatable area. A reset processing
program to be called from the reset state is described at the start address (H'A0000000) of the P2
area. Normally, programs such as system initialization routines and OS initiation programs are
assigned to the P2 area. To access a part of an on-chip I/O, its corresponding program should be
assigned to the P2 area.
(4) P3 Area
The P3 area is defined as a cacheable and address translatable area. This area is used if an address
translation is required for a privileged program.
(5) P4 Area
The P4 area is defined as a control area which is non-cacheable and non-address translatable. This
area can be accessed only in privileged mode. A part of the LSI’s on-chip I/O is assigned to this
area.
This LSI uses 29 bits of the 32-bit virtual address to access external memory. In this case, 0.5-
Gbyte of external memory space can be accessed. The external memory space is managed in area
units. Different types of memory can be connected to each area, as shown in figure 2.2. For
details, please refer to section 9, Bus State Controller (BSC).
In addition, area 1 in the external memory space is used as an on-chip I/O space where most of this
LSI’s on-chip I/Os are mapped.
Normally, the upper three bits of the 32-bit virtual address are masked and the lower 29 bits are
used for external memory addresses.*2 For example, address H'00000100 in the P0 area, address
H'80000100 in the P1 area, address H'A0000100 in the P2 area, and address H'C0000100 in the P3
area of the virtual address space are mapped into address H'00000100 of area 0 in the external
memory space. The P4 area in the virtual address space is not mapped into the external memory
address. If an address in the P4 area is accessed, an external memory cannot be accessed.
Notes: 1. To access an on-chip I/O mapped into area 1 in the external memory space, access the
address from the P2 area which is not cached in the virtual address space.
2. If the address translation unit is enabled, arbitrary mapping in page units can be
specified. For details, refer to section 4, Memory Management Unit (MMU).
P1 area
H'A000 0000
P2 area
H'C000 0000 Address error
P3 area
H'E000 0000
P4 area
H'FFFF FFFF H'FFFF FFFF
Privileged mode User mode
This LSI incorporates the multiply and accumulate registers (MACH/MACL) and procedure
register (PR) as system registers. These registers can be accessed regardless of the processing
mode.
The program counter stores the value obtained by adding 4 to the current instruction address.
This LSI incorporates the status register (SR), global base register (GBR), save status register
(SSR), save program counter (SPC), and vector base register as control register. Only the GBR can
be accessed in user mode. Control registers other than the GBR can be accessed only in privileged
mode.
Table 2.2 shows the register values after reset. Figure 2.3 shows the register configurations in each
process mode.
31 0 31 0 31 0
R0_BANK0*1,*2 R0_BANK1*1,*3 R0_BANK0*1,*4
R1_BANK0*2 R1_BANK1*3 R1_BANK0*4
R2_BANK0*2 R2_BANK1*3 R2_BANK0*4
R3_BANK0*2 R3_BANK1*3 R3_BANK0*4
R4_BANK0*2 R4_BANK1*3 R4_BANK0*4
R5_BANK0*2 R5_BANK1*3 R5_BANK0*4
R6_BANK0*2 R6_BANK1*3 R6_BANK0*4
R7_BANK0*2 R7_BANK1*3 R7_BANK0*4
R8 R8 R8
R9 R9 R9
R10 R10 R10
R11 R11 R11
R12 R12 R12
R13 R13 R13
R14 R14 R14
R15 R15 R15
SR SR SR
SSR SSR
PC PC PC
SPC SPC
R0_BANK0*1,*4 R0_BANK1*1,*3
R1_BANK0*4 R1_BANK1*3
R2_BANK0*4 R2_BANK1*3
R3_BANK0*4 R3_BANK1*3
R4_BANK0*4 R4_BANK1*3
R5_BANK0*4 R5_BANK1*3
R6_BANK0*4 R6_BANK1*3
R7_BANK0*4 R7_BANK1*3
(a) User mode register (b) Privileged mode register (c) Privileged mode register
configuration configuration (RB = 1) configuration (RB = 0)
Notes: 1. The R0 register is used as an index register in indexed register indirect addressing mode
and indexed GBR indirect addressing mode.
2. Bank register
3. Bank register
Accessed as a general register when the RB bit is set to 1 in the SR register.
Accessed only by LDC/STC instructions when the RB bit is cleared to 0.
4. Bank register
Accessed as a general register when the RB bit is cleared to 0 in the SR register.
Accessed only by LDC/STC instructions when the RB bit is set to 1.
In user mode, bank 0 is selected regardless of the RB bit value. Sixteen registers: R0_BANK0 to
R7_BANK0 and R8 to R15 are accessed as general registers R0 to R15. The R0_BANK1 to
R7_BANK1 registers in bank 1 cannot be accessed.
In privileged mode that is entered by a transition to exception handling state, the RB bit is set to 1
to select bank 1. In privileged mode, sixteen registers: R0_BANK1 to R7_BANK1 and R8 to R15
are accessed as general registers R0 to R15. A bank is switched automatically when an exception
handling state is entered, registers R0 to R7 need not be saved by the exception handling routine.
The R0_BANK0 to R7_BANK0 registers in bank 0 can be accessed as R0_BANK to R7_BANK
by the LDC and STC instructions.
In privileged mode, bank 0 can also be used as general registers by clearing the RB bit to 0. In this
case, sixteen registers: R0_BANK0 to R7_BANK0 and R8 to R15 are accessed as general
registers R0 to R15. The R0_BANK1 to R7_BANK1 registers in bank 1 can be accessed as
R0_BANK to R7_BANK by the LDC and STC instructions.
The general registers R0 to R15 are used as equivalent registers for almost all instructions. In
some instructions, the R0 register is automatically used or only the R0 register can be used as
source or destination registers.
31 0
R0*1,*2 General Registers: Undefined after reset
R1*2
R2*2 Notes: 1. R0 functions as an index register in the indexed
register-indirect addressing mode and indexed
R3*2
GBR-indirect addressing mode. In some
R4*2
instructions, only R0 can be used as the source
R5*2 or destination register.
R6*2 2. R0 to R7 are banked registers. In privileged
R7*2 mode, either R0_BANK0 to R7_BANK0 or
R8 R0_BANK1 to R7_BANK1 is selected by the
RB bit in the SR register.
R9
R10
R11
R12
R13
R14
R15
The system registers: multiply and accumulate registers (MACH/MACL) and procedure register
(PR) as system registers can be accessed by the LDS and STS instructions.
The multiply and accumulate registers (MACH/MACL) store the results of multiplication and
accumulation instructions or multiplication instructions. The MACH/MACL registers also store
addition values for the multiplication and accumulations. After reset, these registers are undefined.
The MACH and MACL registers store upper 32 bits and lower 32 bits, respectively.
The procedure register (PR) stores the return address for a subroutine call using the BSR, BSRF,
or JSR instruction. The return address stored in the PR register is restored to the program counter
(PC) by the RTS (return from the subroutine) instruction. After reset, this register is undefined.
The program counter (PC) stores the value obtained by adding 4 to the current instruction address.
There is no instruction to read the PC directly. Before an exception handling state is entered, the
PC is saved in the save program counter (SPC). Before a subroutine call is executed, the PC is
saved in the procedure register (PR). In addition, the PC can be used for PC relative addressing
mode.
Figure 2.5 shows the system register and program counter configurations.
31 0
MACH
MACL
PR
PC
The control registers (SR, SSR, SPC, GBR, and VBR) can be accessed by the LDC or STC
instruction in privileged mode. The GBR register can be accessed in the user mode.
The status register (SR) indicates the system status as shown below. The SR register can be
accessed only in privileged mode.
Initial
Bit Bit Name Value R/W Description
31 0 R Reserved
This bit is always read as 0. The write value should
always be 0.
30 MD 1 R/W Processing Mode
Indicates the CPU processing mode.
0: User mode
1: Privileged mode
The MD bit is set to 1 in reset or exception handling
state.
29 RB 1 R/W Register Bank
The general registers R0 to R7 are banked registers.
0: In this case, R0_BANK0 to R7_BANK0 and R8 to
R15 are used as general registers.
R0_BANK1 to R7_BANK1 can be accessed by the
LDC or STR instruction.
1: In this case, R0_BANK1 to R7_BANK1 and R8 to
R15 are used as general registers.
R0_BANK0 to R7_BANK0 can be accessed by the
LDC or STR instruction.
The RB bit is set to 1 in reset or exception handling
state.
Initial
Bit Bit Name Value R/W Description
28 BL 1 R/W Block
Specifies whether an exception, interrupt, or user
break is enabled or not.
0: Enables an exception, interrupt, or user break.
1: Disables an exception, interrupt, or user break.
The BL bit is set to 1 in reset or exception handling
state.
27 to 10 All 0 R Reserved
These bits are always read as 0. The write value
should always be 0.
9 M R/W M Bit
8 Q R/W Q Bit
These bits are used by the DIV0S, DIV0U, and DIV1
instructions. These bits can be changed even in user
mode by using the DIV0S, DIV0U, and DIV1
instructions. These bits are undefined at reset. These
bits do not change in an exception handling state.
7 to 4 I3 to I0 All 1 R/W Interrupt Mask
Indicates the interrupt mask level. These bits do not
change even if an interrupt occurs. At reset, these bits
are initialized to B'1111. These bits are not affected in
an exception handling state.
3, 2 All 0 R Reserved
These bits are always read as 0. The write value
should always be 0.
1 S R/W Saturation Mode
Specifies the saturation mode for multiply instructions
or multiply and accumulate instructions. This bit can be
specified by the SETS and CLRS instructions in user
mode.
At reset, this bit is undefined. This bit is not affected in
an exception handling state.
Initial
Bit Bit Name Value R/W Description
0 T R/W T Bit
Indicates true or false for compare instructions or carry
or borrow occurrence for an operation instruction with
carry or borrow. This bit can be specified by the SETT
and CLRT instructions in user mode.
At reset, this bit is undefined. This bit is not affected in
an exception handling state.
Note: The M, Q, S, and T bits can be set/cleared by the user mode specific instructions. Other bits
can be read or written in privileged mode.
The save status register (SSR) can be accessed only in privileged mode. Before entering the
exception, the contents of the SR register is stored in the SSR register. At reset, the SSR initial
value is undefined.
The save program counter (SPC) can be accessed only in privileged mode. Before entering the
exception, the contents of the PC is stored in the SPC. At reset, the SPC initial value is undefined.
The global base register (GBR) is referenced as a base register in GBR indirect addressing mode.
At reset, the GBR initial value is undefined.
The vector base register (VBR) can be accessed only in privileged mode. If a transition from reset
state to exception handling state occurs, this register is referenced as a base address. For details,
refer to section 7, Exception Handling. At reset, the VBR is initialized as H'00000000.
Register operands are always longwords (32 bits). When the memory operand is only a byte (8
bits) or a word (16 bits), it is sign-extended into a longword when loaded into a register.
31 0
Longword
Memory data formats are classified into byte, word, and longword. Memory can be accessed in
byte, word, and longword. When the memory operand is only a byte (8 bits) or a word (16 bits), it
is sign-extended into a longword when loaded into a register.
An address error will occur if word data starting from an address other than 2n or longword data
starting from an address other than 4n is accessed. In such cases, the data accessed cannot be
guaranteed.
When a word or longword operand is accessed, the byte positions on the memory corresponding to
the word or longword data on the register is determined to the specified endian mode (big endian
or little endian).
Figure 2.7 shows a byte correspondence in big endian mode. In big endian mode, the MSB byte in
the register corresponds to the lowest address in the memory, and the LSB the in the register
corresponds to the highest address. For example, if the contents of the general register R0 is stored
at an address indicated by the general register R1 in longword, the MSB byte of the R0 is stored at
the address indicated by the R1 and the LSB byte of the R1 register is stored at the address
indicated by the (R1 +3).
The on-chip device registers assigned to memory are accessed in big endian mode. Note that the
available access size (byte, word, or long word) differs in each register.
Note: The CPU instruction codes of this LSI must be stored in word units. In big endian mode,
the instruction code must be stored from upper byte to lower byte in this order from the
word boundary of the memory.
31 23 15 7 0
Byte position
in R0 [7:0] [15:8] [7:0] [31:24] [23:16] [15:8] [7:0]
Byte position
[7:0] [15:8] [7:0] [31:24] [23:16] [15:8] [7:0]
in memory
@(R1+0) @(R1+1) @(R1+2) @(R1+3) @(R1+0) @(R1+1) @(R1+2) @(R1+3) @(R1+0) @(R1+1) @(R1+2) @(R1+3)
The little endian mode can also be specified as data format. Either big-endian or little-endian mode
can be selected according to the MD5 pin at reset. When MD5 is low at reset, the processor
operates in big-endian mode. When MD5 is high at reset, the processor operates in little-endian
mode. The endian mode cannot be modified dynamically.
In little endian mode, the MSB byte in the register corresponds to the highest address in the
memory, and the LSB the in the register corresponds to the lowest address (figure 2.8). For
example, if the contents of the general register R0 is stored at an address indicated by the general
register R1 in longword, the MSB byte of the R0 is stored at the address indicated by the (R1+3)
and the LSB byte of the R1 register is stored at the address indicated by the R1.
If the little endian mode is selected, the on-chip memory are accessed in little endian mode.
However, the on-chip device registers assigned to memory are accessed in big endian mode. Note
that the available access size (byte, word, or long word) differs in each register.
Note: The CPU instruction codes of this LSI must be stored in word units. In little endian mode,
the instruction code must be stored from lower byte to upper byte in this order from the
word boundary of the memory.
31 23 15 7 0
Byte position
in R0 [7:0] [15:8] [7:0] [31:24] [23:16] [15:8] [7:0]
Byte position
[7:0] [15:8] [7:0] [31:24] [23:16] [15:8] [7:0]
in memory
@(R1+3) @(R1+2) @(R1+1) @(R1+0) @(R1+3) @(R1+2) @(R1+1) @(R1+0) @(R1+3) @(R1+2) @(R1+1) @(R1+0)
All instructions have a fixed length of 16 bits and are executed in the sequential pipeline. In the
sequential pipeline, almost all instructions can be executed in one cycle. All data items are handles
in longword (32 bits). Memory can be accessed in byte, word, or longword. In this case, Memory
byte or word data is sign-extended and operated on as longword data. Immediate data is sign-
extended to longword size for arithmetic operations (MOV, ADD, and CMP/EQ instructions) or
zero-extended to longword size for logical operations (TST, AND, OR, and XOR instructions).
Basic operations are executed between registers. In operations involving memory, data is first
loaded into a register (load/store architecture). However, bit manipulation instructions such as
AND are executed directly on memory.
Unconditional branch instructions are executed as delayed branches. With a delayed branch
instruction, the branch is made after execution of the instruction (called the slot instruction)
immediately following the delayed branch instruction. This minimizes disruption of the pipeline
when a branch is made.
This LSI supports two types of conditional branch instructions: delayed branch instruction or
normal branch instruction.
(4) T Bit
The result of a comparison is indicated by the T bit in the status register (SR), and a conditional
branch is performed according to whether the result is True or False. Processing speed has been
improved by keeping the number of instructions that modify the T bit to a minimum.
Byte literal constant is placed inside the instruction code as immediate data. Since the instruction
length is fixed to 16 bits, word and longword literal constant is not placed inside the instruction
code, but in a table in memory. The table in memory is referenced with a MOV instruction using
PC-relative addressing mode with displacement.
When data is referenced by absolute address, the absolute address value is placed in a table in
memory beforehand as well as word or longword literal constant. Using the method whereby
immediate data is loaded when an instruction is executed, this value is transferred to a register and
the data is referenced using register indirect addressing mode.
When data is referenced with a 16- or 32-bit displacement, the displacement value is placed in a
table in memory beforehand. Using the method whereby word or longword immediate data is
loaded when an instruction is executed, this value is transferred to a register and the data is
referenced using indexed register indirect addressing mode.
The following table shows addressing modes and effective address calculation methods for
instructions executed by the CPU core.
Table 2.3 Addressing Modes and Effective Addresses for CPU Instructions
Addressing Instruction
Mode Format Effective Address Calculation Method Calculation Formula
Rn Rn Word: Rn + 2 → Rn
Rn + 1/2/4
+
Longword: Rn + 4 → Rn
1/2/4
1/2/4
Addressing Instruction
Mode Format Effective Address Calculation Method Calculation Formula
Register @(disp:4, Effective address is register Rn contents with 4-bit Byte: Rn + disp
indirect with Rn) displacement disp added. After disp is zero-
Word: Rn + disp × 2
displacement extended, it is multiplied by 1 (byte), 2 (word), or 4
(longword), according to the operand size. Longword: Rn + disp × 4
Rn
Rn
disp +
+ disp × 1/2/4
(zero-extended)
×
1/2/4
+ Rn + R0
R0
GBR indirect with @(disp:8, Effective address is register GBR contents with 8- Byte: GBR + disp
displacement GBR) bit displacement disp added. After disp is zero- Word: GBR + disp × 2
extended, it is multiplied by 1 (byte), 2 (word), or 4
(longword), according to the Longword:
operand size. GBR + disp × 4
GBR
disp GBR
+
(Zero-extended) + disp × 1/2/4
×
1/2/4
Indexed GBR @(R0, GBR) Effective address is sum of register GBR and R0 GBR + R0
indirect contents.
GBR
+ GBR + R0
R0
Addressing Instruction
Mode Format Effective Address Calculation Method Calculation Formula
PC-relative with @(disp:8, Effective address is PC with 8-bit displacement disp Word: PC + disp × 2
displacement PC) added. After disp is zero-extended, it is multiplied
Longword:
by 2 (word) or 4 (longword), according to the PC&H'FFFFFFFC
operand size. With a longword operand, the lower 2
+ disp × 4
bits of PC are masked.
PC
*
&
PC + disp × 2
H'FFFFFFFC or
+ PC &
disp H'FFFFFFFC
(zero-extended) + disp × 4
×
disp + PC + disp × 2
(sign-extended)
disp + PC + disp × 2
(sign-extended)
+ PC + Rn
Rn
Addressing Instruction
Mode Format Effective Address Calculation Method Calculation Formula
Table 2.4 shows the instruction formats, and the meaning of the source and destination operands,
for instructions executed by the CPU core. The meaning of the operands depends on the
instruction code. The following symbols are used in the table.
dddd: Displacement
Destination
Instruction Format Source Operand Operand Sample Instruction
0 type NOP
15 0
xxxx xxxx xxxx xxxx
Destination
Instruction Format Source Operand Operand Sample Instruction
nm type mmmm: register nnnn: register ADD Rm,Rn
15 0 direct direct
xxxx nnnn mmmm xxxx
Destination
Instruction Format Source Operand Operand Sample Instruction
d type dddddddd: GBR R0 (register direct) MOV.L @(disp,GBR),R0
15 0 indirect with
xxxx xxxx dddd dddd displacement
R0 (register direct) dddddddd: GBR MOV.L R0,@(disp,GBR)
indirect with
displacement
dddddddd: R0 (register direct) MOVA @(disp,PC),R0
PC-relative with
displacement
dddddddd: BF label
PC-relative
d12 type dddddddddddd: BRA label
15 0 PC-relative (label=disp+PC)
xxxx dddd dddd dddd
Kinds of Number of
Type Instruction Op Code Function Instructions
Data transfer 5 MOV Data transfer 39
instructions MOVA Effective address transfer
MOVT T bit transfer
SWAP Upper/lower swap
XTRCT Extraction of middle of linked registers
Arithmetic 21 ADD Binary addition 33
operation ADDC Binary addition with carry
instructions
ADDV Binary addition with overflow check
CMP/cond Comparison
DIV1 Division
DIV0S Signed division initialization
DIV0U Unsigned division initialization
DMULS Signed double-precision multiplication
DMULU Unsigned double-precision multiplication
DT Decrement and test
EXTS Sign extension
EXTU Zero extension
MAC Multiply-and-accumulate, double-
precision multiply-and-accumulate
MUL Double-precision multiplication
(32 × 32 bits)
Kinds of Number of
Type Instruction Op Code Function Instructions
Arithmetic 21 MULS Signed multiplication (16 × 16 bits) 33
operation MULU Unsigned multiplication (16 × 16 bits)
instructions
NEG Sign inversion
NEGC Sign inversion with borrow
SUB Binary subtraction
SUBC Binary subtraction with borrow
SUBV Binary subtraction with underflow
Logic 6 AND Logical AND 14
operation NOT Bit inversion
instructions
OR Logical OR
TAS Memory test and bit setting
TST Logical AND and T bit setting
XOR Exclusive logical OR
Shift 12 ROTCL 1-bit left shift with T bit 16
instructions ROTCR 1-bit right shift with T bit
ROTL 1-bit left shift
ROTR 1-bit right shift
SHAD Arithmetic dynamic shift
SHAL Arithmetic 1-bit left shift
SHAR Arithmetic 1-bit right shift
SHLD Logical dynamic shift
SHLL Logical 1-bit left shift
SHLLn Logical n-bit left shift
SHLR Logical 1-bit right shift
SHLRn Logical n-bit right shift
Kinds of Number of
Type Instruction Op Code Function Instructions
Branch 9 BF Conditional branch, delayed conditional 11
instructions branch (T = 0)
BT Conditional branch, delayed conditional
branch (T = 1)
BRA Unconditional branch
BRAF Unconditional branch
BSR Branch to subroutine procedure
BSRF Branch to subroutine procedure
JMP Unconditional branch
JSR Branch to subroutine procedure
RTS Return from subroutine procedure
System 15 CLRMAC MAC register clear 75
control
CLRS S bit clear
instructions
CLRT T bit clear
LDC Load into control register
LDS Load into system register
LDTLB PTEH/PTEL load into TLB
NOP No operation
PREF Data prefetch to cache
RTE Return from exception handling
SETS S bit setting
SETT T bit setting
SLEEP Transition to power-down mode
STC Store from control register
STS Store from system register
TRAPA Trap exception handling
Total: 68 188
The instruction code, operation, and number of execution states of the CPU instructions are shown
in the following tables, classified by instruction type, using the format shown below.
Execution
Instruction Instruction Code Operation Privilege States T Bit
Indicated by mnemonic. Indicated in MSB ↔ Indicates summary of Indicates a Value Value of T
LSB order. operation. privileged when no bit after
instruction. wait states instruction
are is executed
inserted*1
Explanation of Symbols Explanation of Symbols Explanation of Symbols Explanation
of Symbols
OP.Sz SRC, DEST mmmm: Source register →, ←: Transfer direction
OP: Operation code : No
nnnn: Destination register (xx): Memory operand
Sz: Size change
0000: R0
SRC: Source M/Q/T: Flag bits in SR
0001: R1
DEST: Destination .........
&: Logical AND of each bit
Rm: Source register 1111: R15
|: Logical OR of each bit
Rn: Destination register iiii: Immediate data
^: Exclusive logical OR of
imm: Immediate data dddd: Displacement*2 each bit
disp: Displacement ~: Logical NOT of each bit
<<n: n-bit left shift
>>n: n-bit right shift
Notes: 1. The table shows the minimum number of execution states. In practice, the number of
instruction execution states will be increased in cases such as the following:
a. When there is a conflict between an instruction fetch and a data access
b. When the destination register of a load instruction (memory → register) is also
used by the following instruction
2. Scaled (x1, x2, or x4) according to the instruction operand size, etc.
Privileged
Instruction Instruction Code Operation Mode Cycles T Bit
Privileged
Instruction Instruction Code Operation Mode Cycles T Bit
Privileged
Instruction Instruction Code Operation Mode Cycles T Bit
Privileged
Instruction Instruction Code Operation Mode Cycles T Bit
Privileged
Instruction Instruction Code Operation Mode Cycles T Bit
Privileged
Instruction Instruction Code Operation Mode Cycles T Bit
Privilege Cycle
Instruction Instruction Code Operation d Mode s T Bit
BF disp 10001011dddddddd If T = 0, disp × 2 + PC → PC; – 3/1* –
if T = 1, nop
BF/S disp 10001111dddddddd Delayed branch, – 2/1* –
if T = 0, disp × 2 + PC → PC;
if T = 1, nop
BT disp 10001001dddddddd If T = 1, disp × 2 + PC → PC; – 3/1* –
if T = 0, nop
BT/S disp 10001101dddddddd Delayed branch, – 2/1* –
if T = 1, disp × 2 + PC → PC;
if T = 0, nop
BRA disp 1010dddddddddddd Delayed branch, disp × 2 + PC – 2 –
→ PC
BRAF Rm 0000mmmm00100011 Delayed branch,Rm + PC → PC – 2 –
BSR disp 1011dddddddddddd Delayed branch, PC → PR, disp – 2 –
× 2 + PC → PC
BSRF Rm 0000mmmm00000011 Delayed branch, PC → PR, Rm – 2 –
+ PC → PC
JMP @Rm 0100mmmm00101011 Delayed branch, Rm → PC – 2 –
JSR @Rm 0100mmmm00001011 Delayed branch, PC → PR, Rm – 2 –
→ PC
RTS 0000000000001011 Delayed branch, PR → PC – 2 –
Note: * One state when the branch is not executed.
Privileged
Instruction Instruction Code Operation Mode Cycles T Bit
Privileged
Instruction Instruction Code Operation Mode Cycles T Bit
Instruction Privileged
Instruction Code Operation Mode Cycles T Bit
Instruction Code Fx: 0000 Fx: 0001 Fx: 0010 Fx: 0011 to 1111
0000 Rn Fx 0000
0000 Rn Fx 0001
0000 Rn 00MD 0010 STC SR, Rn STC GBR, Rn STC VBR, Rn STC SSR, Rn
0000 Rn 10MD 0010 STC R0_BANK, Rn STC R1_BANK, Rn STC R2_BANK, Rn STC R3_BANK, Rn
0000 Rn 11MD 0010 STC R4_BANK, Rn STC R5_BANK, Rn STC R6_BANK, Rn STC R7_BANK, Rn
0000 Rn Rm 01MD MOV.B Rm, @(R0, Rn) MOV.W Rm, @(R0, Rn) MOV.L Rm,@(R0, Rn) MUL.L Rm, Rn
0000 Rn Fx 1000
0000 Rn Fx 1011
0000 Rn Rm 11MD MOV. B @(R0, Rm), Rn MOV.W @(R0, Rm), Rn MOV.L @(R0, Rm), Rn MAC.L @Rm+,@Rn+
0010 Rn Rm 00MD MOV.B Rm, @Rn MOV.W Rm, @Rn MOV.L Rm, @Rn
0010 Rn Rm 01MD MOV.B Rm, @–Rn MOV.W Rm, @–Rn MOV.L Rm, @–Rn DIV0S Rm, Rn
Instruction Code Fx: 0000 Fx: 0001 Fx: 0010 Fx: 0011 to 1111
0010 Rn Rm 11MD CMP/STR Rm, Rn XTRCT Rm, Rn MULU.W Rm, Rn MULSW Rm, Rn
0011 Rn Rm 01MD DIV1 Rm, Rn DMULU.L Rm,Rn CMP/HI Rm, Rn CMP/GT Rm, Rn
0011 Rn Rm 11MD ADD Rm, Rn DMULS.L Rm,Rn ADDC Rm, Rn ADDV Rm, Rn
0100 Rn Fx 0010 STS.L MACH, @–Rn STS.L MACL, @–Rn STS.L PR, @–Rn
0100 Rn 00MD 0011 STC.L SR, @–Rn STC.L GBR, @–Rn STC.L VBR, @–Rn STC.L SSR, @–Rn
@Rm+, MACH
0100 Rm 00MD 0111 LDC.L @Rm+, SR LDC.L @Rm+, GBR LDC.L @Rm+, VBR LDC.L @Rm+, SSR
0100 Rm Fx 1010 LDS Rm, MACH LDS Rm, MACL LDS Rm, PR
Instruction Code Fx: 0000 Fx: 0001 Fx: 0010 Fx: 0011 to 1111
0100 Rm 00MD 1110 LDC Rm, SR LDC Rm, GBR LDC Rm, VBR LDC Rm, SSR
0100 Rm 10MD 1110 LDC Rm, R0_BANK LDC Rm, R1_BANK LDC Rm, R2_BANK LDC Rm, R3_BANK
0100 Rm 11MD 1110 LDC Rm, R4_BANK LDC Rm, R5_BANK LDC Rm, R6_BANK LDC Rm, R7_BANK
0110 Rn Rm 00MD MOV.B @Rm, Rn MOV.W @Rm, Rn MOV.L @Rm, Rn MOV Rm, Rn
0110 Rn Rm 01MD MOV.B @Rm+, Rn MOV.W @Rm+, Rn MOV.L @Rm+, Rn NOT Rm, Rn
0110 Rn Rm 10MD SWAP.B Rm, Rn SWAP.W Rm, Rn NEGC Rm, Rn NEG Rm, Rn
0110 Rn Rm 11MD EXTU.B Rm, Rn EXTU.W Rm, Rn EXTS.B Rm, Rn EXTS.W Rm, Rn
1100 10MD imm TST #imm: 8, R0 AND #imm: 8, R0 XOR #imm: 8, R0 OR #imm: 8, R0
#imm: 8, @(R0, GBR) #imm: 8, @(R0, GBR) #imm: 8, @(R0, GBR) #imm: 8, @(R0, GBR)
1111 ************
If the DSP extended function is enabled, the following extended system control instructions can be
used for the CPU.
• Repeat loop control instructions and repeat loop control register access instructions are added.
Looped programs can be executed efficiently by using the zero-overhead repeat control unit.
For details, refer to section 3.3, CPU Extended Instructions.
• Modulo addressing control instructions and control register access instructions are added.
Function allows access to data with a circular structure. For details, refer to section 3.4, DSP
Data Transfer Instructions.
• DSP unit register access instructions are added. Some of the DSP unit registers can be used in
the same way as the CPU system registers. For details, refer to section 3.4, DSP Data Transfer
Instructions.
(2) Data Transfer Instructions for Data Transfers between DSP Unit and On-Chip X/Y
Memory
Data transfer instructions for data transfers between the DSP unit and on-chip X/Y memory are
called double-data transfer instructions. Instruction codes for these double-transfer instructions are
16 bit codes as well as CPU instruction codes. These data transfer instructions perform data
transfers between the DSP unit and on-chip X/Y memory that is directly connected to the DSP
unit. These data transfer instructions can be described in combination with other DSP unit
operation instructions. For details, refer to section 3.4, DSP Data Transfer Instructions.
(3) Data Transfer Instructions for Data Transfers between DSP Unit Registers and All
Virtual Address Spaces
Data transfer instructions for data transfers between DSP unit registers and all virtual address
spaces are called single-data transfer instructions. Instruction codes for the double-transfer
instructions are 16 bit codes as well as CPU instruction codes. These data transfer instructions
performs data transfers between the DSP unit registers and all virtual address spaces. For details,
refer to section 3.4, DSP Data Transfer Instructions.
DSP unit operation instructions are called DSP data operation instructions. These instructions are
provided to execute digital signal processing operations at high speed using the DSP. Instruction
codes for these instructions are 32 bits. The DSP data operation instruction fields consist of two
fields: field A and field B. In field A, a function for double data transfer instructions can be
described. In field B, ALU operation instructions and multiply instructions can be described. The
instructions described in fields A and B can be executed in parallel. A maximum of four
instructions (ALU operation, multiply, and two data transfers) can be executed in parallel. For
details, refer to section 3.5, DSP Data Operation Instructions.
Notes: 1. 32-bit instruction codes are handled as two consecutive 16-bit instruction codes.
Accordingly, 32-bit instruction codes can be assigned to a word boundary. 32-bit
instruction codes must be stored in memory, upper word and lower word, in this order,
in word units.
2. In little endian, the upper and lower words must be stored in memory as data to be
accessed in word units.
15 12 11 0
0000
CPU core instruction
*
-
1110
15 10 9 0
15 10 9 0
31 26 25 16 15 0
DSP data operation instruction 111110 A Field B Field
The CPU processing modes can be extended using the mode bit (MD) and DSP bit (DSP) in the
status register (SR), as shown below.
Description
Access of Resources
Protected in Privileged Mode
or Privileged Instruction DSP Extended
MD DSP Processing Mode Execution Functions
0 0 User mode Prohibited Invalid
0 1 User DSP mode Prohibited Valid
1 0 Privileged mode Allowed Invalid
1 1 Privileged DSP mode Allowed Valid
As shown above, the extension of the DSP function by the DSP bit can be specified independently
of the control by the MD bit. Note, however, that the DSP bit can be modified only in privileged
mode. Before the DSP bit is modified, a transition to privileged mode or privileged DSP mode is
necessary.
In DSP mode, a part of the P2 area in the virtual address space can be accessed in user DSP mode.
When this area is accessed in user DSP mode, this area is referred to as a Uxy area. X/Y memory
is then assigned to this Uxy area. Accordingly, X/Y memory can also be accessed in user DSP
mode.
In DSP mode, the status register (SR) in the CPU unit is extended to add control bits and three
control registers: a repeat start register (SR), repeat end register (RE), and modulo register (MOD)
are added as control registers.
31 30 29 28 27 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Status Register
0 MD RB BL RC[11:0] 0 0 0 DSP DMY DMX M Q I3 I2 I1 I0 RF1 RF0 S T
(SR)
31 0
RS Repeat start register (RS)
31 0
31 16 15 0
In DSP mode, the following control bits are added to the status register (SR). These added bits are
called DSP extension bits. These DSP extension bits are valid only in DSP mode.
Initial
Bit Bit Name Value R/W Description
31 to 28 For details, refer to section 2, CPU.
27 to 16 RC11 to All 0 R/W Repeat Counter
RC0 Holds the number of repeat times in order to perform
loop control, and can be modified in privileged mode,
privileged DSP mode, or user DSP mode. At reset, this
bit is initialized to 0. This bit is not affected in the
exception handling state.
15 to 13 For details, refer to section 2, CPU.
12 DSP 0 R/W DSP Bit
Enables or disables the DSP extended functions. If
this bit is set to 1, the DSP extended functions are
enabled. This bit can be modified in privileged mode,
privileged DSP mode, or user DSP mode. At reset, this
bit is initialized to 0. This bit is not affected in the
exception handling state.
11 MDY 0 R/W Modulo Control Bits
10 MDX 0 R/W Enable or disable modulo addressing for X/Y memory
access. These bits can be modified in privileged mode,
privileged DSP mode, or user DSP mode. At reset,
these bits are initialized to 0. These bits are affected in
the exception handling state.
9 to 4 For details, refer to section 2, CPU.
3 FR1 0 R/W Repeat Flag Bits
2 FR0 0 R/W Used by repeat control instructions. These bits can be
modified in privileged mode, privileged DSP mode, or
user DSP mode. At reset, these bits are initialized to 0.
These bits are affected in the exception handling state.
1, 0 For details, refer to section 2, CPU.
Note: When data is written to the SR register, 0 should be written to bits that are specified as 0.
The repeat start register (RS) holds the start address of a loop repeat module that is controlled by
the repeat function. This register can be accessed in DSP mode. At reset, the initial value of this
register is undefined. This register is not affected in the exception handling state.
The repeat end register (RE) holds the end address of a loop repeat module that is controlled by
the repeat function. This register can be accessed in DSP mode. At reset, this register is initialized
to 0. This register is not affected in the exception handling state.
The modulo register stores the modulo end address and modulo start address for modulo
addressing in upper and lower 16 bits. The upper and lower 16 bits of the modulo register are
referred to as the ME register and MS register, respectively. This register can be accessed in DSP
mode. At reset, the initial value of this register is undefined. This register is not affected in the
exception handling state.
The above registers can be accessed by the control register load instruction (LDC) and store
instruction (STC). Note that the LDC and STC instructions for the RS, RE, and MOD registers can
be used only in privileged DSP mode and user DSP mode. The LDC and STC instruction for the
SR register can be executed only when the MD bit is set to 1 or in user DSP mode. Note, however,
that the LDC and STC instructions can modify only the RC11 to RC0, RF1 to RF0, DMX, and
DMY bits in the SR, as described below.
• In user mode, if the LCD and STC instructions are used for the RS, an illegal instruction
exception occurs.
• In privileged and privileged DSP modes, all SR bits can be modified.
• In user DSP mode, the SR can be read by the STC instruction.
• In user DSP mode, the LDC instruction can be issued to the SR but only the DSP extension
bits can be modified.
Access to
Privileged Privileged User DSP
DSP-Related
Mode User Mode DSP Mode Mode Bit with
MD = 1 & MD = 0 & MD = 1 & MD = 0 & Dedicated Initial Value
Field DSP = 0 DSP = 0 DSP = 1 DSP = 1 Instruction after Reset
MD S: OK, L: OK S, L: Invalid S: OK, L: OK S: OK, L: NG 1
instruction
RB S: OK, L: OK S, L: Invalid S: OK, L: OK S: OK, L: NG 1
instruction
BL S: OK, L: OK S, L: Invalid S: OK, L: OK S: OK, L: NG 1
instruction
RC [11:0] S: OK, L: OK S, L: Invalid S: OK, L: OK R: OK, L: OK SETRC 000000000000
instruction instruction
DSP S: OK, L: OK S, L: Invalid S: OK, L: OK S: OK, L: NG 0
instruction
DMY S: OK, L: OK S, L: Invalid S: OK, L: OK R: OK, L: OK 0
instruction
DMX S: OK, L: OK S, L: Invalid S: OK, L: OK R: OK, L: OK 0
instruction
Q S: OK, L: OK S, L: Invalid S: OK, L: OK S: OK, L: NG x
instruction
M S: OK, L: OK S, L: Invalid S: OK, L: OK S: OK, L: NG x
instruction
I[3:0] S: OK, L: OK S, L: Invalid S: OK, L: OK S: OK, L: NG 1111
instruction
RF[1:0] S: OK, L: OK S, L: Invalid S: OK, L: OK R: OK, L: OK SETRC x
instruction instruction
S S: OK, L: OK S, L: Invalid S: OK, L: OK S: OK, L: NG x
instruction
T S: OK, L: OK S, L: Invalid S: OK, L: OK S: OK, L: NG x
instruction
[Legend]
S: STC instruction
L: LDC instruction
OK: STC/LDC operation is enabled.
Invalid instruction: Exception occurs when an invalid instruction is executed.
NG: Previous value is retained. No change.
x: Undefined
Before entering the exception handling state, all bits including the DSP extension bits of the SR
registers are saved in the SSR. Before returning from the exception handling, all bits including the
DSP extension bits of the SR must be restored. If the repeat control must be recovered before
entering the exception handling state, the RS and RE registers must be recovered to the value that
existed before exception handling. In addition, if it is necessary to recover modulo control before
entering the exception handling state, the MOD register must be recovered to the value that
existed before exception handling.
The DSP unit incorporates eight data registers (A0, A1, X0, X1, Y0, Y1, M0, and M1) and a status
register (DSR). Figure 3.3 shows the DSP register configuration. These are 32-bit width registers
with the exception of registers A0 and A1. Registers A0 and A1 include 8 guard bits (fields A0G
and A1G), giving them a total width of 40 bits. The DSR register stores the DSP data operation
result (zero, negative, others). The DSP register has a DC bit whose function is similar to the T bit
in the CPU register. For details on DSR bits, refer to section 3.5, DSP Data Operation Instructions.
39 32 31 0
A0G A0
A1G A1
M0
M1
Initial value
X0
DSR : All 0
X1 Others: Undefined
Y0
Y1
31 8 7 6 5 4 3 1 0
................ GT Z N V CS[2:0] DC
In DSP mode, a specific function is provided to execute repeat loops efficiently. By using this
function, loop programs can be executed without overhead caused by the compare and branch
instructions.
In the above program example, instructions from the RptStart address (instr1 instruction) to the
RptEnd address (instrN instruction) are repeated four times. These repeated instructions in the
program are called repeat loop. The start and end instructions of the repeat loop are called the
repeat start instruction and repeat end instruction, respectively. The CPU sequentially executes
instructions and starts repeat loop control if the CPU detects the completion of a specific
instruction. This specific instruction is called the repeat detection instruction. In a repeat loop
consisting of four or more instructions, an instruction three instructions prior to the repeat end
instruction is regarded as the repeat detection instruction. In a repeat loop consisting of four or
more instructions, the same instruction is regarded as the RptStart instruction and RptDtct
instruction.
To control the repeat loop, the DSP extended control registers, such as the RE register and RS
register and the RC[11:0] and RF[1:0] bits of the SR register, are used. These registers can be
specified by the LDRE, LDRS, and SETRC instructions.
The CPU always executes instructions by comparing the RE register to program counter values.
Because the PC stores (the current instruction address +4), if the RE matches the PC during repeat
instruction detection execution, a repeat detection instruction can be detected. If a repeat detection
instruction is executed without branching and if RC[11:0] > 0, then repeat control is performed. If
RC[11:0] ≥ 2 when the repeat end instruction is completed, the RC[11:0] is decremented by 1 and
then control is passed to the address specified by the RS register.
Examples 2 to 4 show program examples of the repeat loop consisting of three instructions, two
instructions, and one instruction, respectively. In these examples, an instruction immediately prior
to the repeat start instruction is regarded as a repeat detection instruction. The RS register specifies
the specific value that indicates the number of repeat instructions.
In repeat loops consisting of three instructions, two instructions and one instruction, specific
addresses are specified in the RS register. RE – RS is calculated during SETRC instruction
execution, and the number of instructions included in the repeat loop is determined according to
the result. A value of 0, –2,and –4 in the result correspond to three instructions, two instructions,
and one instruction, respectively.
If repeat instruction execution is completed without branching and if RC[11:0] > 0, an instruction
following the repeat detection instruction is regarded as a repeat start instruction and instruction
execution is repeated for the number of times corresponding to the recognized number of
instructions. If RC[11:0] ≥ 2 when the repeat end instruction is completed, the RC[11:0] is
decremented by 1 and then control is passed to the address specified by the RS register. If
RC[11:0] ==1 (or 0) when the repeat end instruction is completed, the RC[11:0] is cleared to 0 and
then the control is passed to the next instruction following the repeat end instruction.
Note: If RE – RS is a positive value, the CPU regards the repeat loop as a four-instruction repeat
loop. (In a repeat loop consisting of four or more instructions, RE – RS is always a
positive value. For details, refer to example 1 above.) If RE – RS is positive, or a value
other than 0, –2,and –4, correct operation cannot be guaranteed.
Table 3.4 shows the addresses to be specified in the repeat start register (RS) and repeat end
register (RE).
To describe a repeat loop, the RS and RE registers must be specified appropriately by the LDRS
and LDRS instructions and then the number of repetitions must be specified by the SERTC
instruction. An 8-bit immediate data or a general register can be used as an operand of the SETRC
instruction. To specify the RC as a value greater than 256, use SETRC Rm type instructions.
Number of
Instruction Operation Execution States
LDRS @(disp,PC) Calculates (disp x 2 + PC) and stores the result to the 1
RS register
LDRE @(disp,PC) Calculates (disp x 2 + PC) and stores the result to the 1
RE register
SETRC #imm Sets 8-bit immediate data imm to the RC[11:0] bits of 1
the SR register and sets the information related to the
number of repetitions to the RF[1:0] bits of the SR.
RC[11:0] can be specified as 0 to 255.
SETRC Rm Sets the[11:0] bits of the Rm register to the RC[11:0] 1
bits of the SR register and sets the information related
to the number of repetitions to the RF[1:0] bits of the
SR.
RC[11:0] can be specified as 0 to 4095.
The RS and RE registers must be specified appropriately according to the rules shown in table 3.4.
The SH assembler supports control macros (REPEAT) as shown in table 3.6 to solve problems.
Number of
Instruction Operation Execution States
REPEAT RptStart, Specifies RptStart as repeat start instruction, RptEnd as 3
RptEnd, #imm repeat end instruction, and 8-bit immediate data #imm
as number of repetitions. This macro is extended to
three instructions: LDRS, LDRE, and SETRC which are
converted correctly.
REPEAT RptStart, Specifies RptStart as repeat start instruction, RptEnd as 3
RptEnd, Rm repeat end instruction, and the [11:0] bits of Rm as
number of repetitions. This macro is extended to three
instructions: LDRS, LDRE, and SETRC which are
converted correctly.
Using the repeat macros shown in table 3.4, examples 1 to 4 shown above can be simplified to
examples 5 to 8 as shown below.
• Example 6: Repeat loop consisting of three instructions (extended to the instruction stream
shown in example 2, above)
REPEAT RptStart, RptEnd, #4
instr0 ;
RptStart: instr1 ; [Repeat start instruction]
instr2 ;
RptEnd: instr3 ; [Repeat end instruction]
• Example 7: Repeat loop consisting of two instructions (extended to the instruction stream
shown in example 3, above)
REPEAT RptStart, RptEnd, #4
instr0 ;
RptStart: instr1 ; [Repeat start instruction]
RptEnd: instr2 ; [Repeat end instruction]
• Example 8: Repeat loop consisting of one instruction instructions (extended to the instruction
stream shown in example 4, above)
REPEAT RptStart, RptEnd, #4
instr0 ;
RptStart:
RptEnd: instr1 ; [Repeat start instruction]==[Repeat end
instruction]
In the DSP mode, the system control instructions (LDC and STC) that handle the RS and RE
registers are extended. The RC[11:0] bits and RF[1:0] bits of the SR can be controlled by the LDC
and STC instructions for the SR register. These instructions should be used if an exception is
enabled during repeat loop execution. The repeat loop can be resumed correctly by storing the RS
and RE register values and RC[11:0] bits and RF[1:0] bits of the SR register before exception
handling and by restoring the stored values after exception handling. However, note that there are
some restrictions on exception acceptance during repeat loop execution. For details refer to
Restrictions on Repeat Loop Control in section 3.3.1, DSP Repeat Control and section 7,
Exception Handling.
Number of
Instruction Operation Execution States
STC RS, Rn RS→Rn 1
STC RE, Rn RE→Rn 1
STC.L RS, @-Rn Rn-4→Rn, RS→(Rn) 1
STC.L RE, @-Rn Rn-4→Rn, RE→(Rn) 1
LDC.L @Rn+, RS (Rn)→RS, Rn+4→Rn 4
LDC.L @Rn+, RE (Rn)→RE, Rn+4→Rn 4
LDC Rn,RS Rn →RS 4
LDC Rn, RE Rn→RE 4
The SETRC instruction must be executed after executing the LDRS and LDRE instructions. In
addition, note that at least one instruction is required between the SETRC instruction and a repeat
start instruction.
(b) Illegal instruction one or more instructions following the repeat detection instruction
If one of the following instructions is executed between an instruction following a repeat detection
instruction to a repeat end instruction, an illegal instruction exception occurs.
• Branch instructions
BRA, BSR, BT, BF, BT/S, BF/S, BSRF, RTS, BRAF, RTE, JSR, JMP, TRAPA
• Repeat control instructions
SETRC, LDRS, LDRE
• Load instructions for SR, RS, and RE registers
LDC Rn,SR, LDC @Rn+,SR, LDC Rn,RE, LDC @Rn+,RE, LDC Rn,RS, LDC @Rn+,RS
Note: This restriction applies to all instructions for a repeat loop consisting of one to three
instructions and to three instructions including a repeat end instruction.
(c) Instructions prohibited during repeat loop (In a repeat loop consisting of four or more
instructions)
The following instructions must not be placed between the repeat start instruction and repeat
detection instruction in a repeat loop consisting of four or more instructions. Otherwise, the
correct operation cannot be guaranteed.
• Repeat control instructions
SETRC, LDRS, LDRE
• Load instructions for SR, RS, and RE registers
LDC Rn,SR, LDC @Rn+,SR, LDC Rn,RE, LDC @Rn+,RE, LDC Rn,RS, LDC @Rn+,RS
Note: Multiple repeat loops cannot be guaranteed. Describe the inner loop by repeat control
instructions, and the external loop by other instructions such as DT or BF/S.
(d) Branching to an instruction following the repeat detection instruction and restriction
on an exception acceptance
Execution of a repeat detection instruction must be completed without any branch so that the CPU
can recognize the repeat loop. Therefore, when the execution branches to an instruction following
the repeat detection instruction, the control will not be passed to a repeat start instruction after
executing a repeat end instruction because the repeat loop is not recognized by the CPU. In this
case, the RC[11:0] bits of the SR register will not be changed.
• If a conditional branch instruction is used in the repeat loop, an instruction before a repeat
detection instruction must be specified as a branch destination.
• If a subroutine call is used in the repeat loop, a delayed slot instruction of the subroutine call
instruction must be placed before a repeat detection instruction.
Here, a branch includes a return from an exception processing routine. If an exception whose
return address is placed in an instruction following the repeat detection instruction occurs, the
repeat control cannot be returned correctly. Accordingly, an exception acceptance is restricted
from the repeat detection instruction to the repeat end instruction. Exceptions such as interrupts
that can be retained by the CPU are retained. For exceptions that cannot be retained by the CPU, a
transition to an exception occurs but a program cannot be returned to the previous execution state
correctly. For details, refer to section 7, Exception Handling.
If RC[11:0] ≥ 2, the program counter (PC) value is not correct for instructions two instructions
following a repeat detection instruction. In a repeat loop consisting of one to three instructions,
the PC indicates the correct value (instruction address + 4) for an instruction (repeat start
instruction) following a repeat detect ion instruction but the PC continues to indicate the same
address (repeat start instruction address) from the subsequent instruction to a repeat end
instruction. In a repeat loop consisting of four or more instructions, the PC indicates the correct
value (instruction address + 4) for an instruction following a repeat detect ion instruction, but
PC indicates the RS and (RS +2) for instructions two and three instructions following the
repeat detection instruction. Here, RS indicates the value stored in the repeat start register
(RS). The correct operation cannot be guaranteed for the incorrect PC values.
Accordingly, PC relative addressing instructions placed two or more instructions following the
repeat detection instruction cannot be executed correctly and the correct results cannot be
obtained.
The CPU always executes a program with comparing the repeat end register (RE) and the program
counter (PC). If the PC matches the RE while the RC[11:0] bits of the SR register are other than 0,
the repeat control function is initiated.
• If RC ≥ 2, a control is passed to a repeat start instruction after a repeat end instruction has been
executed. The RC is decremented by 1 at the completion of the repeat end instruction.
In this case, restrictions (1) to (6) are also applied.
• If RC == 1, the RC is decremented to 0 at the completion of the repeat end instruction and a
control is passed to the subsequent instruction. In this case, restrictions (1) to (6) are also
applied.
• If RC == 0, the repeat control function is not initiated even if a repeat detection instruction is
executed. The repeat loop is executed once as normal instructions and a control is not be
passed to a repeat start instruction even if a repeat end instruction is executed.
In any DSP data transfer instructions, an address to be accessed is generated and output by the
CPU. For DSP data transfer instructions, some of the CPU general registers are used for address
generation and specific addressing modes are used.
LAB
CPU [31:0]
LDB
XAB YAB CDB [31:0]
[15:0] [15:0] [31:0]
Legend
XAB : X bus (address)
XDB : X bus (data)
YAB : Y bus (address)
YDB : Y bus (data)
LAB : L bus (address)
LDB : L bus (data)
CDB : C bus (data)
With double data transfer instructions, X memory and Y memory can be accessed in parallel.
In this case, the specific buses called X bus and Y bus are used to access X memory and Y
memory, respectively. To fetch the CPU instructions, the L bus is used. Accordingly, no conflict
occurs among X, Y, and L buses.
Load instructions for X memory specify the X0 or X1 register as the destination operand. Load
instructions for Y memory specify the Y0 or Y1 register as the destination operand. Store registers
for X or Y memory specify the A0 or A1 register as the source operand. These instructions use
only word data (16 bits). When a word data transfer instruction is executed, the upper word of
register operand is used. To load word data, data is loaded to the upper word of the destination
register and the lower word of the destination register is automatically cleared to 0.
Double data transfer instructions can be described in parallel to the DSP operation instructions.
Even if a conditional operation instruction is specified in parallel to a double data transfer
instruction, the specified condition does not affect the data transfer operations. For details, refer to
section 3.5, DSP Data Operation Instructions.
Double data transfer instructions can access only the X memory or Y memory and cannot access
other memory space. The X bus and Y bus are 16 bits and support 64-byte address spaces
corresponding to address areas H'A5000000 to H'A500FFFF and H'A5010000 to H'A501FFFF,
respectively. Because these areas are included in the P2/Uxy area, they are not affected by the
cache and address translation unit.
The single data transfer instructions access any memory location. All DSP registers other than the
DSR can be specified as source and destination operands.* Guard bit registers A0G and A1G can
also be specified as two independent registers. Because these instructions use the L bus (LAB and
LDB), these instructions can access any virtual space handled by the CPU. If these instructions
access the cacheable area while the cache is enabled, the area accessed by these instructions are
cached. The X memory and Y memory are mapped to the virtual address space and can also be
accessed by the single data transfer instructions. In this case, bus conflict may occur between data
transfer and instruction fetch because the CPU also uses the L bus for instruction fetches.
The single data transfer instructions can handle both word and longword data. In word data
transfer, only the upper word of the operand register is valid. In word data load, word data is
loaded into the upper word of the destination registers and the lower word of the destination is
automatically cleared to 0. If the guard bits are supported, the sign bit is extended before storage.
In longword data load, longword data is loaded into the upper and lower word of the destination
register. If the guard bits are supported, the sign bit is extended before storage. When the guard
register is stored, the sign bit is extended to the upper 24 bits of the LDB and are loaded onto the
LDB bus.
Notes: * Since the DSR register is defined as the system register, it can be accessed by the LDS
or STS instruction.
1. Any data transfer instruction is executed at the MA stage of the pipeline.
2. Any data transfer instruction does not modify the condition code bits of the DSR
register.
The DSR, A0, X0, X1, Y0, and Y1 registers in the DSP unit can also be used as the CPU system
registers. Accordingly, data transfer operations between these DSP system registers and general
registers or memory can be executed by the STS and LDS instructions. These DSP system
registers can be treated as the CPU system register such as PR, MACH and MACL and can use the
same addressing modes.
The DSP instructions 10 general registers in the 16 general registers are used as address pointers
or index registers for double data transfers and single data transfers. In the following descriptions,
another register function in the DSP instructions is also indicated within parentheses [ ].
• Double data transfer instructions (X memory and Y memory are accessed simultaneously)
In double data transfers, X memory Y memory can be accessed simultaneously. To specify X
and Y memory addresses, two address pointers are supported.
31 0
R0 General registers (DSP mode)
R1
X and Y double data transfers:
R2 [As2]
R3 [As3] R4, 5 [Ax] : Address register set for the X data memory
R4 [As0] R8 [Ix] : Index register for X address register set Ax
R5 [As1, Ax1]
R6 [Ay0]
R6, 7 [Ay] : Address register set for the Y data memory
R7 [Ay1]
R9 [Iy] : Index register for Y address register set Ay
R8 [Ix, Is]
R9 [Iy] Single data transfers:
R10 R4, 5, 2, 3 [As] : Address register set for all data memories
R11 R8 [Is] : Index register used for single data transfers
R12
R13
R14
R15
In assembler, R0 to R9 are used as symbols. In the DSP data transfer instructions, the following
register names (alias) can also be used. In assembler, described as shown below.
Ay1: .REG(R7)
As0: .REG (R4); This definition is used for if the alias is required in the single data transfer
As1: .REG (R5); This definition is used for if the alias is required in the single data transfer
Is: .REG (R8); This definition is used for if the alias is required in the single data transfer
Table 3.10 shows the relationship between the double data transfer instructions and single data
transfer instructions.
The double data transfer instructions supports the following three addressing modes.
When using X/Y data addressing, bit 0 of the address pointer is invalid; bits 0 and 1 of the address
pointer are invalid in word access. Accordingly, bit 0 of the address pointer and index register
must be cleared to 0 in X/Y data addressing.
When accessing X and Y memory using the X and Y buses, the upper word of Ax and Ay is
ignored. The result of Ay+ or Ay+Iy is stored in the lower word of Ay, while the upper word
retains its original value. The Ax and Ax +Ix operations are executed in longword (32 bits) and the
upper word may be changed according to the result.
The following four kinds of addressing can be used with single data transfer instructions.
In single data transfer instructions, all bits in 32-bit address are valid.
In double data transfer instructions, a module addressing can be used. If the address pointer value
reaches the preset modulo end address while a modulo addressing mode is specified,, the address
pointer value becomes the modulo start address.
To control modulo addressing, the modulo register (MOD) extended in the DSP mode and the
DMX and DMY bits of the SR register are used.
The MOD register is provided to set the start and end addresses of the modulo address area. The
upper and lower words of the MOD register store modulo start address (MS) and modulo end
address (ME), respectively. The LDC and STC instructions are extended for MOD register
handling.
If the DMX bit in the SR register is set, the modulo addressing is specified for the X address
register. If the DMY bit in the SR register is set, the modulo addressing is specified for the Y
address register. Modulo addressing is valid for either the X or the Y address register, only; it
cannot be set for both at the same time. Therefore, DMX and DMY cannot both be set
simultaneously (if they are, the DMY setting will be valid). ( In the future, this specification may
be changed.) The MDX and MDY bits of the SR can be specified by the STC or LDC instruction
for the SR register.
If an exception is accepted during modulo addressing, the MDX and MDY bits of the SR and
MOD register must be saved. By restoring these register values, a control is returned to the
modulo addressing after an exception handling.
The start and end addresses are specified in MS and ME, then the DMX or DMY bit is set to 1.
When the X or Y data transfer instruction specified by the DMX or DMY is executed, the address
register contents before updating are compared with ME*, and if they match, start address MS is
stored in the address register as the value after updating.
When the addressing type of the X/Y data transfer instruction is no-update, the X/Y data transfer
instruction is not returned to MS even if they match ME. When the addressing type of the X/Y
data transfer instruction is addition index register addressing, the address pointed may not match
the address pointer ME, and exceed it. In this case, the address pointer value does not become the
modulo start address.
The maximum modulo size is 64 kbytes. This is sufficient to access the X and Y data memory.
Note: Not only with modulo addressing, but when X and Y data addressing is used, bit 0 is
ignored. 0 must always be written to bit 0 of the address pointer, index register, MS, and
ME.
Memory data formats that can be used in the DSP instructions are classified into byte and
longword. An address error will occur if word data starting from an address other than 2n or
longword data starting from an address other than 4n is accessed by MOVS.L, LDS.L, or STS.L
instruction. In such cases, the data accessed cannot be guaranteed
An address error will not occur if word data starting from an address other than 2n is accessed by
the MOVX.W or MOVY.W instruction. When using the MOVX.W or MOVY.W instruction, an
address must be specified on the boundary 2n. If an address is specified other than 2n, the data
accessed cannot be guaranteed.
The format of double data transfer instructions is shown in tables 3.12 and that of single data
transfer instructions in table 3.13.
Type Mnemonic 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
X memory NOPX 1 1 1 1 0 0 0 0 0 0 0
data MOVX.W @Ax,Dx Ax Dx 0 0 1
transfer
MOVX.W @Ax+,Dx 1 0
MOVX.W @Ax+Ix,Dx 1 1
MOVX.W Da,@Ax Da 1 0 1
MOVX.W Da,@Ax+ 1 0
MOVX.W Da,@Ax+Ix 1 1
Y memory NOPY 1 1 1 1 0 0 0 0 0 0 0
data
MOVY.W @Ay,Dy Ay Dy 0 0 1
transfer
MOVY.W @Ay+,Dy 1 0
MOVY.W @Ay+Iy,Dy 1 1
MOVY.W Da,@Ay Da 1 0 1
MOVY.W Da,@Ay+ 1 0
MOVY.W Da,@Ay+Iy 1 1
Note: Ax: 0 = R4, 1 = R5
Ay: 0 = R6, 1 = R7
Dx: 0 = X0, 1 = X1
Dy: 0 = Y0, 1 = Y1
Da: 0 = A0, 1 = A1
Type Mnemonic 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Single data MOVS.W @-As,Ds 1 1 1 1 0 1 As Ds 0:(*) 0 0 0 0
transfer
MOVS.W @As,Ds 0:R4 1:(*) 0 1
MOVS.W @As+,Ds 1:R5 2:(*) 1 0
MOVS.W @As+Is,Ds 2:R2 3:(*) 1 1
MOVS.W Ds,@-As 3:R3 4:(*) 0 0 0 1
MOVS.W Ds,@As 5:A1 0 1
MOVS.W Ds,@As+ 6:(*) 1 0
MOVS.W Ds,@As+Is 7:A0 1 1
MOVS.L @-As,Ds 8:X0 0 0 1 0
MOVS.L @As,Ds 9:X1 0 1
MOVS.L @As+,Ds A:Y0 1 0
MOVS.L @As+Is,Ds B:Y1 1 1
MOVS.L Ds,@-As C:M0 0 0 1 1
MOVS.L Ds,@As D:A1G 0 1
MOVS.L Ds,@As+ E:M1 1 0
MOVS.L Ds,@As+Is F:A0G 1 1
Note: * Codes reserved for system use.
This LSI has eight data registers (A0, A1, X0, X1, Y0, Y1, M0 and M1) and one control register
(DSR) as DSP registers (figure 3.3).
Four kinds of operation access the DSP data registers. The first is DSP data processing. When a
DSP fixed-point data operation uses A0 or A1 as the source register, it uses the guard bits (bits 39
to 32). When it uses A0 or A1 as the destination register, guard bits 39 to 32 are valid. When a
DSP fixed-point data operation uses a DSP register other than A0 or A1 as the source register, it
sign-extends the source value to bits 39 to 32. When it uses one of these registers as the
destination register, bits 39 to 32 of the result are discarded.
The second kind of operation is an X or Y data transfer operation, MOVX.W, MOVY.W. This
operation accesses the X and Y memories through the 16-bit X and Y data buses (figure 3.4). The
register to be loaded or stored by this operation always comprises the upper 16 bits (bits 31 to 16).
X0 or X1 can be the destination of an X memory load and Y0 or Y1 can be the destination of a Y
memory load, but no other register can be the destination register in this operation. When data is
read into the upper 16 bits of a register (bits 31 to 16), the lower 16 bits of the register (bits 15 to
0) are automatically cleared. A0 and A1 can be stored in the X or Y memory by this operation, but
no other registers can be stored.
The third kind of operation is a single-data transfer instruction, MOVS.W or MOVS.L. These
instructions access any memory location through the LDB (figure 3.4). All DSP registers connect
to the LDB and can be the source or destination register of the data transfer. These instructions
have word and longword access modes. In word mode, registers to be loaded or stored by this
instruction comprise the upper 16 bits (bits 31 to 16) for DSP registers except A0G and A1G.
When data is loaded into a register other than A0G and A1G in word mode, the lower half of the
register is cleared. When A0 or A1 is used, the data is sign-extended to bits 39 to 32 and the lower
half is cleared. When A0G or A1G is the destination register in word mode, data is loaded into an
8-bit register, but A0 or A1 is not cleared. In longword mode, when the destination register is A0
or A1, it is sign-extended to bits 39 to 32.
The fourth kind of operation is system control instructions such as LDS, STS, LDS.L, or STS.L.
The DSR, A0, X0, X1, Y0, and Y1 registers of the DSP register can be treated as system registers.
For these registers, data transfer instructions between the CPU general registers and system
registers or memory access instructions are supported.
Tables 3.14 and 3.15 show the data type of registers used in DSP instructions. Some instructions
cannot use some registers shown in the tables because of instruction code limitations. For
example, PMULS can use A1 as the source register, but cannot use A0. These tables ignore details
of register selectability.
The DSP unit incorporates one control register and DSP status register (DSR). The DSR register
stores the DSP data operation result (zero, negative, others). The DSP register also has the DC bit
whose function is similar to the T bit in the CPU register. The DC bit functions as status flag.
Conditional DSP data operations are controlled based on the DC bit. These operation control
affects only the DSP unit instructions. In other words, these operations control affects only the
DSP registers and does not affect address register update and CPU instructions such as load and
store instructions. A condition to be reflected on the DC bit should be specified to the DC status
selection bits (CS[2:0]).
The unconditional DSP type data instructions other than PMULS, MOVX, MOVY, and MOVS
change the condition flag and DC bit. However, the CPU instructions including the MAC
instruction do not modify the DC bit. In addition, conditional DSP instructions do not modify the
DSR.
Initial
Bits Bit Name Value R/W Function
31 to 8 All 0 R Reserved
These bits are always read as 0. The write value should
always be 0.
7 GT 0 R/W Signed Greater Bit
Indicates that the operation result is positive (except 0),
or that operand 1 is greater than operand 2
1: Operation result is positive, or operand 1 is greater
than operand 2
6 Z 0 R/W Zero Bit
Indicates that the operation result is zero (0), or that
operand 1 is equal to operand 2
1: Operation result is zero (0), or operands are equal
5 N 0 R/W Negative Bit
Indicates that the operation result is negative, or that
operand 1 is smaller than operand 2
1: Operation result is negative, or operand 1 is smaller
than operand 2
4 V 0 R/W Overflow Bit
Indicates that the operation result has overflowed
1: Operation result has overflowed
Initial
Bits Bit Name Value R/W Function
3 to 1 CS All 0 R/W DC Bit Status Selection
Designate the mode for selecting the operation result
status to be set in the DC bit
000: Carry/borrow mode
001: Negative value mode
010: Zero mode
011: Overflow mode
100: Signed greater mode
101: Signed greater than or equal to mode
110: Reserved (setting prohibited)
111: Reserved (setting prohibited)
0 DC 0 R/W DSP Status Bit
Sets the status of the operation result in the mode
designated by the CS bits
0: Designated mode status has not occurred
1: Designated mode status has occurred
Indicates the operation result by carry or borrow
regardless of the CS bit status after the PADDC or
PSUBC instruction has been executed.
The DSR is assigned to the system registers. For the DSR, the following load and store
instructions are supported.
STS DSR,Rn;
STS.L DSR,@-Rn;
LDS Rn,DSR;
LDS.L @Rn+,DSR;
If the DSR is read by the STS instruction, upper bits (bits 31 to 16) are all 0.
DSP operation instructions are instructions for digital signal processing performed by the DSP
unit. These instructions have a 32-bit instruction code, and multiple instructions can be executed
in parallel. The instruction code is divided into a field A and field B; a parallel data transfer
instruction is specified in the field A, and a single or double data operation instruction in the field
B. Instructions can be specified independently, and are also executed independently.
B-field data operation instructions are of three kinds: double data operation instructions,
conditional single data operation instructions, and unconditional single data operation instructions.
The formats of the DSP operation instructions are shown in table 3.17. The respective operands
are selected independently from the DSP registers. The correspondence between DSP operation
instruction operands and registers is shown in table 3.18.
When writing parallel instructions, the field-B instruction is written first, followed by the field-A
instruction. A sample parallel processing program is shown in figure 3.6.
PADD A0, M0, A0 PMULS X0, Y0, M0 MOVX.W @R4+, X0 MOVY.W @R6+, Y0
The no operation instructions NOPX and NOPY can be omitted. For details on the field B in DSP
data operation instructions, refer to section 3.6.4, DSP Operation Instructions.
The DSR register condition code bit (DC) is always updated on the basis of the result of an
unconditional ALU or shift operation instruction. Conditional instructions do not update the DC
bit. Multiply instructions, also, do not update the DC bit. DC bit updating is performed by means
of the CS[2:0] bits in the DSR register. The DC bit update rules are shown in table 3.19.
Instruction Code
PADD X0,Y0,A0 MOVX.W @R4+,X0 MOVY.W @R6+R9,Y0 1111100000001011
1011000100000111
PADD X0,Y0,A0 NOPX MOVY.W @R6+R9,Y0 1111100000000011
1011000100000111
PADD X0,Y0,A0 NOPX NOPY 1111100000000000
1011000100000111
PADD X0,Y0,A0 NOPX 1111100000000000
1011000100000111
PADD X0,Y0,A0 1111100000000000
1011000100000111
MOVX.W @R4+,X0 MOVY.W @R6+R9,Y0 1111000000001011
MOVX.W @R4+,X0 NOPY 1111000000001000
MOVS.W @R4+,X0 1111010010001000
NOPX MOVY.W @R6+R9,Y0 1111000000000011
MOVY.W @R6+R9,Y0 1111000000000011
NOPX NOPY 1111000000000000
NOP 0000000000001001
This LSI has several different data formats that depend on the instruction. This section explains
the data formats for DSP type instructions.
Figure 3.8 shows three DSP-type data formats with different binary point positions. A CPU-type
data format with the binary point to the right of bit 0 is also shown for reference.
The DSP-type fixed point data format has the binary point between bit 31 and bit 30. The DSP-
type integer format has the binary point between bit 16 and bit 15. The DSP-type logical format
does not have a binary point. The valid data lengths of the data formats depend on the instruction
and the DSP register.
31 30 0
Without guard bits S –1 to +1 – 2–31
39 31 30 16 15 0
Multiplier input S –1 to +1 – 2–15
31 16 15 0
Without guard bits S –215 to +215 – 1
31 21 16 15 0
Shift amount for
logical shift (PSHL) S –16 to +16
39 31 16 15 0
DSP type logical
The shift amount for the arithmetic shift (PSHA) instruction has a 7-bit field that can represent
values from –64 to +63, but –32 to +32 are valid numbers for the instruction. Also the shift
amount for a logical shift operation has a 6-bit field, but –16 to +16 are valid numbers for the
instruction.
Figure 3.9 shows the ALU arithmetic operation flow. Table 3.21 shows the variation of this type
of operation and table 3.22 shows the correspondence between each operand and registers.
39 31 0 39 31 0
Guard Source 1 Guard Source 2
ALU GT Z N V DC
DSR
Guard Destination
39 31 0
Note: The ALU fixed-point arithmetic operations are basically 40-bit operation; 32 bits of the
base precision and 8 bits of the guard-bit parts. So the signed bit is copied to the guard-bit
parts when a register not providing the guard-bit parts is specified as the source operand.
When a register not providing the guard-bit parts is specified as a destination operand, the
lower 32 bits of the operation result are input into the destination register.
ALU fixed-point operations are executed between registers. Each source and destination operand
are selected independently from one of the DSP registers. When a register providing guard bits is
specified as an operand, the guard bits are activated for this type of operation. These operations
are executed in the DSP stage, as shown in figure 3.10. The DSP stage is the same stage as the
MA stage in which memory access is performed.
Register Sx Sy Dz Du
A0 Yes Yes Yes
A1 Yes Yes Yes
M0 Yes Yes
M1 Yes Yes
X0 Yes Yes Yes
X1 Yes Yes
Y0 Yes Yes Yes
Y1 Yes Yes
As shown in figure 3.10, data loaded from the memory at the MA stage, which is programmed at
the same line as the ALU operation, is not used as a source operand for this operation, even
though the destination operand of the data load operation is identical to the source operand of the
ALU operation. In this case, previous operation results are used as the source operands for the
ALU operation, and then updated as the destination operand of the data load operation.
Slot 1 2 3 4 5 6
Stage
EX Addressing Addressing
Every time an ALU arithmetic operation is executed, the DC, N, Z, V, and GT bits in DSR are
basically updated in accordance with the operation result. However, in case of a conditional
operation, they are not updated even though the specified condition is true and the operation is
executed. In case of an unconditional operation, they are always updated in accordance with the
operation result. The definition of a DC bit is selected by CS[2:0] (condition selection) bits in
DSR. The DC bit result is as follows:
The DC bit indicates that carry or borrow is generated from the most significant bit of the
operation result, except the guard-bit parts. Some examples are shown in figure 3.11. This mode is
the default condition. When the input data is negative in a PABS or PNEG instruction, carry is
generated.
Example 1 Example 2
Example 3 Example 4
The DC flag indicates the same value as the MSB of the operation result. When the result is a
negative number, the DC bit shows 1. When it is 0 or a positive number, the DC bit shows 0. The
ALU always executes 40-bit arithmetic operation, so the sign bit to detect whether positive or
negative is always got from the MSB of the operation result regardless of the destination operand.
Some examples are shown in figure 3.12.
Example 1 Example 2
The DC flag indicates whether the operation result is 0 or not. When the result is 0, the DC bit
shows 1. When it is not 0, the DC bit shows 0.
The DC bit indicates whether or not overflow occurs in the result. When an operation yields a
result beyond the range of the destination register, except the guard-bit parts, the DC bit is set.
Even though guard bits are provided in the destination register, the DC bit always indicates the
result of when no guard bits are provided. So, the DC bit is always set to 1 if the guard-bit parts
are used for large number representation. Some DC bit generation examples in overflow mode are
shown in figure 3.13.
Example 1 Example 2
The DC bit indicates whether or not the source 1 data (signed) is greater than the source 2 data
(signed) as the result of compare operation PCMP. The PCMP operation should be executed
before executing the conditional operation under this condition mode. This mode is similar to the
Negative Value Mode described before, because the result of a compare operation is a positive
value if the source 1 data is greater than the source 2 data. However, the signed bit of the result
shows a negative value if the compare operation yields a result beyond the range of the destination
operand, including the guard-bit parts (called “Over-range”), even though the source 1 data is
greater than the source 2 data. The DC bit is updated concerning this type of special case in this
condition mode. The equation below shows the definition of getting this condition:
When the PCMP operation is executed under this condition mode, the result of the DC bit is the
same as the T bit’s result of the CMP/GT operation of the CPU instruction.
The DC bit indicates whether the source 1 data (signed) is greater than or equal to the source 2
data (signed) as the result of compare operation PCMP. This mode is similar to the Signed Greater
Than Mode described before but the equal case is also included in this mode. The equation below
shows the definition of getting this condition:
DC = ~ (Negative ^ Over-range)
When the PCMP operation is executed under this condition mode, the result of the DC bit is the
same as the T bit’s result of a CMP/GE operation of the CPU instruction.
The N bit always indicates the same state as the DC bit set in negative value mode by the CS[2:0]
bits. See the negative value mode part above. The Z bit always indicates the same state as the DC
bit set in zero value mode by the CS[2:0] bits. See the zero value mode part above. The V bit
always indicates the same state as the DC bit set in overflow mode by the CS[2:0] bits. See the
overflow mode part above. The GT bit always indicates the same state as the DC bit set in signed
greater than mode by the CS[2:0] bits. See the signed greater than mode part above.
Note: The DC bit is always updated as the carry flag for ‘PADDC’ and is always updated as the
carry/borrow flag for ‘PSUBC’ regardless of the CS[2:0] state.
• Overflow Protection
The S bit in SR is effective for any ALU fixed-point arithmetic operations in the DSP unit. See
section 3.5.11, Overflow Protection, for details.
Figure 3.14 shows the ALU integer arithmetic operation flow. Table 3.23 shows the variation of
this type of operation. The correspondence between each operand and registers is the same as
ALU fixed-point operations as shown in table 3.22.
39 31 0 39 31 0
Guard Source 1 Guard Source 2
ALU GT Z N V DC
DSR
Ignored
Guard Destination
Cleared to 0
39 31 0
In ALU integer arithmetic operations, the lower word of the source operand is ignored and the
lower word of the destination operand is automatically cleared. The guard-bit parts are effective in
ALU integer arithmetic operations if they are supported. Others are basically the same operation
as ALU fixed-point arithmetic operations. As shown in table 3.23, however, this type of operation
provides two kinds of instructions only, so that the second operand is actually either +1 or –1.
When a word data is loaded into one of the DSP unit’s registers, it is input as an upper word data.
When a register providing guard bits is specified as an operand, the guard bits are also activated.
These operations, as well as fixed-point operations, are executed in the DSP stage, as shown in
figure 3.10. The DSP stage is the same stage as the MA stage in which memory access is
performed.
Every time an ALU arithmetic operation is executed, the DC, N, Z, V, and GT bits in DSR are
basically updated in accordance with the operation result. This is the same as fixed-point
operations but the lower word of each source and destination operand is not used in order to
generate them. See section 3.5.4, ALU Fixed-Point Arithmetic Operations, for details.
In case of a conditional operation, they are not updated even though the specified condition is true
and the operation is executed. In case of an unconditional operation, they are always updated in
accordance with the operation result. See section 3.5.4, ALU Fixed-Point Arithmetic Operations,
for details.
• Overflow Protection
The S bit in SR is effective for any ALU integer arithmetic operations in DSP unit. See section
3.5.11, Overflow Protection, for details.
Figure 3.15 shows the ALU logical operation flow. Table 3.24 shows the variation of this type of
operation. The correspondence between each operand and registers is the same as the ALU fixed-
point operations as shown in table 3.21.
As shown in figure 3.15, this type of operation uses only the upper word of each operand. The
lower word and guard-bit parts are ignored for the source operand and those of the destination
operand are automatically cleared. These operations are also executed in the DSP stage, as shown
in figure 3.10. The DSP stage is the same stage as the MA stage in which memory access is
performed.
39 31 0 39 31 0
Source 1 Source 2
ALU GT Z N V DC
DSR
Ignored
Destination
Cleared to 0
39 31 0
Every time an ALU logical operation is executed, the DC, N, Z, V, and GT bits in the DSR
register are basically updated in accordance with the operation result. In case of a conditional
operation, they are not updated even though the specified condition is true and the operation is
executed. In case of an unconditional operation, they are always updated in accordance with the
operation result. The definition of the DC bit is selected by the CS[2:0] (condition selection) bits
in DSR. The DC bit result is:
The DC bit is set when the operation result is zero; otherwise it is cleared.
The N bit always indicates the same state as the DC bit set in negative value mode by the CS[2:0]
bits. See the negative value mode part above. The Z bit always indicates the same state as the DC
bit set in zero value mode by the CS[2:0] bits. See the zero value mode part above. The V bit
always indicates the same state as the DC bit set in overflow mode by the CS[2:0] bits. See the
overflow mode part above. The GT bit always indicates the same state as the DC bit set in signed
greater than mode by the CS[2:0] bits. See the signed greater than mode part above.
Figure 3.16 shows the multiply operation flow. Table 3.25 shows the variation of this type of
operation and table 3.26 shows the correspondence between each operand and registers. The
multiply operation of the DSP unit is single-word signed single-precision multiplication. These
operations are executed in the DSP stage, as shown in figure 3.10. The DSP stage is the same
stage as the MA stage in which memory access is performed.
39 31 0 39 31 0
S Source 1 S Source 2
MAC
S Destination 0 Ignored
39 31 1 0
Register Se Sf Dg
A0 Yes
A1 Yes Yes Yes
M0 Yes
M1 Yes
X0 Yes Yes
X1 Yes
Y0 Yes Yes
Y1 Yes
Note: The multiply operations basically generate 32-bit operation results. So when a register
providing the guard-bit parts are specified as a destination operand, the guard-bit parts will
copy bit 31 of the operation result.
The multiply operation of the DSP unit side is not integer but fixed-point arithmetic operation. So,
the upper words of each multiplier and multiplicand are input into a MAC unit as shown in figure
3.16. In the SH’s standard multiply operations, the lower words of both source operands are input
into a MAC unit. The operation result is also different from the SH’s case. The SH’s multiply
operation result is aligned to the LSB of the destination, but the fixed-point multiply operation
result is aligned to the MSB, so that the LSB of the fixed-point multiply operation result is always
0.
The fixed-point multiply operation is executed in one cycle. Multiply is always unconditional, but
does not affect any condition code bits, DC, N, Z, V, and GT , in DSR.
• Overflow Protection
The S bit in SR is effective for this multiply operation in the DSP unit. See section 3.5.11,
Overflow Protection, for details.
If the S bit is 0, overflow occurs only when H'8000*H'8000 ((-1.0)*(-1.0)) operation is
executed as signed fixed-point multiply. The result is H'00 8000 0000 but it does not mean
(+1.0). If the S bit is 1, overflow is prevented and the result is H'00 7FFF FFFF.
Shift operations can use either register or immediate value as the shift amount operand. Other
source and destination operands are specified by the register. There are two kinds of shift
operations of arithmetic and logical shifts. Table 3.27 shows the variation of this type of operation.
The correspondence between each operand and registers, except for immediate operands, is the
same as the ALU fixed-point operations as shown in table 3.21.
Note: The arithmetic shift operations are basically 40-bit operation, that is, the 32 bits of the
base precision and eight bits of the guard-bit parts. So the signed bit is copied to the guard-
bit parts when a register not providing the guard-bit parts is specified as the source
operand. When a register not providing the guard-bit parts is specified as a destination
operand, the lower 32 bits of the operation result are input into the destination register.
In this arithmetic shift operation, all bits of the source 1 and destination operands are activated.
The shift amount is specified by the source 2 operand as an integer data. The source 2 operand can
be specified by either a register or immediate operand. The available shift range is from –32 to
+32. Here, a negative value means the right shift, and a positive value means the left shift. It is
possible for any source 2 operand to specify from –64 to +63 but the result is unknown if an
invalid shift value is specified. In case of a shift with an immediate operand instruction, the source
1 operand must be the same register as the destination’s. This operation is executed in the DSP
stage, as shown in figure 3.10 as well as in fixed-point operations. The DSP stage is the same
stage as the MA stage in which memory access is performed.
Every time an arithmetic shift operation is executed, the DC, N, Z, V, and GT bits in DSR are
basically updated in accordance with the operation result. In case of a conditional operation, they
are not updated even though the specified condition is true and the operation is executed. In case
of an unconditional operation, they are always updated in accordance with the operation result.
The definition of the DC bit is selected by the CS[2:0] (condition selection) bits in DSR. The DC
bit result is:
The N bit always indicates the same state as the DC bit set in negative value mode by the CS[2:0]
bits. See the negative value mode part above. The Z bit always indicates the same state as the DC
bit set in zero value mode by the CS[2:0] bits. See the zero value mode part above. The V bit
always indicates the same state as the DC bit set in overflow mode by the CS[2:0] bits. See the
overflow mode part above. The GT bit always indicates the same state as the DC bit set in signed
greater than mode by the CS[2:0] bits. See the signed greater than mode part above.
• Overflow Protection
The S bit in SR is also effective for arithmetic shift operation in the DSP unit. See section
3.5.11, Overflow Protection, for details.
Cleared to 0
Left shift Right shift
39 32 31 16 15 0 39 32 31 16 15 0
0 0
Shift out Shift out
>=0 <0
Updated GT Z N V DC
+16 to -16 DSR
39 32 31 22 21 16 15 0
Shift amount data Sy
(source 2)
5 0 Ignored
Imm2
As shown in figure 3.18, the logical shift operation uses the upper word of the source 1 operand
and the destination operand. The lower word and guard-bit parts are ignored for the source
operand and those of the destination operand are automatically cleared as in the ALU logical
operations. The shift amount is specified by the source 2 operand as an integer data. The source 2
operand can be specified by either the register or immediate operand. The available shift range is
from –16 to +16. Here, a negative value means the right shift, and a positive value means the left
shift. It is possible for any source 2 operand to specify from –32 to +31, but the result is unknown
if an invalid shift value is specified. In case of a shift with an immediate operand instruction, the
source 1 operand must be the same register as the destination’s. These operations are executed in
the DSP stage, as shown in figure 3.10. The DSP stage is the same stage as the MA stage in which
memory access is performed.
Every time a logical shift operation is executed, the DC, N, Z, V, and GT bits in DSR are basically
updated in accordance with the operation result. In case of a conditional operation, they are not
updated even though the specified condition is true and the operation is executed. In case of an
unconditional operation, they are always updated in accordance with the operation result. The
definition of the DC bit is selected by the CS[2:0] (condition selection) bits in DSR. The DC bit
result is:
The N bit always indicates the same state as the DC bit set in negative value mode by the CS[2:0]
bits. See the negative value mode part above. The Z bit always indicates the same state as the DC
bit set in zero value mode by the CS[2:0] bits. See the zero value mode part above. The V bit
always indicates the same state as the DC bit set in overflow mode by the CS[2:0] bits, but it is
always cleared in this operation. So is the GT bit.
The PDMSB, most significant bit detection operation, is used to calculate the shift amount for
normalization. Figure 3.19 shows the PDMSB operation flow and table 3.28 shows the operation
definition. Table 3.29 shows the possible variations of this type of operation. The correspondence
between each operand and registers is the same as for ALU fixed-point operations, as shown in
table 3.21.
Note: The result of the MSB detection operation is basically 24 bits as well as ALU integer
operation, the upper 16 bits of the base precision and eight bits of the guard-bit parts.
When a register not providing the guard-bit parts is specified as a destination operand, the
upper word of the operation result is input into the destination register.
As shown in figure 3.19, the PDMSB operation uses all bits as a source operand, but the
destination operand is treated as an integer operation result because shift amount data for
normalization should be integer data as described in section 3.5.8, Shift Operations. These
operations are executed in the DSP stage, as shown in figure 3.10. The DSP stage is the same
stage as the MA stage in which memory access is performed.
Every time a PDMSB operation is executed, the DC, N, Z, V, and GT bits in DSR are basically
updated in accordance with the operation result. In case of a conditional operation, they are not
updated, even though the specified condition is true, and the operation is executed. In case of an
unconditional operation, they are always updated with the operation result.
39 31 0
Guard Source 1 or 2
GT Z N V DC
Priority encoder
DSR
Guard Cleared to 0
39 31 0
The definition of the DC bit is selected by the CS0 to CS2 (condition selection) bits in DSR. The
DC bit result is
The DC bit is set when the operation result is a negative value, and cleared to 0 when the
operation result is zero or a positive value.
The DC bit is set when the operation result is zero; otherwise it is cleared to 0.
The DC bit is set to 1 when the operation result is a positive value; otherwise it is cleared to 0.
The DC bit is set to 1 when the operation result is zero or a positive value; otherwise it is cleared
to 0.
The N bit always indicates the same state as the DC bit set in negative value mode by the CS[2:0]
bits. See the negative value mode part above. The Z bit always indicates the same state as the DC
bit set in zero value mode by the CS[2:0] bits. See the zero value mode part above. The V bit is
always cleared. The GT bit always indicates the same state as the DC bit set in signed greater than
mode by the CS[2:0] bits. See the signed greater than mode part above.
The DSP unit provides the function that rounds from 32 bits to 16 bits. In case of providing guard-
bit parts, it rounds from 40 bits to 24 bits. When a round instruction is executed, H'00008000 is
added to the source operand data and then, the lower word is cleared. Figure 3.20 shows the
rounding operation flow and figure 3.21 shows the operation definition. Table 3.30 shows the
variation of this type of operation. The correspondence between each operand and registers is the
same as ALU fixed-point operations as shown in table 3.21.
As shown in figure 3.21, the rounding operation uses full-size data for both source and destination
operands. These operations are executed in the DSP stage as shown in figure 3.10. The DSP stage
is the same stage as the MA stage in which memory access is performed.
The rounding operation is always executed unconditionally, so that the DC, N, Z, V, and GT bits
in DSR are always updated in accordance with the operation result. The definition of the DC bit is
selected by the CS0 to CS2 (condition selection) bits in DSR. The result of these condition code
bits is the same as the ALU-fixed point arithmetic operations.
39 31 0
Guard Source 1 or 2 H'00008000
ALU GT Z N V DC
DSR
Guard Cleared to 0
39 31 0
Rounded result
H'00 0002
H'00 0001
Analog value
0 True value
H'00 0001 8000
H'00 0002 0000
H'00 0002 8000
• Overflow Protection
The S bit in SR is effective for any rounding operations in the DSP unit. See section 3.5.11,
Overflow Protection, for details.
The S bit in SR is effective for any arithmetic operations executed in the DSP unit, including the
SH’s standard multiply and MAC operations. The S bit in SR is used as the overflow protection
enable bit. The arithmetic operation overflows when the operation result exceeds the range of
two’s complement representation without guard-bit parts. Table 3.31 shows the definition of
overflow protection for fixed-point arithmetic operations, including fixed-point signed by signed
multiplication described in section 3.5.7, Fixed-Point Multiply Operation. Table 3.32 shows the
definition of overflow protection for integer arithmetic operations. The lower word of the
saturation value of the integer arithmetic operation is don’t care. Lower word value cannot be
guaranteed.
When the overflow protection is effective, overflow never occurs. So, the V bit is cleared, and the
DC bit is also cleared when the overflow mode is selected by the CS[2:0] bits.
The DSP unit of this LSI provides additional two independent registers, MACL and MACH, in
order to support CPU standard multiply/MAC operations. They can be also used as temporary
storage registers by local data move instructions between MACH/L and other DSP registers.
Figure 3.22 shows the flow of seven local data move instructions. Table 3.33 shows the variation
of this type of instruction.
MACH
MACL
PSTS PLDS
X0 X1
Y0 Y1
M0 M1
A0 A1
A0G A1G DSR
Cannot be used
This instruction is very similar to other transfer instructions. If either the A0 or A1 register is
specified as the destination operand of PSTS, the signed bit is sign-extended and copied into the
corresponding guard-bit parts, A0G or A1G. The DC bit in DSR and other condition code bits are
not updated regardless of the instruction result. This instruction can operate as a conditional. This
instruction can operate with MOVX and MOVY in parallel.
When an identical destination operand is specified with multiple parallel instructions, data conflict
occurs. Table 3.34 shows the correspondence between each operand and registers.
• When ALU operation and multiply instructions specify the same destination operand (Du and
Dg)
• When X-memory load and ALU operation specify the same destination operand (Dx and Du,
or Dz)
• When Y-memory load and ALU operation specify the same destination operand (Dy and Du,
or Dz)
Execution
Instruction Instruction Code Operation States DC
Execution
Instruction Instruction Code Operation States DC Category
The correspondence between DSP data transfer operands and registers is shown in table 3.38.
Table 3.38 Correspondence between DSP Data Transfer Operands and Registers
Register Ax Ix Dx Ay Iy Dy Da As Ds
SH R0
register R1
R2 (As2) Yes
R3 (As3) Yes
R4 (Ax0) Yes Yes
R5 (Ax1) Yes Yes
R6 (Ay0) Yes
R7 (Ay1) Yes
R8 (Ix) Yes
R9 (Iy) Yes
DSP A0 Yes Yes
register
A1 Yes Yes
M0 Yes
M1 Yes
X0 Yes Yes
X1 Yes Yes
Y0 Yes Yes
Y1 Yes Yes
A0G Yes
A1G Yes
Execution
Instruction Instruction Code Operation States DC
Execution
Instruction Instruction Code Operation States DC
Execution
Instruction Instruction Code Operation States DC
DCF PDMSB Sy,Dz 111110********** If DC = 0, normalization count shift value 1 –
Sy → Dz
1011111100yyzzzz
If DC=1, nop
PINC Sx,Dz 111110********** MSW of Sx + 1 → Dz 1 *
10011001xx00zzzz
PINC Sy,Dz 111110********** MSW of Sy + 1 → Dz 1 *
1011100100yyzzzz
DCT PINC Sx,Dz 111110********** If DC = 1, MSW of Sx + 1 → Dz 1 –
10011010xx00zzzz If DC = 0, nop
DCT PINC Sy,Dz 111110********** If DC = 1, MSW of Sy + 1 → Dz 1 –
1011101000yyzzzz If DC = 0, nop
DCF PINC Sx,Dz 111110********** If DC = 0, MSW of Sx + 1 → Dz 1 –
10011011xx00zzzz If DC = 1, nop
DCF PINC Sy,Dz 111110********** If DC = 0, MSW of Sy + 1 → Dz 1 –
1011101100yyzzzz If DC = 1, nop
PNEG Sx,Dz 111110********** 0-Sx → Dz 1 *
11001001xx00zzzz
PNEG Sy,Dz 111110********** 0-Sy → Dz 1 *
1110100100yyzzzz
DCT PNEG Sx,Dz 111110********** If DC = 1, 0-Sx → Dz 1 –
11001010xx00zzzz If DC = 0, nop
DCT PNEG Sy,Dz 111110********** If DC = 1, 0-Sy → Dz 1 –
1110101000yyzzzz If DC = 0, nop
DCF PNEG Sx,Dz 111110********** If DC = 0, 0-Sx → Dz 1 –
11001011xx00zzzz If DC = 1, nop
DCF PNEG Sy,Dz 111110********** If DC = 0, 0-Sy → Dz 1 –
1110101100yyzzzz If DC = 1, nop
POR Sx,Sy,Dz 111110********** Sx | Sy → Dz 1 *
10110101xxyyzzzz
DCT POR Sx,Sy,Dz 111110********** If DC = 1, Sx | Sy → Dz 1 –
10110110xxyyzzzz If DC = 0, nop
DCF POR Sx,Sy,Dz 111110********** If DC = 0, Sx | Sy → Dz 1 –
10110111xxyyzzzz If DC = 1, nop
Execution
Instruction Instruction Code Operation States DC
PAND Sx,Sy,Dz 111110********** Sx & Sy → Dz 1 *
10010101xxyyzzzz
DCT PAND Sx,Sy,Dz 111110********** If DC = 1, Sx & Sy → Dz 1 –
10010110xxyyzzzz If DC = 0, nop
DCF PAND Sx,Sy,Dz 111110********** If DC = 0, Sx & Sy → Dz 1 –
10010111xxyyzzzz If DC = 1, nop
PXOR Sx,Sy,Dz 111110********** Sx ^ Sy → Dz 1 *
10100101xxyyzzzz
DCT PXOR Sx,Sy,Dz 111110********** If DC = 1, Sx ^ Sy → Dz 1 –
10100110xxyyzzzz If DC = 0, nop
DCF PXOR Sx,Sy,Dz 111110********** If DC = 0, Sx ^ Sy → Dz 1 –
10100111xxyyzzzz If DC = 1, nop
PDEC Sx,Dz 111110********** Sx [39:16]-1 → Dz 1 *
10001001xx00zzzz
DCT PDEC Sx,Dz 111110********** If DC = 1, Sx [39:16]-1 → Dz 1 –
10001010xx00zzzz If DC = 0, nop
DCF PDEC Sx,Dz 111110********** If DC = 0, Sx [39:16]-1 → Dz 1 –
10001011xx00zzzz If DC = 1, nop
PDEC Sy,Dz 111110********** Sy [31:16]-1 → Dz 1 *
1010100100yyzzzz
DCT PDEC Sy,Dz 111110********** If DC = 1, Sy [31:16]-1 → Dz 1 –
1010101000yyzzzz If DC = 0, nop
DCF PDEC Sy,Dz 111110********** If DC = 0, Sy [31:16]-1 → Dz 1 –
1010101100yyzzzz If DC = 1, nop
PCLR Dz 111110********** h'00000000 → Dz 1 *
100011010000zzzz
DCT PCLR Dz 111110********** If DC = 1, h'00000000 → Dz 1 –
100011100000zzzz If DC = 0, nop
DCF PCLR Dz 111110********** If DC = 0, h'00000000 → Dz 1 –
100011110000zzzz If DC = 1, nop
PSHA #imm,Dz 111110********** If imm>=0, Dz<<imm → Dz (arithmetic 1 *
shift)
00010iiiiiiizzzz
If imm<0, Dz>>imm → Dz
Execution
Instruction Instruction Code Operation States DC
Execution
Instruction Instruction Code Operation States DC
Table 3.40 shows the operation code map including an instruction codes extended in the DSP
mode.
Instruction Code Fx: 0000 Fx: 0001 Fx: 0010 Fx: 0011 to 1111
0000 Rn Fx 0000
0000 Rn Fx 0001
0000 Rn 00MD 0010 STC SR, Rn STC GBR, Rn STC VBR, Rn STC SSR, Rn
0000 Rn 01MD 0010 STC SPC, Rn STC MOD, Rn STC RS, Rn STC RE, Rn
0000 Rn 10MD 0010 STC R0_BANK, Rn STC R1_BANK, Rn STC R2_BANK, Rn STC R3_BANK, Rn
0000 Rn 11MD 0010 STC R4_BANK, Rn STC R5_BANK, Rn STC R6_BANK, Rn STC R7_BANK, Rn
0000 Rn Rm 01MD MOV.B Rm, @(R0, Rn) MOV.W Rm, @(R0, Rn) MOV.L Rm,@(R0, Rn) MUL.L Rm, Rn
0000 Rn Fx 1000
0000 Rn 10MD 1010 STS X0, Rn STS X1, Rn STS Y0, Rn STS Y1, Rn
0000 Rn Fx 1011
Instruction Code Fx: 0000 Fx: 0001 Fx: 0010 Fx: 0011 to 1111
0010 Rn Rm 00MD MOV.B Rm, @Rn MOV.W Rm, @Rn MOV.L Rm, @Rn
0010 Rn Rm 01MD MOV.B Rm, @−Rn MOV.W Rm, @−Rn MOV.L Rm, @−Rn DIV0S Rm, Rn
0010 Rn Rm 11MD CMP/STR Rm, Rn XTRCT Rm, Rn MULU.W Rm, Rn MULSW Rm, Rn
0011 Rn Rm 01MD DIV1 Rm, Rn DMULU.L Rm,Rn CMP/HI Rm, Rn CMP/GT Rm, Rn
0011 Rn Rm 11MD ADD Rm, Rn DMULS.L Rm,Rn ADDC Rm, Rn ADDV Rm, Rn
0100 Rn 00MD 0011 STC.L SR, @−Rn STC.L GBR, @−Rn STC.L VBR, @−Rn STC.L SSR, @−Rn
0100 Rn 01MD 0011 STC.L SPC, @−Rn STC.L MOD, @−Rn STC.L RS, @−Rn STC.L RE, @−Rn
0100 Rm 10MD 0110 LDS.L @Rm+, X0 LDS.L @Rm+, X1 LDS.L @Rm+, Y0 LDS.L @Rm+, Y1
Instruction Code Fx: 0000 Fx: 0001 Fx: 0010 Fx: 0011 to 1111
0100 Rm 00MD 0111 LDC.L @Rm+, SR LDC.L @Rm+, GBR LDC.L @Rm+, VBR LDC.L @Rm+, SSR
0100 Rm 01MD 0111 LDC.L @Rm+, SPC LDC.L @Rm+, MOD LDC.L @Rm+, RS LDC.L @Rm+, RE
0100 Rm 00MD 1010 LDS Rm, MACH LDS Rm, MACL LDS Rm, PR
0100 Rm 10MD 1010 LDS Rm, X0 LDS Rm, X1 LDS Rm, Y0 LDS Rm, Y1
0100 Rm 00MD 1110 LDC Rm, SR LDC Rm, GBR LDC Rm, VBR LDC Rm, SSR
0100 Rm 01MD 1110 LDC Rm, SPC LDC Rm, MOD LDC Rm, RS LDC Rm, RE
0110 Rn Rm 00MD MOV.B @Rm, Rn MOV.W @Rm, Rn MOV.L @Rm, Rn MOV Rm, Rn
0110 Rn Rm 01MD MOV.B @Rm+, Rn MOV.W @Rm+, Rn MOV.L @Rm+, Rn NOT Rm, Rn
0110 Rn Rm 10MD SWAP.B Rm, Rn SWAP.W Rm, Rn NEGC Rm, Rn NEG Rm, Rn
0110 Rn Rm 11MD EXTU.B Rm, Rn EXTU.W Rm, Rn EXTS.B Rm, Rn EXTS.W Rm, Rn
Instruction Code Fx: 0000 Fx: 0001 Fx: 0010 Fx: 0011 to 1111
1000 11MD imm/disp LDRS @(disp:8,PC) BT/S disp: 8 LDRE @(disp:8,PC) BF/S disp: 8
1100 10MD imm TST #imm: 8, R0 AND #imm: 8, R0 XOR #imm: 8, R0 OR #imm: 8, R0
1111 10** ******** MOVX.W, MOVY.W Double data transfer instruction, with DSP parallel operation instruction (32-
bit instruction )
The virtual memory system that came into being in this way is particularly effective in a time-
sharing system (TSS) in which a number of processes are running simultaneously (figure 4.1 (3)).
If processes running in a TSS had to take mapping onto virtual memory into consideration while
running, it would not be possible to increase efficiency. Virtual memory is thus used to reduce this
load on the individual processes and so improve efficiency (figure 4.1 (4)). In the virtual memory
system, virtual memory is allocated to each process. The task of the MMU is to perform efficient
mapping of these virtual memory areas onto physical memory. It also has a memory protection
feature that prevents one process from inadvertently accessing another process’s physical memory.
When address translation from virtual memory to physical memory is performed using the MMU,
it may occur that the relevant translation information is not recorded in the MMU, with the result
that one process may inadvertently access the virtual memory allocated to another process. In this
case, the MMU will generate an exception, change the physical memory mapping, and record the
new address translation information.
Although the functions of the MMU could also be implemented by software alone, the need for
translation to be performed by software each time a process accesses physical memory would
result in poor efficiency. For this reason, a buffer for address translation (translation look-aside
buffer: TLB) is provided in hardware to hold frequently used address translation information. The
TLB can be described as a cache for storing address translation information. Unlike cache
memory, however, if address translation fails, that is, if an exception is generated, switching of
address translation information is normally performed by software. This makes it possible for
memory management to be performed flexibly by software.
The MMU has two methods of mapping from virtual memory to physical memory: a paging
method using fixed-length address translation, and a segment method using variable-length
address translation. With the paging method, the unit of translation is a fixed-size address space
(usually of 1 to 64 kbytes) called a page.
In the following text, the address space in virtual memory is referred to as virtual address space,
and address space in physical memory as physical memory space.
Virtual
memory
Process 1 Process 1 MMU
Physical Physical
Physical memory memory
memory
Process 1
(1) (2)
Virtual
Process 1 Process 1 memory
MMU
Physical Physical
memory memory
Process 2 Process 2
Process 3
Process 3
(3) (4)
This LSI supports a 32-bit virtual address space that enables access to a 4-Gbyte address space. As
shown in figures 4.2 and 4.3, the virtual address space is divided into several areas. In privileged
mode, a 4-Gbyte space comprising areas P0 to P4 are accessible. In user mode, a 2-Gbyte space of
U0 area is accessible, and a 16-Mbyte space of Uxy area is also accessible if the DSP bit in the SR
register is set to 1. Access to any area (excluding the U0 area and Uxy area) in user mode will
result in an address error.
If the MMU is enabled by setting the AT bit in the MMUCR register to 1, P0, P3, and U0 areas
can be used as any physical address area in 1- or 4-kbyte page units. By using an 8-bit address
space identifier, P0, P2, and U0 areas can be increased to up to 256 areas. Mapping from virtual
address to 29-bit physical address can be achieved by the TLB.
The P0, P3, and U0 areas can be address translated by the TLB and can be accessed through the
cache. If the MMU is enabled, these areas can be mapped to any physical address space in 1- or 4-
kbyte page units via the TLB. If the CE bit in the cache control register (CCR1) is set to 1 and if
the corresponding cache enable bit (C bit) of the TLB entry is set to 1, access via the cache is
enabled. If the MMU is disabled, replacing the upper three bits of an address in these areas with 0s
creates the address in the corresponding physical address space. If the CE bit in the CCR1 register
is set to 1, access via the cache is enabled. When the cache is used, either the copy-back or write-
through mode is selected for write access via the WT bit in CCR1.
If these areas are mapped to the on-chip module control register area or on-chip memory area in
area 1 in the physical address space via the TLB, the C bit of the corresponding page must be
cleared to 0.
(b) P1 Area
The P1 area can be accessed via the cache and cannot be address-translated by the TLB. Whether
the MMU is enabled or not, replacing the upper three bits of an address in these areas with 0s
creates the address in the corresponding physical address space. Use of the cache is determined by
the CE bit in the cache control register (CCR1). When the cache is used, either the copy-back or
write-through mode is selected for write access by the CB bit in the CCR1 register.
(c) P2 Area
The P2 area cannot be accessed via the cache and cannot be address-translated by the TLB.
Whether the MMU is enabled or not, replacing the upper three bits of an address in this area with
0s creates the address in the corresponding physical address space.
(d) P4 Area
The P4 area is mapped to the on-chip I/O of this LSI. This area cannot be accessed via the cache
and cannot be address-translated by the TLB. Figure 4.4 shows the configuration of the P4 area.
H'E000 0000
Reserved
H'F000 0000
Cache address array
H'F100 0000
Cache data array
H'F200 0000
TLB address array
H'F300 0000
TLB data array
H'F400 0000
Reserved
H'FC00 0000
Control register area
H'FFFF FFFF
The area from H'F000 0000 to H'F0FF FFFF is for direct access to the cache address array. For
more information, see section 5.4, Memory-Mapped Cache.
The area from H'F100 0000 to H'F1FF FFFF is for direct access to the cache data array. For more
information, see section 5.4, Memory-Mapped Cache.
The area from H'F200 0000 to H'F2FF FFFF is for direct access to the TLB address array. For
more information, see section 4.6, Memory-Mapped TLB.
The area from H'F300 0000 to H'F3FF FFFF is for direct access to the TLB data array. For more
information, see section 4.6, Memory-Mapped TLB.
The area from H'FC00 0000 to H'FFFF FFFF is reserved for registers of the on-chip peripheral
modules. For more information, see section 37, List of Registers.
The Uxy area is mapped to the on-chip memory of this LSI. This area is made usable in user mode
when the DSP bit in the SR register is set to 1. In user mode, accessing this area when the DSP bit
is 0 will result in an address error. This area cannot be accessed via the cache and cannot be
address-translated by the TLB. For more information on the Uxy area, see section 6, X/Y
Memory.
This LSI supports a 29-bit physical address space. As shown in figure 4.5, the physical address
space is divided into eight areas. Area 1 is mapped to the on-chip module control register area and
on-chip memory area. Area 7 is reserved.
For details on physical address space, refer to section 9, Bus State Controller (BSC).
H'0000 0000
Area 0
H'0400 0000
Area 1
(On-chip registers and
On-chip memories)
H'0800 0000
Area 2
H'0C00 0000
Area 3
H'1000 0000
Area 4
H'1400 0000
Area 5
H'1800 0000
Area 6
H'1C00 0000
Area 7
(Reserved)
H'1FFF FFFF
When the MMU is enabled, the virtual address space is divided into units called pages. Physical
addresses are translated in page units. Address translation tables in external memory hold
information such as the physical address that corresponds to the virtual address and memory
protection codes. When an access to area P1 or P2 occurs, there is no TLB access and the physical
address is defined uniquely by hardware. If it belongs to area P0, P3 or U0, the TLB is searched
by virtual address and, if that virtual address is registered in the TLB, the access hits the TLB. The
corresponding physical address and the page control information are read from the TLB and the
physical address is determined.
If the virtual address is not registered in the TLB, a TLB miss exception occurs and processing
will shift to the TLB miss handler. In the TLB miss handler, the TLB address translation table in
external memory is searched and the corresponding physical address and the page control
information are registered in the TLB. After returning from the handler, the instruction that caused
the TLB miss is re-executed. When the MMU is enabled, address translation information that
results in a physical address space of H'2000 0000 to H'FFFF FFFF should not be registered in the
TLB.
When the MMU is disabled, masking the upper three bits of the virtual address to 0s creates the
address in the corresponding physical address space. Since this LSI supports 29-bit address space
as physical address space, the upper three bits of the virtual address are ignored as shadow areas.
For details, refer to section 9, Bus State Controller (BSC). For example, address H'0000 1000 in
the P0 area, address H'8000 1000 in the P1 area, address H'A000 1000 in the P2 area, and address
H'C000 1000 in the P3 area are all mapped to the same physical memory. If these addresses are
accessed while the cache is enabled, the upper three bits are always cleared to 0 to guarantee the
continuity of addresses stored in the address array of the cache.
(4) Single Virtual Memory Mode and Multiple Virtual Memory Mode
There are two virtual memory modes: single virtual memory mode and multiple virtual memory
mode. In single virtual memory mode, multiple processes run in parallel using the virtual address
space exclusively and the physical address corresponding to a given virtual address is specified
uniquely. In multiple virtual memory mode, multiple processes run in parallel sharing the virtual
address space, so a given virtual address may be translated into different physical addresses
depending on the process. By the value set to the MMU control register (MMUCR), either single
or multiple virtual mode is selected.
In terms of operation, the only difference between single virtual memory mode and multiple
virtual memory mode is in the TLB address comparison method (see section 4.3.3, TLB Address
Comparison).
In multiple virtual memory mode, the address space identifier (ASID) is used to differentiate
between processes running in parallel and sharing virtual address space. The ASID is eight bits in
length and can be set by software setting of the ASID of the currently running process in page
table entry register high (PTEH) within the MMU. When the process is switched using the ASID,
the TLB does not have to be purged.
In single virtual memory mode, the ASID is used to provide memory protection for processes
running simultaneously and using the virtual address space exclusively (see section 4.3.3, TLB
Address Comparison).
The MMU has the following registers. Refer to section 37, List of Registers, for more details on
the addresses and access size of these registers.
The page table entry register high (PTEH) register residing at address H'FFFF FFF0, which
consists of a virtual page number (VPN) and ASID. The VPN set is the VPN of the virtual address
at which the exception is generated in case of an MMU exception or address error exception.
When the page size is 4 kbytes, the VPN is the upper 20 bits of the virtual address, but in this case
the upper 22 bits of the virtual address are set. The VPN can also be modified by software. As the
ASID, software sets the number of the currently executing process. The VPN and ASID are
recorded in the TLB by the LDTLB instruction.
A program that modifies the ASID in PTEH should be allocated in the P1 or P2 areas.
Initial
Bit Bit Name Value R/W Description
31 to 10 VPN R/W The Number of the Logical Page
9, 8 All 0 R Reserved
These bits are always read as 0. The write value
should always be 0.
7 to 0 ASID R/W Address Space Identifier
The page table entry register low (PTEL) register residing at address H'FFFF FFF4, and used to
store the physical page number and page management information to be recorded in the TLB by
the LDTLB instruction. The contents of this register are only modified in response to a software
command.
Initial
Bit Bit Name Value R/W Description
31 to 29 All 0 R/W Reserved
These bits are always read as 0. The write value
should always be 0.
28 to 10 PPN R/W The Number of the Physical Page
9 0 R Page Management Information
8 V R/W For more details, see section 4.3, TLB Functions.
7 0 R
6, 5 PR R/W
4 SZ R/W
3 C R/W
2 D R/W
1 SH R/W
0 0 R
The translation table base register (TTB) residing at address H'FFFF FFF8, which points to the
base address of the current page table. The hardware does not set any value in TTB automatically.
TTB is available to software for general purposes. The initial value is undefined.
The MMU control register (MMUCR) residing at address H'FFFF FFE0. Any program that
modifies MMUCR should reside in the P1 or P2 area.
Initial
Bit Bit Name Value R/W Description
31 to 9 All 0 R Reserved
These bits are always read as 0. The write value should
always be 0.
8 SV 0 R/W Single Virtual Memory Mode
0: Multiple virtual memory mode
1: Single virtual memory mode
7, 6 All 0 R Reserved
These bits are always read as 0. The write value should
always be 0.
5, 4 RC All 0 R/W Random Counter
A 2-bit random counter that is automatically updated by
hardware according to the following rules in the event of
an MMU exception.
When a TLB miss exception occurs, all of TLB entry
way corresponding to the virtual address at which the
exception occurred are checked. If all ways are valid, 1
is added to RC; if there is one or more invalid way, they
are set by priority from way 0, in the order way 0, way 1,
way 2, way 3. In the event of an MMU exception other
than a TLB miss exception, the way which caused the
exception is set in RC.
3 0 R Reserved
This bit is always read as 0. The write value should
always be 0.
2 TF 0 R/W TLB Flush
Write 1 to flush the TLB (clear all valid bits of the TLB to
0). When they are read, 0 is always returned.
1 IX 0 R/W Index Mode
0: VPN bits 16 to 12 are used as the TLB index number.
1: The value obtained by EX-ORing ASID bits 4 to 0 in
PTEH and VPN bits 16 to 12 is used as the TLB
index number.
0 AT 0 R/W Address Translation
Enables/disables the MMU.
0: MMU disabled
1: MMU enabled
The TLB caches address translation table information located in the external memory. The address
translation table stores the virtual page number and the corresponding physical number, the
address space identifier, and the control information for the page, which is the unit of address
translation. Figure 4.6 shows the overall TLB configuration. The TLB is 4-way set associative
with 128 entries. There are 32 entries for each way. Figure 4.7 shows the configuration of virtual
addresses and TLB entries.
Way 0 to 3 Way 0 to 3
Entry 1 Entry 1
Entry 31 Entry 31
31 10 9 0
VPN Offset
31 12 11 0
VPN Offset
Virtual address (4-kbyte page)
(15) (2) (8) (1) (19) (2) (1) (1) (1) (1)
VPN (31 to 17) VPN (11 to 10) ASID V PPN PR SZ C D SH
TLB entry
[Legend]
VPN: Virtual page number
Upper 19 bits of virtual address for a 1-kbyte page, or upper 20 bits of logical address for a 4-kbyte page. Since VPN
bits 16 to 12 are used as the index number, they are not stored in the TLB entry. Attention must be paid to the
synonym problem (see section 4.4.4, Avoiding Synonym Problems).
ASID: Address space identifier
Indicates the process that can access a virtual page. In single virtual memory mode and user mode, or in multiple
virtual memory mode, if the SH bit is 0, the address is compared with the ASID in PTEH when address comparison is
performed.
SH: Share status bit
0: Page not shared between processes
1: Page shared between processes
SZ: Page-size bit
0: 1-kbyte page
1: 4-kbyte page
V: Valid bit
Indicates whether entry is valid.
0: Invalid
1: Valid
Cleared to 0 by a power-on reset. Not affected by a manual reset.
PPN: Physical page number
Upper 22 bits of physical address. PPN bits 11 to10 are not used in case of a 4-kbyte page.
PR: Protection key field
2-bit field encoded to define the access rights to the page.
00: Reading only is possible in privileged mode.
01: Reading/writing is possible in privileged mode.
10: Reading only is possible in privileged/user mode.
11: Reading/writing is possible in privileged/user mode.
C: Cacheable bit
Indicates whether the page is cacheable.
0: Non-cacheable
1: Cacheable
D: Dirty bit
Indicates whether the page has been written to.
0: Not written to
1: Written to
The TLB uses a 4-way set associative scheme, so entries must be selected by index. VPN bits 16
to 12 and ASID bits 4 to 0 in PTEH are used as the index number regardless of the page size. The
index number can be generated in two different ways depending on the setting of the IX bit in
MMUCR.
1. When IX = 1, VPN bits 16 to 12 are EX-ORed with ASID bits 4 to 0 to generate a 5-bit index
number
2. When IX = 0, VPN bits 16 to 12 alone are used as the index number
The first method is used to prevent lowered TLB efficiency that results when multiple processes
run simultaneously in the same virtual address space (multiple virtual memory) and a specific
entry is selected by indexing of each process. In single virtual memory mode (MMUCR.SV = 1),
IX bit should be set to 0. Figures 4.8 and 4.9 show the indexing schemes.
ASID(4 to 0)
Exclusive-OR
Index
Way 0 to 3
31
Virtual address
31 17 16 12 11 0
Index
Way 0 to 3
31
The results of address comparison determine whether a specific virtual page number is registered
in the TLB. The virtual page number of the virtual address that accesses external memory is
compared to the virtual page number of the indexed TLB entry. The ASID within the PTEH is
compared to the ASID of the indexed TLB entry. All four ways are searched simultaneously. If
the compared values match, and the indexed TLB entry is valid (V bit = 1), the hit is registered.
It is necessary to have software ensure that TLB hits do not occur simultaneously in more than one
way, as hardware operation is not guaranteed if this occurs. An example of setting which causes
TLB hits to occur simultaneously in more than one way is described below. It is necessary to
ensure that this kind of setting is not made by software.
1. If there are two identical TLB entries with the same VPN and a setting is made such that a
TLB hit is made only by a process with ASID = H'FF when one is in the shared state (SH = 1)
and the other in the non-shared state (SH = 0), then if the ASID in PTEH is set to H'FF, there
is a possibility of simultaneous TLB hits in both these ways.
2. If several entries which have different ASID with the same VPN are registered in single virtual
memory mode, there is the possibility of simultaneous TLB hits in more than one way when
accessing the corresponding page in privileged mode. Several entries with the same VPN must
not be registered in single virtual memory mode.
3. There is the possibility of simultaneous TLB hits in more than one way. These hits may occur
depending on the contents of ASID in PTEH when a page to which SH is set 1 is registered in
the TLB in index mode (MMUCR.IX = 1). Therefore a page to which SH is set 1 must not be
registered in index mode. When memory is shared by several processings, different pages must
be registered in each ASID.
The object compared varies depending on the page management information (SZ, SH) in the TLB
entry. It also varies depending on whether the system supports multiple virtual memory or single
virtual memory.
The page-size information determines whether VPN (11 to 10) is compared. VPN (11 to 10) is
compared for 1-kbyte pages (SZ = 0) but not for 4-kbyte pages (SZ = 1).
The sharing information (SH) determines whether the PTEH.ASID and the ASID in the TLB entry
are compared. ASIDs are compared when there is no sharing between processes (SH = 0) but not
when there is sharing (SH = 1).
When single virtual memory is supported (MMUCR.SV = 1) and privileged mode is engaged
(SR.MD = 1), all process resources can be accessed. This means that ASIDs are not compared
when single virtual memory is supported and privileged mode is engaged. The objects of address
comparison are shown in figure 4.10.
SH = 1 or No
(SR.MD = 1 and
MMUCR.SV = 1)?
Yes
No (4-kbyte) No (4-kbyte)
SZ = 0? SZ = 0?
In addition to the SH and SZ bits, the page management information of TLB entries also includes
D, C, and PR bits.
The D bit of a TLB entry indicates whether the page is dirty (i.e., has been written to). If the D bit
is 0, an attempt to write to the page results in an initial page write exception. For physical page
swapping between secondary memory and main memory, for example, pages are controlled so that
a dirty page is paged out of main memory only after that page is written back to secondary
memory. To record that there has been a write to a given page in the address translation table in
memory, an initial page write exception is used.
The C bit in the entry indicates whether the referenced page resides in a cacheable or non-
cacheable area of memory. When the control registers and on-chip memory in area 1 are mapped,
set the C bit to 0. The PR field specifies the access rights for the page in privileged and user modes
and is used to protect memory. Attempts at non-permitted accesses result in TLB protection
violation exceptions.
Access states designated by the D, C, and PR bits are shown in table 4.1.
1. The MMU decodes the virtual address accessed by a process and performs address translation
by controlling the TLB in accordance with the MMUCR settings.
2. In address translation, the MMU receives page management information from the TLB, and
determines the MMU exception and whether the cache is to be accessed (using the C bit). For
details of the determination method and the hardware processing, see section 4.5, MMU
Exceptions.
When single virtual memory mode is used, it is possible to create a state in which physical
memory access is enabled in the privileged mode only by clearing the share status bit (SH) to 0 to
specify recording of all TLB entries. This strengthens inter-process memory protection, and
enables special access levels to be created in the privileged mode only.
Recording a 1- or 4- kbyte page TLB entry may result in a synonym problem. See section 4.4.4,
Avoiding Synonym Problems.
The load TLB instruction (LDTLB) is used to record TLB entries. When the IX bit in MMUCR is
0, the LDTLB instruction changes the TLB entry in the way specified by the RC bit in MMUCR
to the value specified by PTEH and PTEL, using VPN bits 16 to 12 specified in PTEH as the
index number. When the IX bit in MMUCR is 1, the EX-OR of VPN bits 16 to 12 specified in
PTEH and ASID bits 4 to 0 in PTEH are used as the index number.
When an MMU exception occurs, the virtual page number of the virtual address that caused the
exception is set in PTEH by hardware. The way is set in the RC bit in MMUCR for each exception
according to the rules (see section 4.2.4, MMU Control Register (MMUCR)). Consequently, if the
LDTLB instruction is issued after setting only PTEL in the MMU exception processing routine,
TLB entry recording is possible. Any TLB entry can be updated by software rewriting of PTEH
and the RC bits in MMUCR.
As the LDTLB instruction changes address translation information, there is a risk of destroying
address translation information if this instruction is issued in the P0, U0, or P3 area. Make sure,
therefore, that this instruction is issued in the P1 or P2 area. Also, an instruction associated with an
access to the P0, U0, or P3 area (such as the RTE instruction) should be issued at least two
instructions after the LDTLB instruction.
MMUCR
31 9 0
0 SV 0 0 RC 0 TF IX AT
Write Write
Way 0 to 3
31
When a 1- or 4-kbyte page is recorded in a TLB entry, a synonym problem may arise. If a number
of virtual addresses are mapped onto a single physical address, the same physical address data will
be recorded in a number of cache entries, and it will not be possible to guarantee data congruity.
The reason that this problem occurs is explained below with reference to figure 4.12.
The relationship between bit n of the virtual address and cache size is shown in the following
table. Note that no synonym problems occur in 4-kbyte page when the cache size is 16 kbytes.
To achieve high-speed operation of this LSI’s cache, an index number is created using virtual
address bits 12 to 4. When a 1-kbyte page is used, virtual address bits 12 to 10 is subject to
address translation and when a 4-kbyte page is used, a virtual address bit 12 is subject to address
translation. Therefore, the physical address bits 12 to 10 may not be the same as the virtual address
bits 12 to 10.
For example, assume that, with 1-kbyte page TLB entries, TLB entries for which the following
translation has been performed are recorded in two TLBs:
Virtual address 1 is recorded in cache entry H'000, and virtual address 2 in cache entry H'0C0.
Since two virtual addresses are recorded in different cache entries despite the fact that the physical
addresses are the same, memory inconsistency will occur as soon as a write is performed to either
virtual address.
Consequently, the following restrictions apply to the recording of address translation information
in TLB entries.
1. When address translation information whereby a number of 1-kbyte page TLB entries are
translated into the same physical address is recorded in the TLB, ensure that the VPN bits 12 is
the same.
2. When address translation information whereby a number of 4-kbyte page TLB entries are
translated into the same physical address is recorded in the TLB, ensure that the VPN bit 12 is
the same.
3. Do not use the same physical addresses for address translation information of different page
sizes.
The above restrictions apply only when performing accesses using the cache.
Note: When multiple items of address translation information use the same physical memory to
provide for future SuperH RISC engine family expansion, ensure that the VPN bits 20 to
10 are the same.
Virtual address 12 to 4
Physical address
28 13 12 11 10 0
PPN Offset Cache
Physical address 28 to 10
Virtual address 12 to 4
Physical address
28 13 12 11 10 0
PPN Offset Cache
Physical address 28 to 10
A TLB miss results when the virtual address and the address array of the selected TLB entry are
compared and no match is found. TLB miss exception processing includes both hardware and
software operations.
• Hardware Operations
In a TLB miss, this hardware executes a set of prescribed operations, as follows:
A. The VPN field of the virtual address causing the exception is written to the PTEH register.
B. The virtual address causing the exception is written to the TEA register.
C. Either exception code H'040 for a load access, or H'060 for a store access, is written to the
EXPEVT register.
D. The PC value indicating the address of the instruction in which the exception occurred is
written to the save program counter (SPC). If the exception occurred in a delay slot, the PC
value indicating the address of the related delayed branch instruction is written to the SPC.
E The contents of the status register (SR) at the time of the exception are written to the save
status register (SSR).
F. The mode (MD) bit in SR is set to 1 to place the privileged mode.
G. The block (BL) bit in SR is set to 1 to mask any further exception requests.
H. The register bank (RB) bit in SR is set to 1.
I. The RC field in the MMU control register (MMUCR) is incremented by 1 when all entries
indexed are valid. When some entries indexed are invalid, the smallest way number of
them is set in RC. The setting priority is way0, way1, way2, and way3.
J. Execution branches to the address obtained by adding the value of the VBR contents and
H'0000 0400 to invoke the user-written TLB miss exception handler.
A TLB protection violation exception results when the virtual address and the address array of the
selected TLB entry are compared and a valid entry is found to match, but the type of access is not
permitted by the access rights specified in the PR field. TLB protection violation exception
processing includes both hardware and software operations.
• Hardware Operations
In a TLB protection violation exception, this hardware executes a set of prescribed operations,
as follows:
A. The VPN field of the virtual address causing the exception is written to the PTEH register.
B. The virtual address causing the exception is written to the TEA register.
C. Either exception code H'0A0 for a load access, or H'0C0 for a store access, is written to the
EXPEVT register.
D. The PC value indicating the address of the instruction in which the exception occurred is
written into SPC (if the exception occurred in a delay slot, the PC value indicating the
address of the related delayed branch instruction is written into SPC).
E. The contents of SR at the time of the exception are written to SSR.
F. The MD bit in SR is set to 1 to place the privileged mode.
G. The BL bit in SR is set to 1 to mask any further exception requests.
H. The RB bit in SR is set to 1.
I. The way that generated the exception is set in the RC field in MMUCR.
J. Execution branches to the address obtained by adding the value of the VBR contents and
H'0000 0100 to invoke the TLB protection violation exception handler.
A TLB invalid exception results when the virtual address is compared to a selected TLB entry
address array and a match is found but the entry is not valid (the V bit is 0). TLB invalid exception
processing includes both hardware and software operations.
• Hardware Operations
In a TLB invalid exception, this hardware executes a set of prescribed operations, as follows:
A. The VPN field of the virtual address causing the exception is written to the PTEH register.
B. The virtual address causing the exception is written to the TEA register.
C. Either exception code H'040 for a load access, or H'060 for a store access, is written to the
EXPEVT register.
D. The PC value indicating the address of the instruction in which the exception occurred is
written to the SPC. If the exception occurred in a delay slot, the PC value indicating the
address of the delayed branch instruction is written to the SPC.
E. The contents of SR at the time of the exception are written into SSR.
F. The mode (MD) bit in SR is set to 1 to place the privileged mode.
G. The block (BL) bit in SR is set to 1 to mask any further exception requests.
H. The RB bit in SR is set to 1.
I. The way number causing the exception is written to RC in MMUCR.
J. Execution branches to the address obtained by adding the value of the VBR contents and
H'0000 0100, and the TLB protection violation exception handler starts.
An initial page write exception results in a write access when the virtual address and the address
array of the selected TLB entry are compared and a valid entry with the appropriate access rights
is found to match, but the D (dirty) bit of the entry is 0 (the page has not been written to). Initial
page write exception processing includes both hardware and software operations.
• Hardware Operations
In an initial page write exception, this hardware executes a set of prescribed operations, as
follows:
A. The VPN field of the virtual address causing the exception is written to the PTEH register.
B. The virtual address causing the exception is written to the TEA register.
C. Exception code H'080 is written to the EXPEVT register.
D. The PC value indicating the address of the instruction in which the exception occurred is
written to the SPC. If the exception occurred in a delay slot, the PC value indicating the
address of the related delayed branch instruction is written to the SPC.
E. The contents of SR at the time of the exception are written to SSR.
F. The MD bit in SR is set to 1 to place the privileged mode.
G. The BL bit in SR is set to 1 to mask any further exception requests.
H. The RB bit in SR is set to 1.
I. The way that caused the exception is set in the RC field in MMUCR.
J. Execution branches to the address obtained by adding the value of the VBR contents and
H'0000 0100 to invoke the user-written initial page write exception handler.
If a CPU address error or MMU exception occurs in a specific instruction in the repeat loop, the
SPC may indicate an illegal address or the repeat loop cannot be reexecuted correctly even if the
SPC is correct. Accordingly, if a CPU address error or MMU exception occurs in a specific
instruction in the repeat loop, this LSI generates a specific exception code to set the EXPEVT to
H′070 for a TLB miss exception, TLB invalid exception, initial page write exception, and CPU
address error and to H'0D0 for a TLB protection violation exception. In addition, a vector offset
for TLB miss exception is H'100. For details, refer to section 7.4.3, Exception in Repeat Control
Period.
Start
Yes
Address error?
CPU address No
error
SH = 0 and
No (MMUCR.SV = 0 or
SR.MD = 0)?
Yes
No
VPNs match?
VPNs
No and ASIDs
Yes match?
Yes
No
V = 1?
PR? PR?
00/01 10 11 01/11 00/10
W W W W
R/W? R/W? R/W? R/W?
R R R R
No
D = 1?
Yes
Memory Cache
access access
The address array is assigned to H'F200 0000 to H'F2FF FFFF. To access an address array, the 32-
bit address field (for read/write operations) and 32-bit data field (for write operations) must be
specified. The address field specifies information for selecting the entry to be accessed; the data
field specifies the VPN, V bit and ASID to be written to the address array (figure 4.14 (1)).
In the address field, specify the entry address for selecting the entry (bits 16 to 12), W for
selecting the way (bits 9 to 8) and H′F2 to indicate address array access (bits 31 to 24). The IX bit
in MMUCR indicates whether an EX-OR is taken of the entry address and ASID.
The data array is assigned to H'F300 0000 to H'F3FF FFFF. To access a data array, the 32-bit
address field (for read/write operations), and 32-bit data field (for write operations) must be
specified. The address section specifies information for selecting the entry to be accessed; the data
section specifies the longword data to be written to the data array (figure 4.14 (2)).
In the address section, specify the entry address for selecting the entry (bits 16 to 12), W for
selecting the way (bits 9 to 8), and H'F3 to indicate data array access (bits 31 to 24). The IX bit in
MMUCR indicates whether an EX-OR is taken of the entry address and ASID.
Both reading and writing use the longword of the data array specified by the entry address and
way number. The access size of the data array is fixed at longword.
• Read Access
31 24 23 17 16 12 1110 9 8 7 6 2 1 0
Address field 1 1 1 1 0 0 1 0 *............* VPN * * W 0 * . . . . . . . . . * 00
31 17 16 12 1110 9 8 7 0
Data field VPN 0 . . . . . . . 0 VPN 0 V ASID
• Write Access
31 24 23 17 16 12 11 10 9 8 7 6 2 1 0
Address field 1 1 1 1 0 0 1 0 *............* VPN * * W 0 * . . . . . . . . . * 00
31 17 16 12 11 10 9 8 7 0
Data field VPN * . . . . . . . * VPN * V ASID
• Read/Write Access
31 24 23 17 16 12 1110 9 8 7 2 1 0
Address field 1 1 1 1 0 0 1 1 *............* VPN * * W * . . . . . . . . . . . * 00
31 29 28 10 9 8 7 6 5 4 3 2 1 0
Data field 0 0 0 PPN X V X PR SZ C D SH X
Figure 4.14 Specifying Address and Data for Memory-Mapped TLB Access
Specific TLB entries can be invalidated by writing 0 to the entry’s V bit. R0 specifies the write
data and R1 specifies the address.
This example reads the data section of a specific TLB entry. The bit order indicated in the data
field in figure 4.17 (2) is read. R0 specifies the address and the data section of a selected entry is
read to R1.
Section 5 Cache
5.1 Features
• Capacity: 16 or 32 kbytes
• Structure: Instructions/data mixed, 4-way set associative
• Locking: Way 2 and way 3 are lockable
• Line size: 16 bytes
• Number of entries: 256 entries/way in 16-kbyte mode to 512 entries/way in 32-kbyte mode
• Write system: Write-back/write-through is selectable for spaces P0, P1, P3, and U0
Group 1 (P0, P3, and U0 areas)
Group 2 (P1 area)
• Replacement method: Least-recently used (LRU) algorithm
Note: After power-on reset or manual reset, initialized as 16-kbyte mode (256 entries/way).
The cache mixes instructions and data and uses a 4-way set associative system. It is composed of
four ways (banks), and each of which is divided into an address section and a data section. Note
that the following sections will be described for the 16-kbyte mode as an example. For other cache
size modes, change the number of entries and size/way according to table 5.1. Each of the address
and data sections is divided into 256 entries. The entry data is called a line. Each line consists of
16 bytes (4 bytes × 4). The data capacity per way is 4 kbytes (16 bytes × 256 entries) in the cache
as a whole (4 ways). The cache capacity is 16 kbytes as a whole.
. . .
. . .
. . .
. . .
. . .
. . .
The V bit indicates whether the entry data is valid. When the V bit is 1, data is valid; when 0, data
is not valid. The U bit indicates whether the entry has been written to in write-back mode. When
the U bit is 1, the entry has been written to; when 0, it has not. The tag address holds the physical
address used in the external memory access. It is composed of 22 bits (address bits 31 to 10) used
for comparison during cache searches.
In this LSI, the top three of 32 physical address bits are used as shadow bits (see section 9, Bus
State Controller (BSC)), and therefore the top three bits of the tag address are cleared to 0.
The V and U bits are initialized to 0 by a power-on reset, but are not initialized by a manual reset.
The tag address is not initialized by either a power-on or manual reset.
Holds a 16-byte instruction or data. Entries are registered in the cache in line units (16 bytes). The
data array is not initialized by a power-on or manual reset.
(3) LRU
With the 4-way set associative system, up to four instructions or data with the same entry address
can be registered in the cache. When an entry is registered, LRU shows which of the four ways it
is recorded in. There are six LRU bits, controlled by hardware. A least-recently-used (LRU)
algorithm is used to select the way.
Six LRU bits indicate the way to be replaced, when a cache miss occurs. Table 5.2 shows the
relationship between the LRU bits and the way to be replaced when the cache locking mechanism
is disabled. (For the relationship when the cache locking mechanism is enabled, refer to section
5.2.2, Cache Control Register 2 (CCR2).) If a bit pattern other than those listed in table 5.2 is set
in the LRU bits by software, the cache will not function correctly. When modifying the LRU bits
by software, set one of the patterns listed in table 5.2.
The LRU bits are initialized to H'000000 by a power-on reset, but are not initialized by a manual
reset.
Table 5.2 LRU and Way Replacement (when Cache Locking Mechanism is Disabled)
The cache is enabled or disabled using the CE bit in CCR1. CCR1 also has a CF bit (which
invalidates all cache entries), and WT and CB bits (which select either write-through mode or
write-back mode). Programs that change the contents of the CCR1 register should be placed in
address space that is not cached.
Initial
Bit Bit Name Value R/W Description
31 to 4 All 0 R Reserved
These bits are always read as 0. The write value should
always be 0.
3 CF 0 R/W Cache Flush
Writing 1 flushes all cache entries (clears the V, U, and
LRU bits of all cache entries to 0). This bit is always
read as 0. Write-back to external memory is not
performed when the cache is flushed.
2 CB 0 R/W Write-Back
Indicates the cache’s operating mode for space P1.
0: Write-through mode
1: Write-back mode
1 WT 0 R/W Write-Through
Indicates the cache’s operating mode for spaces P0,
U0, and P3.
0: Write-back mode
1: Write-through mode
0 CE 0 R/W Cache Enable
Indicates whether the cache function is used.
0: The cache function is not used.
1: The cache function is used.
The CCR2 register controls the cache locking mechanism in cache lock mode only. The CPU
enters the cache lock mode when the DSP bit (bit 12) in the status register (SR) is set to 1 or the
lock enable bit (bit 16) in the cache control register 2 (CCR2) is set to 1. The cache locking
mechanism is disabled in non-cache lock mode (DSP bit = 0).
When a prefetch instruction (PREF@Rn) is issued in cache lock mode and a cache miss occurs,
the line of data pointed to by Rn will be loaded into the cache, according to the setting of bits 9
and 8 (W3LOAD, W3LOCK) and bits 1 and 0 (W2LOAD, W2LOCK in CCR2).
Table 5.3 shows the relationship between the settings of bits and the way that is to be replaced
when the cache is missed by a prefetch instruction.
On the other hand, when the cache is hit by a prefetch instruction, new data is not loaded into the
cache and the valid entry is held. For example, a prefetch instruction is issued while bits
W3LOAD and W3LOCK are set to 1 and the line of data to which Rn points is already in way 0,
the cache is hit and new data is not loaded into way 3.
In cache lock mode, bits W3LOCK and W2LOCK restrict the way that is to be replaced, when
instructions other than the prefetch instruction are issued. Table 5.4 shows the relationship
between the settings of bits in CCR2 and the way that is to be replaced when the cache is missed
by instructions other than the prefetch instruction.
Programs that change the contents of the CCR2 register should be placed in address space that is
not cached.
Initial
Bit Bit Name Value R/W Description
31 to 17 All 0 R Reserved
These bits are always read as 0. The write value
should always be 0.
16 LE 0 R/W Lock enable (LE)
Controls cache lock mode.
0: Enters cache lock mode when the DSP bit in the SR
register is set to 1.
1: Enters cache lock mode regardless of the DSP bit
value.
15 to 10 All 0 R Reserved
These bits are always read as 0. The write value
should always be 0.
9 W3LOAD 0 R/W Way 3 Load (W3LOAD)
8 W3LOCK 0 R/W Way 3 Lock (W3LOCK)
When the cache is missed by a prefetch instruction
while in cache lock mode and when bits W3LOAD and
W3LOCK in CCR2 are set to 1, the data is always
loaded into way 3. Under any other condition, the
prefetched data is loaded into the way to which LRU
points.
7 to 2 All 0 R Reserved
These bits are always read as 0. The write value
should always be 0.
1 W2LOAD 0 R/W Way 2 Load (W2LOAD)
0 W2LOCK 0 R/W Way 2 Lock (W2LOCK)
When the cache is missed by a prefetch instruction
while in cache lock mode and when bits W2LOAD and
W2LOCK in CCR2 are set to 1, the data is always
loaded into way 2. Under any other condition, the
prefetched data is loaded into the way to which LRU
points.
Note: W2LOAD and W3LOAD should not be set to 1 at the same time.
Table 5.3 Way Replacement when a PREF Instruction Misses the Cache
Table 5.4 Way Replacement when Instructions other than the PREF Instruction Miss the
Cache
Table 5.5 LRU and Way Replacement (when W2LOCK = 1 and W3LOCK =0)
Table 5.6 LRU and Way Replacement (when W2LOCK = 0 and W3LOCK =1)
Table 5.7 LRU and Way Replacement (when W2LOCK = 1 and W3LOCK =1)
The CCR3 register controls the cache size to be used. The cache size must be specified according
to the LSI to be selected. If the specified cache size exceeds the size of cache incorporated in the
LSI, correct operation cannot be guaranteed. Note that programs that change the contents of the
CCR3 register should be placed in un-cached address space. In addition, note that all cache entries
must be invalidated by setting the CF bit in the CCR1 to 1 before accessing the cache after the
CCR3 is modified.
Initial
Bit Bit Name Value R/W Description
31 to 24 All 0 R Reserved
These bits are always read as 0. The write value
should always be 0.
23 to 16 CSIZE7 to H'01 R/W Cache Size
CSIZE0 Specify the cache size as shown below.
0000 0001: 16-kbyte cache
0000 0010: 32-kbyte cache
Settings other than above are prohibited.
15 to 0 All 0 R Reserved
These bits are always read as 0. The write value
should always be 0.
5.3 Operation
If the cache is enabled (the CE bit in CCR1 = 1), whenever instructions or data in spaces P0, P1,
P3, and U0 are accessed the cache will be searched to see if the desired instruction or data is in the
cache. Figure 5.2 illustrates the method by which the cache is searched. The cache is a physical
cache and holds physical addresses in its address section. The example of operation in 16-kbyte
mode is described below:
Entries are selected using bits 11 to 4 of the address (virtual) of the access to memory and the tag
address of that entry is read. In parallel with reading the tag address, the virtual address is
converted into the physical address. The virtual address of the access to memory and the physical
address (tag address) read from the address array are compared. The address comparison uses all
four ways. When the comparison shows a match and the selected entry is valid (V = 1), a cache hit
occurs. When the comparison does not show a match or the selected entry is not valid (V = 0), a
cache miss occurs. Figure 5.2 shows a hit on way 1.
Virtual address
31 12 11 4 3 21 0
Ways 0 to 3 Ways 0 to 3
255
Physical address
Hit signal 1
In a read access, instructions and data are transferred from the cache to the CPU. The LRU is
updated to indicate that the hit way is the most recently hit way.
An external bus cycle starts and the entry is updated. The way to be replaced is shown in table 5.4.
Entries are updated in 16-byte units. When the desired instruction or data that caused the miss is
loaded from external memory to the cache, the instruction or data is transferred to the CPU in
parallel with being loaded to the cache. When it is loaded to the cache, the U bit is cleared to 0 and
the V bit is set to 1 to indicate that the hit way is the most recently hit way. When the U bit for the
entry which is to be replaced by entry updating in write-back mode is 1, the cache-update cycle
starts after the entry is transferred to the write-back buffer. After the cache completes its update
cycle, the write-back buffer writes the entry back to the memory. Transfer is in 16-byte units.
The LRU is updated to indicate that the hit way is the most recently hit way. The other contents of
the cache are not changed. Instructions and data are not transferred from the cache to the CPU.
Instructions and data are not transferred from the cache to the CPU. The way that is to be replaced
is shown in table 5.3. The other operations are the same as those for a read miss.
In a write access in write-back mode, the data is written to the cache and no external memory
write cycle is issued. The U bit of the entry that has been written to is set to 1, and the LRU is
updated to indicate that the hit way is the most recently hit way. In write-through mode, the data is
written to the cache and an external memory write cycle is issued. The U bit of the entry that has
been written to is not updated, and the LRU is updated to indicate that the hit way is the most
recently hit way.
In write-back mode, an external write cycle starts when a write miss occurs, and the entry is
updated. The way to be replaced is shown in table 5.4. When the U bit of the entry which is to be
replaced by entry updating is 1, the cache-update cycle starts after the entry has been transferred to
the write-back buffer. Data is written to the cache and the U bit and the V bit are set to 1. The
LRU is updated to indicate that the replaced way is the most recently updated way. After the cache
has completed its update cycle, the write-back buffer writes the entry back to the memory.
Transfer is in 16-byte units. In write-through mode, no write to cache occurs in a write miss; the
write is only to the external memory.
When the U bit of the entry to be replaced in write-back mode is 1, the entry must be written back
to the external memory. To increase performance, the entry to be replaced is first transferred to the
write-back buffer and fetching of new entries to the cache takes priority over writing back to the
external memory. After the fetching of new entries to the cache completes, the write-back buffer
writes the entry back to the external memory. During the write-back cycles, the cache can be
accessed. The write-back buffer can hold one line of cache data (16 bytes) and its physical
address. Figure 5.3 shows the configuration of the write-back buffer.
Use software to ensure coherency between the cache and the external memory. When memory
shared by this LSI and another device is placed in an address space to which caching applies, use
the memory-mapped cache to make the data invalid and written back, as required. Memory that is
shared by this LSI’s CPU and DMAC should also be handled in this way.
The address array is mapped onto H'F0000000 to H'F0FFFFFF. To access an address array, the
32-bit address field (for read/write accesses) and 32-bit data field (for write accesses) must be
specified. The address field specifies information for selecting the entry to be accessed; the data
field specifies the tag address, V bit, U bit, and LRU bits to be written to the address array.
In the address field, specify the entry address for selecting the entry, W for selecting the way, A
for enabling or disabling the associative operation, and H'F0 for indicating address array access.
As for W, B'00 indicates way 0, B'01 indicates way 1, B'10 indicates way 2, and B'11 indicates
way 3.
In the data field, specify the tag address, LRU bits, U bit, and V bit. Figure 5.4 shows the address
and data formats in 16-byte mode. For other cache size modes, change the entry address and Was
shown in table 5.8. The following three operations are available in the address array.
Read the tag address, LRU bits, U bit, and V bit for the entry that corresponds to the entry address
and way specified by the address field of the read instruction. In reading, the associative operation
is not performed, regardless of whether the associative bit (A bit) specified in the address is 1 or 0.
Write the tag address, LRU bits, U bit, and V bit, specified by the data field of the write
instruction, to the entry that corresponds to the entry address and way as specified by the address
field of the write instruction. Ensure that the associative bit (A bit) in the address field is set to 0.
When writing to a cache line for which the U bit = 1 and the V bit =1, write the contents of the
cache line back to memory, then write the tag address, LRU bits, U bit, and V bit specified by the
data field of the write instruction. Always clear the uppermost 3 bits (bits 31 to 29) of the tag
address to 0. When 0 is written to the V bit, 0 must also be written to the U bit for that entry.
When writing with the associative bit (A bit) of the address = 1, the addresses in the four ways for
the entry specified by the address field of the write instruction are compared with the tag address
that is specified by the data field of the write instruction. If the MMU is enabled in this case, a
virtual address specified by data is translated into a physical address via the TLB before
comparison. Write the U bit and the V bit specified by the data field of the write instruction to the
entry of the way that has a hit. However, the tag address and LRU bits remain unchanged. When
there is no way that receives a hit, nothing is written and there is no operation. This function is
used to invalidate a specific entry in the cache. When the U bit of the entry that has received a hit
is 1 at this point, writing back should be performed. However, when 0 is written to the V bit, 0
must also be written to the U bit of that entry.
The data array is mapped onto H'F1000000 to H'F1FFFFFF. To access a data array, the 32-bit
address field (for read/write accesses) and 32-bit data field (for write accesses) must be specified.
The address field specifies information for selecting the entry to be accessed; the data field
specifies the longword data to be written to the data array.
In the address field, specify the entry address for selecting the entry, L for indicating the longword
position within the (16-byte) line, W for selecting the way, and H'F1 for indicating data array
access. As for L, B'00 indicates longword 0, B'01 indicates longword 1, B'10 indicates longword
2, and B'11 indicates longword 3. As for W, B'00 indicates way 0, B′01 indicates way 1, B'10
indicates way 2, and B′11 indicates way 3.
Since access size of the data array is fixed at longword, bits 1 and 0 of the address field should be
set to B'00.
Figure 5.4 shows the address and data formats in 16-kbyte mode. For other cache size modes,
change the entry address and W as shown in table 5.8.
The following two operations on the data array are available. The information in the address array
is not affected by these operations.
Read the data specified by L of the address filed, from the entry that corresponds to the entry
address and the way that is specified by the address filed.
Write the longword data specified by the data filed, to the position specified by L of the address
field, in the entry that corresponds to the entry address and the way specified by the address field.
Read access
31 24 23 14 13 12 11 4 3 2 0
Write access
31 24 23 14 13 12 11 4 3 2 0
Longword
Figure 5.4 Specifying Address and Data for Memory-Mapped Cache Access
(16-kbyte mode)
Table 5.8 Address Format Based on the Size of Cache to be Assigned to Memory
Specific cache entries can be invalidated by writing 0 to the entry’s V bit in the memory-mapped
cache access. When the A bit is 1, the tag address specified by the write data is compared to the
tag address within the cache selected by the entry address, and a match is found, the entry is
written back if the entry’s U bit is 1 and the V bit and U bit specified by the write data are written.
If no match is found, there is no operation. In the example shown below, R0 specifies the write
data and R1 specifies the address.
To read the data field of a specific entry is enabled by the memory-mapped cache access. The
longword indicated in the data field of the data array in figure 5.4 is read into the register. In the
example shown below, R0 specifies the address and R1 shows what is read.
6.1 Features
• Page
There are four pages. The X memory is divided into two pages (pages 0 and 1) and the Y
memory is divided into two pages (pages 0 and 1).
• Memory map
The X/Y memory is located in the virtual address space, physical address space, and X-bus and
Y-bus address spaces.
In the virtual address space, this memory is located in the addresses shown in table 6.1. These
addresses are included in space P2 (when SR.MD = 1) or Uxy (when SR.MD = 0 and SR.DSP
= 1) according to the CPU operating mode.
On the other hand, this memory is located in a part of area 1 in the physical address space. When
this memory is accessed from the physical address space, addresses in which the upper three bits
are 0 in addresses shown in table 6.1 are used. In the X-bus and Y-bus address spaces, addresses in
which the upper 16 bits are ignored in addresses of X memory and Y memory shown in table 6.1
are used.
• Ports
Each page has three independent read/write ports and is connected to each bus. The X memory
is connected to the I bus, X bus, and L bus. The Y memory is connected to the I bus, Y bus,
and L bus. The L bus is used when this memory is accessed from the virtual address space.
The I bus is used when this memory is accessed from the physical address space. The X bus
and Y bus are used when this memory is accessed from the X-bus and Y-bus address spaces.
• Priority order
In the event of simultaneous accesses to the same page from different buses, the accesses are
processed according to the priority order. The priority order is: I bus > X bus > L bus in the X
memory and I bus > Y bus > L bus in the Y memory.
6.2 Operation
Methods for accessing by the CPU are directly via the L bus from the virtual addresses, and via
the I bus after the virtual addresses are converted to be the physical addresses using the MMU. As
long as a conflict on the page does not occur, access via the L bus is performed in one cycle.
Several cycles are necessary for accessing via the I bus. According to the CPU operating mode,
access from the CPU is as follows:
The X/Y memory can be accessed by the CPU directly from space P2. The MMU can be used to
map the virtual addresses in spaces P0 and P3 to this memory.
The X/Y memory can be accessed by the CPU directly from space Uxy. The MMU can be used to
map the virtual addresses in space U0 to this memory.
The MMU can be used to map the virtual addresses in space U0 to this memory.
With a X data transfer instruction and a Y data transfer instruction, the X/Y memory is always
accessed via the X bus or Y bus. As long as a conflict on the page does not occur, access via the X
bus or Y bus is performed in one cycle. The X memory access via the X bus and the Y memory
access via the Y bus can be performed simultaneously.
In the case of a single data transfer instruction, methods for accessing from the DSP are directly
via the L bus from the virtual addresses, and via the I bus after the virtual addresses are converted
to be the physical addresses using the MMU. As long as a conflict on the page does not occur,
access via the L bus is performed in one cycle. Several cycles are necessary for accessing via the I
bus. According to the CPU operating mode, access from the CPU is as follows:
The X/Y memory can be accessed by the DSP directly from space P2. The MMU can be used to
map the virtual addresses in spaces P0 and P3 to this memory.
The X/Y memory can be accessed by the DSP directly from space Uxy. The MMU can be used to
map the virtual addresses in space U0 to this memory.
The X/Y memory is always accessed by bus master modules such as the DMAC and USB host via
the I bus, which is a physical address bus. Addresses in which the upper three bits are 0 in
addresses shown in table 6.1 must be used.
In the event of simultaneous accesses to the same page from different buses, the conflict on the
pages occurs. Although each access is completed correctly, this kind of conflict tends to lower
X/Y memory accessibility. Therefore it is advisable to provide software measures to prevent such
conflict as far as possible. For example, conflict will not arise if different memory or different
pages are accessed by each bus.
The I bus is shared by several bus master modules. When the X/Y memory is accessed via the I
bus, a conflict between the other I-bus master modules may occur on the I bus. This kind of
conflict tends to lower X/Y memory accessibility. Therefore it is advisable to provide software
measures to prevent such conflict as far as possible. For example, by accessing the X/Y memory
by the CPU not via the I bus but directly from space P2 or Uxy, conflict on the I bus can be
prevented.
When the X/Y memory is accessed via the I bus using the cache from the CPU and DSP, correct
operation cannot be guaranteed. If the X/Y memory is accessed while the cache is enabled
(CCR1.CE = 1), it is advisable to access the X/Y memory via the L bus from space P2 or Uxy. If
the X/Y memory is accessed from space P0, P3, or U0, it is advisable to access the X/Y memory
via the I bus, which does not use the cache, with MMU setting enabled (MMUCR.AT = 1) and
cache disabled (C bit = 0) as page attributes. Since access using the MMU occurs via the I bus,
several cycles are necessary (the number of necessary cycles varies according to the ratio between
the internal clock (Iφ) and bus clock (Bφ) or the operation state of the DMAC). In a program that
requires high performance, it is advisable to access the X/Y memory from space P2 or Uxy. The
relationship described above is summarized in table 6.2.
In sleep mode, I bus master modules such as the DMAC cannot access the X/Y memory.
Transferring control to a user-defined exception processing routine and executing the process to
support the above functions are called exception handling. This LSI has two types of exceptions:
general exceptions and interrupts. The user can execute the required processing by assigning
exception handling routines corresponding to the required exception processing and then return to
the source program.
A reset input can terminate the normal program execution and pass control to the reset vector after
register initialization. This reset operation can also be regarded as an exception handling. This
section describes an overview of the exception handling operation. Here, general exceptions and
interrupts are referred to as exception handling. For interrupts, this section describes only the
process executed for interrupt requests. For details on how to generate an interrupt request, refer to
section 8, Interrupt Controller (INTC).
31 10 9 21 0
0 TRA 0 TRA
31 12 11 0
0 EXPEVT EXPEVT
31 12 11 0
0 INTEVT INTEVT
31 12 11 0
0 INTEVT2 INTEVT2
31 0
TEA TEA
TRA is assigned to address H'FFFFFFD0 and consists of the 8-bit immediate data (imm) of the
TRAPA instruction. TRA is automatically specified by the hardware when the TRAPA instruction
is executed. Only bits 9 to 2 of the TRA can be re-written using the software.
Initial
Bit Bit Name Value R/W Description
31 to 10 R Reserved
These bits are always read as 0. The write value
should always be 0.
9 to 2 TRA R/W 8-bit Immediate Data
1, 0 R Reserved
These bits are always read as 0. The write value
should always be 0.
EXPEVT is assigned to address H'FFFFFFD4 and consists of a 12-bit exception code. Exception
codes to be specified in EXPEVT are those for resets and general exceptions. These exception
codes are automatically specified the hardware when an exception occurs. Only bits 11 to 0 of
EXPEVT can be re-written using the software.
Initial
Bit Bit Name Value R/W Description
31 to 12 All 0 R Reserved
These bits are always read as 0. The write value
should always be 0.
11 to 0 EXPEVT * R/W 12-bit Exception Code
Note: Initialized to H'000 at power-on reset and H'020 at manual reset.
INTEVT is assigned to address H'FFFFFFD8 and stores an exception code or a code which
indicates interrupt priority order. A code to be specified when an interrupt occurs is determined by
an interrupt source. (For details, see section 8.4.6, Interrupt Exception Handling and Priority.)
These exception and interrupt priority order codes are automatically specified by the hardware
when an exception occurs. INTEVT can be modified using the software. Only bits 11 to 0 of
INTEVT can be modified using the software.
Initial
Bit Bit Name Value R/W Description
31 to 12 All 0 R Reserved
These bits are always read as 0. The write value
should always be 0.
11 to 0 INTEVT R 12-bit Exception Code
INTEVT2 is assigned to address H'A4000000 and consists of a 12-bit exception code. Exception
codes to be specified in INTEVT2 are those for interrupt requests. These exception codes are
automatically specified by the hardware when an exception occurs. INTEVT2 cannot be modified
using the software.
Initial
Bit Bit Name Value R/W Description
31 to 12 All 0 R Reserved
These bits are always read as 0. The write value
should always be 0.
11 to 0 INTEVT2 R 12-bit Exception Code
TEA is assigned to address H'FFFFFFFC and the virtual address for an exception occurrence is
stored in this register when an exception related to memory accesses occurs. TEA can be modified
using the software.
Initial
Bit Bit Name Value R/W Description
31 to 0 TEA All 0 R/W The virtual address for an exception occurrence
In exception handling, the contents of the program counter (PC) and status register (SR) are saved
in the saved program counter (SPC) and saved status register (SSR), respectively, and execution of
the exception handler is invoked from a vector address. By executing the return from exception
handler (RTE) in the exception handler routine, it restores the contents of PC and SR, and returns
to the processor state at the point of interruption and the address where the exception occurred.
A basic exception handling sequence consists of the following operations. If an exception occurs
and the CPU accepts it, operations 1 to 8 are executed.
The above operations from 1 to 8 are executed in sequence. During these operations, no other
exceptions may be accepted unless multiple exception acceptance is enabled.
In an exception handling routine for a general exception, the appropriate exception handling must
be executed based on an exception source determined by the EXPEVT. In an interrupt exception
handling routine, the appropriate exception handling must be executed based on an exception
source determined by the INTEVT or INTEVT2. After the exception handling routine has been
completed, program execution can be resumed by executing an RTE instruction. The RTE
instruction causes the following operations to be executed.
1. The contents of the SSR are restored into the SR to return to the processing state in effect
before the exception handling took place.
2. A delay slot instruction of the RTE instruction is executed.*2
3. Control is passed to the address stored in the SPC.
The above operations from 1 to 3 are executed in sequence. During these operations, no other
exceptions may be accepted. By changing the SPC and SSR before executing the RTE instruction,
a status different from that in effect before the exception handling can also be specified.
Notes: 1. The MMU registers are also modified if an MMU exception occurs.
2. For details on the CPU processing mode in which RTE delay slot instructions are
executed, please refer to section 7.5, Usage Notes.
A vector address for general exceptions is determined by adding a vector offset to a vector base
address. The vector offset for general exceptions other than the TLB miss exception is
H'00000100. The vector offset for interrupts is H'00000600. The vector base address is loaded into
the vector base register (VBR) using the software. The vector base address should reside in the P1
or P2 fixed physical address space.
The exception codes are written to bits 11 to 0 of the EXPEVT (for reset or general exceptions) or
the INTEVT and INTEVT2 (for interrupt requests) to identify each specific exception event. See
section 8, Interrupt Controller (INTC), for details of the exception codes for interrupt requests.
Table 7.1 lists exception codes for resets and general exceptions.
The BL bit in SR is set to 1 when a reset or exception is accepted. While the BL bit is set to 1,
acceptance of general exceptions is restricted as described below, making it possible to effectively
prevent multiple exceptions from being accepted.
If the BL bit is set to 1, an interrupt request is not accepted and is retained. The interrupt request is
accepted when the BL bit is cleared to 0. If the CPU is in low power consumption mode, an
interrupt is accepted even if the BL bit is set to 1 and the CPU returns from the low power
consumption mode.
A DMA error is not accepted and is retained if the BL bit is set to 1 and accepted when the BL bit
is cleared to 0. User break requests generated while the BL bit is set are ignored and are not
retained. Accordingly, user breaks are not accepted even if the BL bit is cleared to 0.
If a general exception other than a DMA address error or user break occurs while the BL bit is set
to 1, the CPU enters a state similar to that in effect immediately after a reset, and passes control to
the reset vector (H'A0000000) (multiple exception). In this case, unlike a normal reset, modules
other than the CPU are not initialized, the contents of EXPEVT, SPC, and SSR are undefined, and
this status is not detected by an external device.
To enable acceptance of multiple exceptions, the contents of SPC and SSR must be saved while
the BL bit is set to 1 after an exception has been accepted, and then the BL bit must be cleared to
0. Before restoring the SPC and SSR, the BL bit must be set to 1.
Resets and interrupts are requested asynchronously regardless of the program flow. In general
exceptions, a DMA address error and a user break under the specific condition are also requested
asynchronously. The user cannot expect on which instruction an exception is requested. For
general exceptions other than a DMA address error and a user break under a specific condition,
each general exception corresponds to a specific instruction.
All exceptions are classified into two types: a re-execution type and a processing-completion type.
If a re-execution type exception is accepted, the current instruction executed when the exception is
accepted is terminated and the instruction address is saved to the SPC. After returning from the
exception processing, program execution resumes from the instruction where the exception was
accepted. In a processing-completion type exception, the current instruction executed when the
exception is accepted is completed, the next instruction address is saved to the SPC, and then the
exception processing is executed.
During a delayed branch instruction and delay slot, the following operations are executed. A re-
execution type exception detected in a delay slot is accepted before executing the delayed branch
instruction. A processing-completion type exception detected in a delayed branch instruction or a
delay slot is accepted when the delayed branch instruction has been executed. In this case, the
acceptance of delayed branch instruction or a delay slot precedes the execution of the branch
destination instruction. In the above description, a delay slot indicates an instruction following an
Acceptance priorities are determined for all exception requests. The priority of resets, general
exceptions, and interrupts are determined in this order: a reset is always accepted regardless of the
CPU status. Interrupts are accepted only when resets or general exceptions are not requested.
If multiple general exceptions occur simultaneously in the same instruction, the priority is
determined as follows.
Only one exception is accepted at a time. Accepting multiple exceptions sequentially results in all
exception requests being processed.
7.3.1 Resets
• Conditions
Power-on reset is request
• Operations
Set EXPEVT to H'000, initialize the CPU and on-chip peripheral modules, and branch to the
reset vector H'A0000000. For details, refer to the register descriptions in the relevant sections.
• Conditions
Manual reset is request
• Operations
Set EXPEVT to H'020, initialize the CPU and on-chip peripheral modules, and branch to the
reset vector H'A0000000. For details, refer to the register descriptions in the relevant sections.
• Conditions
Instruction is fetched from odd address (4n + 1, 4n + 3)
Word data is accessed from addresses other than word boundaries (4n + 1, 4n + 3)
Longword is accessed from addresses other than longword boundaries (4n + 1, 4n + 2,
4n + 3)
The area ranging from H'80000000 to H'FFFFFFFF in virtual space is accessed in user
mode
• Types
Instruction synchronous, re-execution type
• Save address
Instruction fetch: An instruction address to be fetched when an exception occurred
Data access: An instruction address where an exception occurs (a delayed branch instruction
address if an instruction is assigned to a delay slot)
• Exception code
An exception occurred during read: H'0E0
An exception occurred during write: H'100
• Remarks
The virtual address (32 bits) that caused the exception is set in TEA.
• Conditions
When undefined code not in a delay slot is decoded
Delayed branch instructions: JMP, JSR, BRA, BRAF, BSR, BSRF, RTS, RTE, BT/S, BF/S
Note: For details on undefined code, refer to table 2.12. When an undefined code other than
H'F000 to H'FFFF is decoded, operation cannot be guaranteed.
• Conditions
When undefined code in a delay slot is decoded
Delayed branch instructions: JMP, JSR, BRA, BRAF, BSR, BSRF, RTS, RTE, BT/S, BF/S
When a privileged instruction in a delay slot is decoded in user mode
Privileged instructions: LDC, STC, RTE, LDTLB, SLEEP; instructions that access GBR
with LDC/STC are not privileged instructions.
When an instruction that rewrites PC in a delay slot is decoded
Instructions that rewrite PC: JMP, JSR, BRA, BRAF, BSR, BSRF, RTS, RTE, BT, BF,
BT/S, BF/S, TRAPA, LDC Rm, SR, LDC.L @Rm+, SR
• Types
Instruction synchronous, re-execution type
• Save address
A delayed branch instruction address
• Exception code
H'1A0
• Remarks
None
• Conditions
TRAPA instruction executed
• Types
Instruction synchronous, processing-completion type
• Save address
An address of an instruction following TRAPA
• Exception code
H'160
• Remarks
The exception is a processing-completion type, so an instruction after the TRAPA instruction
is saved to SPC. The 8-bit immediate value in the TRAPA instruction is set in TRA[9:2].
• Conditions
When a break condition set in the user break controller is satisfied
• Types
Break (L bus) before instruction execution: Instruction synchronous, re-execution type
Operand break (L bus): Instruction synchronous, processing-completion type
Data break (L bus): Instruction asynchronous, processing-completion type
I bus break: Instruction asynchronous, processing-completion type
• Save address
Re-execution type: An address of the instruction where a break occurs (a delayed branch
instruction address if an instruction is assigned to a delay slot)
Processing-completion type: An address of the instruction following the instruction where a
break occurs (a delayed branch instruction destination address if an instruction is assigned to a
delay slot)
• Exception code
H'1E0
• Remarks
For details on user break controller, refer to section 33, User Break Controller (UBC).
• Conditions
Word data accessed from addresses other than word boundaries (4n + 1, 4n + 3)
Longword accessed from addresses other than longword boundaries (4n + 1, 4n + 2, 4n +
3)
• Types
Instruction asynchronous, processing-completion type
• Save address
An address of the instruction following the instruction where a break occurs (a delayed branch
instruction destination address if an instruction is assigned to a delay slot)
• Exception code
H'5C0
• Remarks
An exception occurs when a DMA transfer is executed while an exception instruction address
described above is specified in the DMAC. Since the DMA transfer is performed
asynchronously with the CPU instruction operation, an exception is also requested
asynchronously with the instruction execution. For details on DMAC, refer to section 10,
Direct Memory Access Controller (DMAC).
When the address translation unit of the memory management unit (MMU) is valid, MMU
exceptions are checked after a CPU address error has been checked. Four types of MMU
exceptions are defined: TLB miss exception, TLB invalid exception, TLB protection exception,
initial page write exception. These exceptions are checked in this order.
A vector offset for a TLB miss exception is defined as H'00000400 to simplify exception source
determination. For details on MMU exception operations, refer to section 4, Memory Management
Unit (MMU).
• Conditions
Comparison of TLB addresses shows no address match.
• Types
Instruction synchronous, re-execution type
• Save address
Instruction fetch: An instruction address to be fetched when an exception occurred
Data access: An instruction address where an exception occurs (a delayed branch instruction
address if an instruction is assigned to a delay slot)
• Exception code
An exception occurred during read: H'040
An exception occurred during write: H'060
• Remarks
• The virtual address (32 bits) that caused the exception is set in TEA, and the MMU register is
updated. The vector address for TLB miss exception is VBR + H'0400. To speed up TLB miss
processing, the offset differs from other exceptions.
• Conditions
Comparison of TLB addresses shows address match but V = 0.
• Types
Instruction synchronous, re-execution type
• Save address
Instruction fetch: An instruction address to be fetched when an exception occurred
Data access: An instruction address where an exception occurs (a delayed branch instruction
address if an instruction is assigned to a delay slot)
• Exception code
An exception occurred during read: H'040
An exception occurred during write: H'060
• Remarks
The virtual address (32 bits) that caused the exception is set in TEA, and the MMU register is
updated.
• Conditions
When a hit access violates the TLB protection information (PR bits).
• Types
Instruction synchronous, re-execution type
• Save address
Instruction fetch: An instruction address to be fetched when an exception occurred
Data access: An instruction address where an exception occurs (a delayed branch instruction
address if an instruction is assigned to a delay slot)
• Exception code
An exception occurred during read: H'0A0
An exception occurred during write: H'0C0
• Remarks
The virtual address (32 bits) that caused the exception is set in TEA, and the MMU register is
updated.
• Conditions
A hit occurred to the TLB for a store access, but D = 0.
• Types
Instruction synchronous, re-execution type
• Save address
Instruction fetch: An instruction address to be fetched when an exception occurred
Data access: An instruction address where an exception occurs (a delayed branch instruction
address if an instruction is assigned to a delay slot)
• Exception code
H'080
• Remarks
The virtual address (32 bits) that caused the exception is set in TEA, and the MMU register is
updated.
In the DSP mode, a DSP extension instruction can be executed. If a DSP extension instruction is
executed when the DSP bit in SR is cleared to 0 (in a mode other than the DSP mode), an illegal
instruction exception occurs.
In the DSP mode, STC and LDC instructions for the SR register can be executed even in user
mode. (Note, however, that only the RC[11:0], DMX, DMY, and RF[1:0] bits in the DSP
extension bits can be changed.)
In the DSP mode, a part of the space P2 (Uxy area: H'A5000000 to H'A5FFFFFF) can be accessed
in user mode and no CPU address error will occur even if the area is accessed.
If an exception is requested or an exception is accepted during repeat control, the exception may
not be accepted correctly or a program execution may not be returned correctly from exception
processing that is different from the normal state. These restrictions may occur from repeat
detection instruction to repeat end instruction while the repeat counter is 1 or more. In this section,
this period is called the repeat control period.
The following shows program examples where the number of instructions in the repeat loop are 4
or more, 3, 2, and 1, respectively. In this section, a repeat detection instruction and its instruction
address are described as RptDtct. The first, second, and third instructions following the repeat
detection instruction are described as RptDtct1, RptDtct2, and RptDtct3. In addition, [A], [B],
[C1], and [C2] in the following examples indicate instructions where a restriction occurs. Table
7.2 summarizes the instruction positions and restriction types.
If an exception is accepted in the repeat control period while the repeat counter (RC[11:0]) in the
SR register is two or greater, the program counter to be saved may not indicate the value to be
returned correctly. To execute the repeat control after returning from an exception processing, the
return address must indicate an instruction prior to a repeat detection instruction. Accordingly, if
an exception is accepted in repeat control period, an exception other than re-execution type
exception by a repeat detection instruction cannot return to the repeat control correctly.
Table 7.3 SPC Value When a Re-Execution Type Exception Occurs in Repeat Control
(SR.RC[11:0]≥2)
If one of the following instructions is executed at the address following RptDtct1, a general illegal
instruction exception occurs. For details on an address to be saved in the SPC, refer to SPC Saved
by an Exception in Repeat Control Period in section 7.4.3, Exception in Repeat Control Period.
• Branch instructions
BRA, BSR, BT, BF, BT/S, BF/S, BSRF, RTS, BRAF, RTE, JSR, JMP, TRAPA
• Repeat control instructions
SETRC, LDRS, LDRE
• Load instructions for SR, RS, and RE
LDC Rn,SR, LDC @Rn+,SR, LDC Rn,RE, LDC @Rn+,RE, LDC Rn,RS, LDC @Rn+, Rs
Note: An extension instruction of this LSI and is not disclosed to the user.
In a repeat loop consisting of one to three instructions, some restrictions apply to repeat
detection instructions and all the remaining instructions. In a repeat loop consisting of four
or more instructions, restrictions apply to only the three instructions that include a repeat
end instruction.
In the repeat control period, an interrupt or some exception will be retained to prevent an
exception acceptance at an instruction where returning from the exception cannot be performed
correctly. For details, refer to repeat loop program examples 1 to 4. In the examples, exceptions
generated at instructions indicated as [B], [C], ([C1], or [C2]), the following processing is
executed.
Note: An interrupt request or a DMA address error exception request is retained in the interrupt
controller (INTC) and the direct memory access controller (DMAC) until the CPU can
accept a request.
If a CPU address error occurs in the repeat control period, the exception is accepted but an
exception code (H'070) indicating the repeat loop period is specified in the EXPEVT. If a CPU
address error occurs in instructions following a repeat detection instruction to repeat end
instruction, an exception code for instruction access or data access is specified in the EXPEVT.
The SPC is saved according to the description, SPC Saved by an Exception in Repeat Control
Period in section 7.4.3, Exception in Repeat Control Period.
After the CPU address error exception processing, the repeat control cannot be returned correctly.
To execute a repeat loop correctly, care must be taken not to generate a CPU address error in the
repeat control period.
Note: In a repeat loop consisting of one to three instructions, some restrictions apply to repeat
detection instructions and all the remaining instructions. In a repeat loop consisting of four
or more instructions, restrictions apply to only the three instructions that include a repeat
end instruction. The restriction occurs when SR.RC[11:0] ≥ 1.
Table 7.5 Instruction Where a Specific Exception Occurs When a Memory Access
Exception Occurs in Repeat Control (SR.RC[11:0]≥1)
If an MMU exception occurs in the repeat control period, a specific exception code is generated as
well as a CPU address error. For a TLB miss exception, TLB invalid exception, and initial page
write exception, an exception code (H'070) indicating the repeat loop period is specified in the
EXPEVT. For a TLB protection exception, an exception code (H'0D0) is specified in the
EXPEVT. In a TLB miss exception, vector offset is specified as H'00000100.
An instruction where an exception occurs and the SPC value to be saved are the same as those for
the CPU address error.
After this exception processing, the repeat control cannot be returned correctly. To execute a
repeat loop correctly, care must be taken not to generate an MMU related exception in the repeat
control period.
Note: In a repeat loop consisting of one to three instructions, some restrictions apply to repeat
detection instructions and all the remaining instructions. In a repeat loop consisting of four
or more instructions, restrictions apply to only the three instructions that include a repeat
end instruction. The restriction occurs when SR.RC[11:0] ≥ 1.
Note: * If an LDC instruction is executed for the SR, the following instructions are re-fetched
and an instruction fetch exception is accepted according to the modified SR value.
8.1 Features
• 16 levels of interrupt priority can be set
By setting the interrupt-priority registers, the priorities of on-chip peripheral modules, and IRQ
and PINT interrupts can be selected from 16 levels for individual request sources.
• NMI noise canceller function
An NMI input-level bit indicates the NMI pin state. By reading this bit in the interrupt
exception service routine, the pin state can be checked, enabling it to be used as a noise
canceller.
• IRQ interrupts can be set
Detection of low level, high level, rising edge, or falling edge
• Interrupt request signal can be externally output (IRQOUT pin)
By notifying the external bus master that the external interrupt and on-chip peripheral module
interrupt requests have been generated, the bus mastership can be requested.
IRLQOUT
NMI
6
IRQ5 to IRQ0 Input/output
4
IRL3 to IRL0 control
16
PINT5 to PINT0
Com- Interrupt
(Interrupt request) parator request
DMAC
SCIF SR
SIOF
I3 I2 I1 I0
TMU
TPU CPU
Priority
WDT identifier
ADC
USBF
USBH
RTC
SIM
LCDC
PCC
MMC
I2C
CMT
AFEIF
SSL
SDHI
REF
PINTER IPR
ICR
IRR0
Internal bus
Bus
interface
INTC
[Legend]
ICR: Interrupt control register
IPR: Interrupt priority register
IRR: Interrupt request register
PINTER: PINT interrupt enable register
REF: Refresh request in bus state controller
Port interrupt input pins PINT15 to Input Input of port interrupt signals
PINT0
Bus request signal pin IRQOUT*2 Output Bus request signal for an interrupt
Notes: 1. IRL3 to IRL0 and IRQ3 to IRQ0 cannot be used simultaneously because these pins are
multiplexed.
2. When the NMI or H-UDI interrupt requests are generated and the response time of CPU
is short, this pin may not be asserted.
IPRA to IPRJ are 16-bit readable/writable registers in which priority levels from 0 to 15 are set for
on-chip peripheral module and IRQ interrupts.
13 IPR13 0 R/W
12 IPR12 0 R/W
11 IPR11 0 R/W
10 IPR10 0 R/W
9 IPR9 0 R/W
8 IPR8 0 R/W
7 IPR7 0 R/W
6 IPR6 0 R/W
5 IPR5 0 R/W
4 IPR4 0 R/W
3 IPR3 0 R/W
2 IPR2 0 R/W
1 IPR1 0 R/W
0 IPR0 0 R/W
As shown in table 8.2, on-chip peripheral module or IRQ interrupts are assigned to four 4-bit
groups in each register. These 4-bit groups (bits 15 to 12, bits 11 to 8, bits 7 to 4, and bits 3 to 0)
are set with values from H'0 (0000) to H'F (1111). Setting H'0 means priority level 0 (masking is
requested); H'F means priority level 15 (the highest level).
ICR0 is a register that sets the input signal detection mode of the external interrupt input pin NMI,
and indicates the input signal level at the NMI pin.
Initial
Bit Bit Name Value R/W Description
15 NMIL 0/1* R NMI Input Level
Sets the level of the signal input at the NMI pin. This bit
can be read from to determine the NMI pin level. This bit
cannot be modified.
0: NMI input level is low
1: NMI input level is high
14 to 9 — All 0 R Reserved
These bits are always read as 0. The write value should
always be 0.
8 NMIE 0 R/W NMI Edge Select
Selects whether the falling or rising edge of the interrupt
request signal at the NMI pin is detected.
0: Interrupt request is detected on falling edge of NMI
input
1: Interrupt request is detected on rising edge of NMI
input
7 to 0 — All 0 R Reserved
These bits are always read as 0. The write value should
always be 0.
Note: * The initial value is 1 when NMI input is high, 0 when NMI input is low.
ICR1 is a 16-bit register that specifies the detection mode for external interrupt input pins IRQ5 to
IRQ0 individually: rising edge, falling edge, high level, or low level.
Initial
Bit Bit Name Value R/W Description
15 MAI 0 R/W All Interrupt Mask
When this bit is set to 1, all interrupt requests are masked
while low level is input to the NMI pin. The NMI interrupt
is masked in standby mode.
0: When the NMI pin is low, all interrupt requests are not
masked
1: When the NMI pin is low, all interrupt requests are
masked
14 IRQLVL 1 R/W Interrupt Request Level Detection
Enables or disables the use of pins IRQ3 to IRQ0 as four
independent interrupt pins. The IRQ4 and IRQ5 are not
affected.
0: Use of pins IRQ3 to IRQ0 as four independent interrupt
pins enabled
1: Use of pins IRL3 to IRL0 as encoded 15 level interrupt
pins
13 BLMSK 0 R/W BL Bit Mask
When the BL bit in the SR register is set to 1, specifies
whether the NMI interrupt is masked.
0: When the BL bit is set to 1, the NMI interrupt is masked
1: The NMI interrupt is accepted regardless of the BL bit
setting
12 — 0 R Reserved
This bit is always read as 0. The write value should
always be 0.
Initial
Bit Bit Name Value R/W Description
11 IRQ51S 0 R/W IRQn Sense Select
10 IRQ50S 0 R/W These bits select whether interrupt request signals
9 IRQ41S 0 R/W corresponding to pins IRQ5 to IRQ0 are detected by a
rising edge, falling edge, high level, or low level.
8 IRQ40S 0 R/W
Bit 2n + 1 Bit 2n
7 IRQ31S 0 R/W
IRQn1S IRQn0S
6 IRQ30S 0 R/W
0 0 Interrupt request is detected on
5 IRQ21S 0 R/W
falling edge of IRQn input
4 IRQ20S 0 R/W
0 1 Interrupt request is detected on
3 IRQ11S 0 R/W rising edge of IRQn input
2 IRQ10S 0 R/W 1 0 Interrupt request is detected on
1 IRQ01S 0 R/W low level of IRQn input
0 IRQ00S 0 R/W 1 1 Interrupt request is detected on
high level of IRQn input
[Legend] n= 0 to 5
IRR0 is an 8-bit register that indicates interrupt requests from the TMU and IRQ0 to IRQ5.
Initial
Bit Bit Name Value R/W Description
7 0 R Reserved
This bit is always read as 0. The write value should
always be 0.
6 TMU_ 0 R/W TMU_SUNI Interrupt Request
SUNIR Indicates whether the TMU_SUNI (TMU) interrupt request
is generated.
0: TMU_SUNI interrupt request is not generated
1: TMU_SUNI interrupt request is generated
5 IRQ5R 0 R/W IRQn Interrupt Request
4 IRQ4R 0 R/W Indicates whether there is interrupt request input to the
3 IRQ3R 0 R/W IRQn pin. When edge-detection mode is set for IRQn, an
interrupt request is cleared by writing 0 to the IRQnR bit
2 IRQ2R 0 R/W after reading IRQnR = 1.
1 IRQ1R 0 R/W When level-detection mode is set for IRQn, these bits
indicate whether an interrupt request is input. The
0 IRQ0R 0 R/W
interrupt request is set/cleared by only 1/0 input to the
IRQn pin.
IRQnR
0: No interrupt request input to IRQn pin
1: Interrupt request input to IRQn pin
[Legend] n = 0 to 5
IRR1 is an 8-bit register that indicates whether interrupt requests from the DMAC are generated.
This register is initialized to H'00 by a power-on reset or manual reset, but is not initialized in
standby mode.
IRR2 is an 8-bit register that indicates whether interrupt requests from the SSL and LCDC are
generated. This register is initialized to H'00 by a power-on reset or manual reset, but is not
initialized in standby mode.
Note: On the models not having the SSL, the SSL-related bits are reserved. The write value
should always be 0.
IRR3 is an 8-bit register that indicates whether interrupt requests from the RTC and SIM are
generated. This register is initialized to H'00 by a power-on reset or manual reset, but is not
initialized in standby mode.
IRR4 is an 8-bit register that indicates whether interrupt requests from the REF, WDT, and TMU
are generated. This register is initialized to H'00 by a power-on reset or manual reset, but is not
initialized in standby mode.
IRR5 is an 8-bit register that indicates whether interrupt requests from the SCIF0, SCIF1, DMAC,
and ADC are generated. This register is initialized to H'00 by a power-on reset or manual reset,
but is not initialized in standby mode.
IRR6 is an 8-bit register that indicates whether interrupt requests from the PINT, SIOF0, and
SIOF1 are generated. This register is initialized to H'00 by a power-on reset or manual reset, but is
not initialized in standby mode.
IRR7 is an 8-bit register that indicates whether interrupt requests from the TPU and IIC are
generated. This register is initialized to H'00 by a power-on reset or manual reset, but is not
initialized in standby mode.
IRR8 is an 8-bit register that indicates whether interrupt requests from the SDHI, MMC, and
AFEIF are generated. This register is initialized to H'00 by a power-on reset or manual reset, but is
not initialized in standby mode.
Note: Note: On the models not having the SDHI, the SDHI-related bits are reserved. The write
value should always be 0.
IRR9 is an 8-bit register that indicates whether interrupt requests from the PCC, USBH, USBF,
and CMT are generated. This register is initialized to H'00 by a power-on reset or manual reset,
but is not initialized in standby mode.
PINTER is a 16-bit register which enables interrupt requests input to the external interrupt input
pins PINT0 to PINT15. This register is initialized to H'0000 by a power-on reset or manual reset,
but is not initialized in standby mode.
10 PINT10E 0 R/W n = 0 to 15
9 PINT9E 0 R/W
8 PINT8E 0 R/W
7 PINT7E 0 R/W
6 PINT6E 0 R/W
5 PINT5E 0 R/W
4 PINT4E 0 R/W
3 PINT3E 0 R/W
2 PINT2E 0 R/W
1 PINT1E 0 R/W
0 PINT0E 0 R/W
INCR2 is a 16-bit register which specifies low or high detection mode to the external interrupt
input pins PINT0 to PINT15 individually. This register is initialized to H'0000 by a power-on reset
or manual reset, but is not initialized in standby mode.
The NMI interrupt has the highest priority level of 16. When the BLMSK bit in the interrupt
control register 1 (ICR1) is 1 or the BL bit in the status register (SR) is 0, NMI interrupts are
accepted if the MAI bit in ICR1 is 0. NMI interrupts are edge-detected. In sleep or standby mode,
the interrupt is accepted regardless of the BL setting. The NMI edge select bit (NMIE) in the
interrupt control register 0 (ICR0) is used to select either rising or falling edge detection.
When using edge-input detection for NMI interrupts, a pulse width of at least two Pφ cycles
(peripheral clock) is necessary. NMI interrupt exception handling does not affect the interrupt
mask bits (I3 to I0) in the status register (SR). When the BL bit is 1, only an NMI interrupt is
accepted if the BLMSK bit in ICR1 is 1.
It is possible to wake the chip up from sleep mode or standby mode with an NMI interrupt.
IRQ interrupts are input by level or edge from pins IRQ0 to IRQ5. The priority level can be set by
interrupt priority registers C and D (IPRC and IPRD) in a range from 0 to 15.
When using edge-sensing for IRQ interrupts, clear the interrupt source by having software read 1
from the corresponding bit in IRR0, then write 0 to the bit.
When ICR1 is rewritten, IRQ interrupts may be mistakenly detected, depending on the IRQ pin
states. To prevent this, rewrite the register while interrupts are masked, then release the mask after
clearing the illegal interrupt by reading the interrupt request register 0 (IRR0) and writing 0 to
IRR0.
Edge input interrupt detection requires input of a pulse width of more than two cycles on a Pφ
clock basis.
When using level-sensing for IRQ interrupts, the pin levels must be retained until the CPU
samples the pins. Therefore, the interrupt source must be cleared by the interrupt handler.
The interrupt mask bits (I3 to I0) in the status register (SR) are not affected by IRQ interrupt
handling. IRQ interrupts specified for edge detection can be used to recover from a standby state
when the corresponding interrupt level is higher than that set in the I3 to I0 bits of the SR register.
(However, when RTC is used, recovering from standby by using the clock for RTC is enabled.)
IRL interrupts are input by pins IRL3 to IRL0 as level. The priority level is the higher level that is
indicated by IRL3 to IRL0 pins. When the values of IRL3 to IRL0 pins are 0 (B'0000), it indicates
the highest level interrupt request (interrupt priority level 15). When the values of the pins are 15
(B'1111), no interrupt is requested (interrupt priority level 0). Figure 8.2 shows an example of
connection for IRL interrupt.
IRL interrupts are included with noise canceller function and detected when the sampled levels of
each peripheral module clock keep same value for 2 cycles. This prevents sampling error level in
IRL pin changing.
IRL interrupts priority level should be kept until interrupt is accepted and its handling is started.
However, changing to higher level is enabled.
The interrupt mask bits I3 to I0 in the status register (SR) are not affected by the IRL interrupt
handling.
Interrupt Priority 4
request encoder IRL3 to IRL0
IRL3 to IRL0
PINT interrupts are input by level from pins PINT0 to PINT15. The priority level of PINT0 to
PINT7 (PINTA) and PINT8 to PINT15 (PINTB) can be set by the interrupt priority level register
H (IPRH) in a range from 0 to 15. The PINT interrupt level should be retained until the interrupt
processing starts after an interrupt request has been accepted.
The interrupt mask bits I3 to I0 in the status register (SR) are not affected by the PIN interrupt
processing routine.
While an RTC clock is supplied, recovery from a standby state on a PINT interrupt is possible if
the interrupt level is higher than that set in the I3 to I0 bits of the SR register.
Not every interrupt source is assigned a different interrupt vector. Sources are reflected in the
interrupt event registers (INTEVT and INTEVT2). It is easy to identify sources by using the value
of INTEVT or INTEVT2 as a branch offset.
A priority level (from 0 to 15) can be set for each module except H-UDI by writing to the interrupt
priority registers A, B, and E to J (IPRA, IPRB, and IPRE to IPRJ). The priority level of the H-
UDI interrupt is 15 (fixed).
The interrupt mask bits (I3 to I0) in the status register are not affected by on-chip peripheral
module interrupt handling.
There are four types of interrupt sources: NMI, IRQ, IRL, and on-chip peripheral modules. The
priority of each interrupt source is set within priority levels 0 to 16; level 16 is the highest and
level 1 is the lowest. When the priority is set to level 0, that interrupt is masked and the interrupt
request is ignored.
Tables 8.3 and 8.4 list the interrupt sources, the codes for the interrupt event registers (INTEVT
and INTEVT2), and the interrupt priority.
Each interrupt source is assigned a unique code by INTEVT and INTEVT2. The start address of
the exception handling routine is common for each interrupt source. This is why, for instance, the
value of INTEVT or INTEVT2 is used as an offset at the start of the exception handling routine
and branched to in order to identify the interrupt source.
IRQ interrupt and on-chip peripheral module interrupt priorities can be set freely between 0 and 15
for each module by setting interrupt priority registers A to J (IPRA to IPRJ). A reset assigns
priority level 0 to IRQ and on-chip peripheral module interrupts.
If the same priority level is assigned to two or more interrupt sources and interrupts from those
sources occur simultaneously, their priority order is the default priority order indicated at the right
in tables 8.3 and 8.4.
Table 8.3 Interrupt Exception Handling Sources and Priority (IRQ Mode)
Interrupt Priority
Interrupt Priority IPR within IPR Default
Interrupt Source Code *1 (Initial Value) (Bit Numbers) Setting Unit Priority
2
NMI H'1C0* 16 High
2
H-UDI H'5E0* 15
3
IRQ IRQ0 H'600* 0 to 15 (0) IPRC (3 to 0)
3
IRQ1 H'620* 0 to 15 (0) IPRC (7 to 4)
3
IRQ2 H'640* 0 to 15 (0) IPRC (11 to 8)
IRQ3 H'660*3 0 to 15 (0) IPRC (15 to 12)
3
IRQ4 H'680* 0 to 15 (0) IPRD (3 to 0)
3
IRQ5 H'6A0* 0 to 15 (0) IPRD (7 to 4)
3
TMU TMU_SUNI H'6C0* 0 to 15 (0) IPRD (11 to 8)
3
DMAC (1) DEI0 H'800* 0 to 15 (0) IPRE (15 to 12) High
3
DEI1 H'820* 0 to 15 (0)
3
DEI2 H'840* 0 to 15 (0)
3
DEI3 H'860* 0 to 15 (0) Low
LCDC LCDCI H'900*3 0 to 15 (0) IPRE (7 to 4)
SSL SSLI H'980*3 0 to 15 (0) IPRE (3 to 0)
3
USBF USBFI0 H'A20* 0 to 15 (0) IPRF (7 to 4) High
3
USBFI1 H'A40* Low
3
USBH USBHI H'A60* 0 to 15 (0) IPRJ (11 to 8)
3
DMAC (2) DEI4 H'B80* 0 to 15 (0) IPRF (11 to 8) High
3
DEI5 H'BA0* Low
3
ADC ADCI H'BE0* 0 to 15 (0) IPRF (15 to 12)
SCIF0 SCIFI0 H'C00*3 0 to 15 (0) IPRG (15 to 12)
SCIF1 SCIFI1 H'C20*3 0 to 15 (0) IPRG (11 to 8)
3
PINT PINTA H'C80* 0 to 15 (0) IPRH (15 to 12)
3
PINTB H'CA0* 0 to 15 (0) IPRH (11 to 8)
3
SIOF0 SIOFI0 H'D00* 0 to 15 (0) IPRI (15 to 12)
3
SIOF1 SIOFI1 H'D20* 0 to 15 (0) IPRI (11 to 8) Low
Interrupt Priority
Interrupt Priority IPR within IPR Default
Interrupt Source Code *1 (Initial Value) (Bit Numbers) Setting Unit Priority
3
TPU TPI0 H'D80* 0 to 15 (0) IPRH (7 to 4) High High
3
TPI1 H'DA0*
TPI2 H'DC0*3
TPI3 H'DE0*3 Low
3
IIC IICI H'E00* 0 to 15 (0) IPRH (3 to 0)
3
MMC MMCI0 H'E80* 0 to 15 (0) IPRI (7 to 4) High
3
MMCI1 H'EA0*
MMCI2 H'EC0*3
MMCI3 H'EE0*3 Low
3
CMT CMI H'F00* 0 to 15 (0) IPRF (3 to 0)
3
PCC PCCI H'F60* 0 to 15 (0) IPRI (3 to 0)
3
SDHI SDI H'F80* 0 to 15 (0) IPRJ (7 to 4)
3
AFEIF AFECI H'FE0* 0 to 15 (0) IPRJ (3 to 0)
2
TMU0 TUNI0 H'400* 0 to 15 (0) IPRA (15 to 12)
2
TMU1 TUNI1 H'420* 0 to 15 (0) IPRA (11 to 8)
2
TMU2 TUNI2 H'440* 0 to 15 (0) IPRA (7 to 4)
2
RTC ATI H'480* 0 to 15 (0) IPRA (3 to 0) High
2
PRI H'4A0*
CUI H'4C0*2 Low
2
SIM ERI H'4E0* 0 to 15 (0) IPRB (7 to 4) High
2
RXI H'500*
TXI H'520*2
TEND H'540*2 Low
2
WDT ITI H'560* 0 to 15 (0) IPRB (15 to 12)
2
REF RCMI H'580* 0 to 15 (0) IPRB (11 to 8) Low
Notes: 1. INTEVT2 code.
2. The code set in INTEVT is as same as INTEVT2.
3. The code set in INTEVT indicates interrupt level H'200 to H'3C0. For the
correspondence of interrupt level and INTEVT, see table 8.5.
Table 8.4 Interrupt Exception Handling Sources and Priority (IRL Mode)
Priority
Interrupt Interrupt Priority IPR within IPR Default
Interrupt Source Code *1 (Initial Value) (Bit Numbers) Setting Unit Priority
2
NMI H'1C0* 16 High
2
H-UDI H'5E0* 15
IRL3 to RL0=B'0000 H'200*
3
IRL 15
IRL3 to IRL0=B'0001 H'220*
3
14
IRL3 to IRL0=B'0010 H'240*
3
13
IRL3 to IRL0=B'0011 H'260*3 12
IRL3 to IRL0=B'0100 H'280*
3
11
IRL3 to IRL0=B'0101 H'2A0*
3
10
IRL3 to IRL0=B'0110 H'2C0*
3
9
IRL3 to IRL0=B'0111 H'2E0*
3
8
IRL3 to IRL0=B'1000 H'300*
3
7
IRL3 to IRL0=B'1001 H'320*
3
6
IRL3 to IRL0=B'1010 H'340*
3
5
IRL3 to IRL0=B'1011 H'360*3 4
IRL3 to IRL0=B'1100 H'380*
3
3
IRL3 to IRL0=B'1101 H'3A0*
3
2
IRL3 to IRL0=B'1110 H'3C0*
3
1
3
IRQ IRQ4 H'680* 0 to 15 (0) IPRD (3 to 0)
3
IRQ5 H'6A0* 0 to 15 (0) IPRD (7 to 4)
IPRD (11 to 8)
3
TMU TMU_SUNI H'6C0* 0 to 15 (0)
3
DMAC DEI0 H'800* 0 to 15 (0) IPRE High
(1) (15 to 12)
DEI1 H'820*3 0 to 15 (0)
3
DEI2 H'840* 0 to 15 (0)
3
DEI3 H'860* 0 to 15 (0) Low
3
LCDC LCDCI H'900* 0 to 15 (0) IPRE (7 to 4)
3
SSL SSLI H'980* 0 to 15 (0) IPRE (3 to 0) Low
Priority
Interrupt Interrupt Priority IPR within IPR Default
Interrupt Source Code *1 (Initial Value) (Bit Numbers) Setting Unit Priority
3
USBF USBFI0 H'A20* 0 to 15 (0) IPRF (7 to 4) High High
3
USBFI1 H'A40* Low
IPRJ (11 to 8)
3
USBH USBHI H'A60* 0 to 15 (0)
DMAC DEI4 H'B80*3 0 to 15 (0) IPRF (11 to 8) High
(2) DEI5 H'BA0*3 Low
3
ADC ADCI H'BE0* 0 to 15 (0) IPRF
(15 to 12)
SCIF0 SCIFI0 H'C00*3 0 to 15 (0) IPRG (15 to
12)
SCIF1 SCUFI1 H'C20*3 0 to 15 (0) IPRG (11 to 8)
3
PINT PINTA H'C80* 0 to 15 (0) IPRH (15 to
12)
PINTB H'CA0*3 0 to 15 (0) IPRH (11 to 8)
IPRI (15 to 12)
3
SIOF0 SIOFI0 H'D00* 0 to 15 (0)
3
SIOF1 SIOFI1 H'D20* 0 to 15 (0) IPRI (11 to 8)
3
TPU TPI0 H'D80* 0 to 15 (0) IPRH (7 to 4) High
3
TPI1 H'DA0*
TPI2 H'DC0*3
TPI3 H'DE0*3 Low
3
IIC IICI H'E00* 0 to 15 (0) IPRH (3 to 0)
3
MMC MMCI0 H'E80* 0 to 15 (0) IPRI (7 to 4) High
3
MMCI1 H'EA0*
MMCI2 H'EC0*3
MMCI3 H'EE0*3 Low
3
CMT CMI H'F00* 0 to 15 (0) IPRF (3 to 0)
3
PCC PCCI H'F60* 0 to 15 (0) IPRI (3 to 0)
3
SDHI SDI H'F80* 0 to 15 (0) IPRJ (7 to 4)
3
AFEIF AFECI H'FE0* 0 to 15 (0) IPRJ (3 to 0) Low
Priority
Interrupt Interrupt Priority IPR within IPR Default
Interrupt Source Code *1 (Initial Value) (Bit Numbers) Setting Unit Priority
2
TMU0 TUNI0 H'400* 0 to 15 (0) IPRA High
(15 to 12)
TMU1 TUNI1 H'420*2 0 to 15 (0) IPRA (11 to 8)
2
TMU2 TUNI2 H'440* 0 to 15 (0) IPRA (7 to 4)
2
RTC ATI H'480* 0 to 15 (0) IPRA (3 to 0) High
2
PRI H'4A0*
CUI H'4C0*2 Low
2
SIM ERI H'4E0* 0 to 15 (0) IPRB (7 to 4) High
2
RXI H'500*
TXI H'520*2
TEND H'540*2 Low
2
WDT ITI H'560* 0 to 15 (0) IPRB (15 to
12)
REF RCMI H'580*2 0 to 15 (0) IPRB (11 to 8) Low
Notes: 1. INTEVT2 code.
2. The code set in INTEVT is as same as INTEVT2.
3. The code set in INTEVT indicates interrupt level H'200 to H'3C0. For the
correspondence of interrupt level and INTEVT, see table 8.5.
8.5 Operation
The sequence of interrupt operations is described below. Figure 8.3 is a flowchart of the
operations.
1. The interrupt request sources send interrupt request signals to the interrupt controller.
2. The interrupt controller selects the highest-priority interrupt from the interrupt requests sent,
following the priority levels set in the interrupt priority registers A to J (IPRA to IPRJ). Lower
priority interrupts are held pending. If two of these interrupts have the same priority level or if
multiple interrupts occur within a single module, the interrupt with the highest priority is
selected, according to table 8.3, Interrupt Exception Handling Sources and Priority (IRQ
Mode) and table 8.4, Interrupt Exception Handling Sources and Priority (IRL Mode).
3. The priority level of the interrupt selected by the interrupt controller is compared with the
interrupt mask bits (I3 to I0) in the status register (SR) of the CPU. If the request priority level
is higher than the level in bits I3 to I0, the interrupt controller accepts the interrupt and sends
an interrupt request signal to the CPU.
4. Detection timing: The INTC operates, and notifies the CPU of interrupt requests, in
synchronization with the peripheral clock (Pφ). The CPU receives an interrupt at a break in
instructions.
5. The interrupt source code is set in the interrupt event registers (INTEVT and INTEVT2).
6. The status register (SR) and program counter (PC) are saved to SSR and SPC, respectively.
7. The block bit (BL), mode bit (MD), and register bank bit (RB) in SR are set to 1.
8. The CPU jumps to the start address of the interrupt handler (the sum of the value set in the
vector base register (VBR) and H'00000600). This jump is not a delayed branch. The interrupt
handler may branch with the INTEVT or INTEVT2 value as its offset in order to identify the
interrupt source. This enables it to branch to the handling routine for the individual interrupt
source.
Notes: 1. The interrupt mask bits (I3 to I0) in the status register (SR) are not changed by
acceptance of an interrupt in this LSI.
2. The interrupt source flag should be cleared in the interrupt handler. To ensure that an
interrupt source that should have been cleared is not inadvertently accepted again, read
the interrupt source flag after it has been cleared, and then clear the BL bit or execute
an RTE instruction.
Program
execution state
Interrupt No
generated?
Yes
SR.BL=0,
No sleep mode,
or standby mode?
Yes
No
NMI?
Yes
Level 15 No
interrupt?
Yes Level 14 No
interrupt?
Yes I3 to I0 levels are
Set interrupt source in Yes Level 1 No
14 or lower?
INTEVT and INTEVT2 interrupt?
No I3 to I0 levels are
Save SR to SSR; Yes
Yes 13 or lower?
save PC to SPC
No
I3 to I0 levels are 0?
Set BL, MD, and RB Yes
bits in SR to 1
No
Branch to exception
handler
When handling multiple interrupts, an interrupt handler should include the following procedures:
When these procedures are followed in order, an interrupt of higher priority than the one being
handled can be accepted after clearing BL in step 4. Figure 8.3 shows a sample interrupt operation
flowchart.
9.1 Features
The BSC has the following features:
• A maximum 32 or 64 Mbytes for each of the eight areas, CS0, CS2 to CS4, CS5A, CS5B,
CS6A and CS6B, totally 384 Mbytes (divided into eight areas).
• A maximum 64 Mbytes for each of the six areas, CS0, CS2 to CS4, CS5, and CS6, totally a
total of 384 Mbytes (divided into six areas).
• Can specify the normal space interface, byte-selection SRAM, burst ROM (clock synchronous
or asynchronous), SDRAM, PCMCIA for each address space.
• Can select the data bus width (8, 16, or 32 bits) for each address space.
• Controls the insertion of the wait state for each address space.
• Controls the insertion of the wait state for each read access and write access.
• Can set the independent idling cycle in the continuous access for five cases: read-write (in
same space/different space), read-read (in same space/different space), or the first cycle is a
write access.
• High-speed access to the ROM that has the page mode function.
• Supports IC memory cards and I/O card interfaces defined in the JEIDA specifications Ver. 4.2
(PCMCIA2.1 Rev 2.1).
• Controls the insertion of the wait state using software.
• Supports the bus sizing function of the I/O bus width (only in little endian mode).
• Shares all of the resources with other CPU and outputs the bus enable after receiving the bus
request from external devices.
Note: The PCMCIA direct interfaces supported by the BSC are only signals and bus protocols
shown in table 9.1. For details on other control signals, see section 29, PC Card Controller
(PCC) (external circuits and this LSI on-chip PC card controller).
Both area 5 and area 6 have the PCMCIA direct interface function which is common to the
SH3. The on-chip PC card controller supports only area 6.
Internal master
module
Internal bus
BACK Bus
BREQ mastership CMNCR Internal slave
controller module
CS0WCR
...
...
Wait
WAIT controller CS6BWCR
RWTCNT
Module bus
...
CS6BBCR
MD5 to MD3
...
A25 to A0,
D31 to D0
BS, RD/WR, RD,
WE3(BE3) to WE0(BE0), Memory
RAS, CAS, controller
CKE, DQMxx,
CE2A, CE2B
CE1A, CE1B
ICIORD, ICIOWR
SDCR
IOIS16
RTCSR
RTCNT
Refresh
REFOUT
controller
Comparator
Interrupt
controller RTCOR
BSC
[Legend]
CMNCR: Common control register
CSnWCR: CSn space wait control register (n = 0, 2, 3, 4, 5A, 5B, 6A, 6B)
RWTCNT: Reset wait counter
CSnBCR: CSn space bus control register (n = 0, 2, 3, 4, 5A, 5B, 6A, 6B)
SDCR: SDRAM control register
RTCSR: Refresh timer control/status register
RTCNT: Refresh timer counter
RTCOR: Refresh time constant register
In the architecture of this LSI, both virtual spaces and physical spaces have 32-bit address spaces.
The upper three bits divide into the P0 to P4 areas, and specify the cache access method. For
details see section 5, Cache. The remaining 29 bits are used for division of the space into ten areas
(address map 1) or eight areas (address map 2) according to the MAP bit in CMNCR setting. The
BSC performs control for this 29-bit space.
As listed in tables 9.2 and 9.3, this LSI can be connected directly to eight or six areas of memory,
and it outputs chip select signals (CS0, CS2 to CS4, CS5A, CS5B, CS6A, and CS6B) for each of
them. CS0 is asserted during area 0 access; CS5A is asserted during area 5A access when address
map 1 is selected; and CS5B is asserted when address map 2 is selected.
The BSC decodes A28 to A25 of the physical address and generates chip select signals that
correspond to areas 0, 2 to 4, 5A, 5B, 6A, and 6B. Address bits A31 to A29 are ignored. This
means that the range of area 0 addresses, for example, is H'00000000 to H'03FFFFFF, and its
corresponding shadow space is the address space in P1 to P3 areas obtained by adding to it
H'20000000 × n (n = 1 to 6).
The address range for area 7 is H'1C000000 to H'1FFFFFFF. The address space H'1C000000 +
H'20000000 × n to H'1FFFFFFF + H'20000000 × n (n = 0 to 6) corresponding to the area 7
shadow space is reserved, so do not use it.
Area P4 (H'E0000000 to H'EFFFFFFF) is an I/O area and is assigned for internal register
addresses. Therefore, area P4 does not become shadow space.
H'00000000
Area 0 (CS0)
Area 1 (Internal I/O)
H'20000000 Area 2 (CS2)
P0 Area 3 (CS3)
H'40000000 Area 4 (CS4)
Area 5A (CS5A)
H'60000000 Area 5B (CS5B)
Area 6A (CS6A)
H'80000000 Area 6B (CS6B)
P1 Area 7 (Reserved area)
H'A0000000
P2 Physical address space
H'C0000000
P3
H'E0000000
P4
Address space
The external address space has a capacity of 384 Mbytes and is used by dividing eight partial
spaces (address map 1) or six partial spaces (address map 2). The kind of memory to be connected
and the data bus width are specified in each partial space. The address map for the external address
space is listed below.
The memory bus width in this LSI can be set for each area. In area 0, external pins can be used to
select byte (8 bits), word (16 bits), or longword (32 bits) on power-on reset. The memory bus
width of the other area is set by the register. The correspondence between the memory type,
external pins (MD3, MD4), and bus width is listed in the table below.
Table 9.4 Correspondence between External Pins (MD3 and MD4), Memory Type of CS0,
and Memory Bus Width
This LSI supports the big endian and little endian methods of data alignment. The data alignment
is specified using the external pin (MD5) at power-on reset as shown in table 9.5.
MD5 Endian
0 Big endian
1 Little endian
Do not access spaces other than CS0 until the termination of the setting the memory interface.
CMNCR is a 32-bit register that controls the common items for each area. Do not access external
memory other than area 0 until the CMNCR initialization is complete.
Initial
Bit Bit Name Value R/W Description
31 to 15 All 0 R Reserved
These bits are always read as 0. The write value should
always be 0.
14 BSD 0 R/W Bus Access Start Timing Specification After Bus
Acknowledge
Specifies the bus access start timing after the external bus
acknowledge signal is received.
0: Starts the external access at the same timing as the
address drive start after the bus acknowledge signal is
received.
1: Starts the external access one cycle following the address
drive start after the bus acknowledge signal is received.
13 0 R Reserved
This bit is always read as 0. The write value should always be
0.
12 MAP 0 R/W Space Specification
Selects the address map for the external address space. The
address maps to be selected are shown in tables 9.2 and 9.3.
0: Selects address map 1
1: Selects address map 2
11 BLOCK 0 R/W Bus Lock Bit
Specifies whether or not the BREQ signal is received.
0: Receives BREQ
1: Does not receive BREQ
Initial
Bit Bit Name Value R/W Description
10 DPRTY1 0 R/W DMA Burst Transfer Priority
9 DPRTY0 0 R/W Specify the priority for a refresh request/bus mastership request
during DMA burst transfer.
00: Accepts a refresh request and bus mastership request
during DMA burst transfer
01: Accepts a refresh request but does not accept a bus
mastership request during DMA burst transfer
10: Accepts neither a refresh request nor a bus mastership
request during DMA burst transfer
11: Reserved (Setting prohibited)
8 DMAIW2 0 R/W Wait States between Access Cycles when DMA Single Address
7 DMAIW1 0 R/W is Transferred
6 DMAIW0 0 R/W Specify the number of idle cycles to be inserted after an access
to an external device with DACK when DMA single address
transfer is performed. The method of inserting idle cycles
depends on the contents of DMAIWA.
000: No idle cycle inserted
001: 1 idle cycle inserted
010: 2 idle cycles inserted
011: 4 idle cycled inserted
100: 6 idle cycled inserted
101: 8 idle cycle inserted
110: 10 idle cycles inserted
111: 12 idle cycled inserted
5 DMAIWA 0 R/W Method of Inserting Wait States between Access Cycles when
DMA Single Address is Transferred
Specifies the method of inserting the idle cycles specified by the
DMAIW1 and DMAIW0 bits. Clearing this bit will make this LSI
insert the idle cycles when another device, which includes this
LSI, drives the data bus after an external device with DACK
drove it. Setting this bit will make this LSI insert the idle cycles
even when the continuous accesses to an external device with
DACK are performed.
0: Inserts the idle cycles when another device drives the data
bus after an external device with DACK drove it.
1: Inserts the idle cycles every time when an external device
with DACK is accessed.
Initial
Bit Bit Name Value R/W Description
4 1 R Reserved
This bit is always read as 1. The write value should always
be 1.
3 ENDIAN 0/1* R Endian Flag
Samples the external pin for specifying endian on power-on
reset (MD5). All address spaces are defined by this bit. This
is a read-only bit.
0: The external pin for specifying endian (MD5) was low level
on power-on reset. This LSI is being operated as big
endian.
1: The external pin for specifying endian (MD5) was high
level on power-on reset. This LSI is being operated as
little endian.
2 0 R Reserved
This bit is always read as 0. The write value should always
be 0.
1 HIZMEM 0 R/W High-Z Memory Control
Specifies the pin state in standby mode for A25 to A0, BS,
CSn, RD/WR, WEn(BEn)/DQMxx, and RD. When a bus is
released, these pins enter the high-impedance state
regardless of the setting of this bit.
0: High impedance in standby mode
1: Driven in standby mode
0 HIZCNT 0 R/W High-Z Control
Specifies the state in standby mode and bus released for
CKIO, CKE, RAS, and CAS.
0: High impedance in standby mode and bus released for
CKIO, CKE, RAS, and CAS.
1: Driven in standby mode and bus released for CKIO, CKE,
RAS, and CAS.
Note: * The external pin (MD5) for specifying endian is sampled on power-on reset. When big
endian is specified, this bit is read as 0 and when little endian is specified, this bit is
read as 1.
This register specifies the type of memory connected to each space, data-bus width of each space,
and the number of wait cycles between access cycles.
Do not access external memory other than area 0 until the CSnBCR initialization is completed.
Initial
Bit Bit Name Value R/W Description
31 0 R Reserved
This bit is always read as 0. The write value should always
be 0.
30 IWW2 0 R/W Idle Cycles between Write-Read Cycles and Write-Write
29 IWW1 1 R/W Cycles
28 IWW0 1 R/W These bits specify the number of idle cycles to be inserted
after the access to a memory that is connected to the space.
The target access cycles are the write-read cycle and write-
write cycle.
000: No idle cycle
001: 1 idle cycle inserted
010: 2 idle cycles inserted
011: 4 idle cycles inserted
100: 6 idle cycles inserted
101: 8 idle cycles inserted
110: 10 idle cycles inserted
111: 12 idle cycles inserted
Initial
Bit Bit Name Value R/W Description
27 IWRWD2 0 R/W Idle Cycles for Another Space Read-Write
26 IWRWD1 1 R/W Specify the number of idle cycles to be inserted after the
25 IWRWD0 1 R/W access to a memory that is connected to the space. The
target access cycle is a read-write one in which continuous
accesses switch between different spaces.
000: No idle cycle inserted
001: 1 idle cycles inserted
010: 2 idle cycles inserted
011: 4 idle cycles inserted
100: 6 idle cycles inserted
101: 8 idle cycles inserted
110: 10 idle cycles inserted
111: 12 idle cycles inserted
24 IWRWS2 0 R/W Idle Cycles for Read-Write in Same Space
23 IWRWS1 1 R/W Specify the number of idle cycles to be inserted after the
22 IWRWS0 1 R/W access to a memory that is connected to the space. The
target cycle is a read-write cycle of which continuous
accesses are for the same space.
000: No idle cycle inserted
001: 1 idle cycles inserted
010: 2 idle cycles inserted
011: 4 idle cycles inserted
100: 6 idle cycles inserted
101: 8 idle cycles inserted
110: 10 idle cycles inserted
111: 12 idle cycles inserted
Initial
Bit Bit Name Value R/W Description
21 IWRRD2 0 R/W Idle Cycles for Read-Read in Another Space
20 IWRRD1 1 R/W Specify the number of idle cycles to be inserted after the
19 IWRRD0 1 R/W access to a memory that is connected to the space. The
target cycle is a read-read cycle of which continuous
accesses switch between different spaces.
000: No idle cycle inserted
001: 1 idle cycles inserted
010: 2 idle cycles inserted
011: 4 idle cycles inserted
100: 6 idle cycles inserted
101: 8 idle cycles inserted
110: 10 idle cycles inserted
111: 12 idle cycles inserted
18 IWRRS2 0 R/W Idle Cycles for Read-Read in Same Space
17 IWRRS1 1 R/W Specify the number of idle cycles to be inserted after the
16 IWRRS0 1 R/W access to a memory that is connected to the space. The
target cycle is a read-read cycle of which continuous
accesses are for the same space.
000: No idle cycle inserted
001: 1 idle cycles inserted
010: 2 idle cycles inserted
011: 4 idle cycles inserted
100: 6 idle cycles inserted
101: 8 idle cycles inserted
110: 10 idle cycles inserted
111: 12 idle cycles inserted
Initial
Bit Bit Name Value R/W Description
15 TYPE3 0 R/W Memory Type
14 TYPE2 0 R/W Specify the type of memory connected to a space.
13 TYPE1 0 R/W 0000: Normal space
12 TYPE0 0 R/W 0001: Burst ROM (clock asynchronous)
0010: Reserved (setting prohibited)
0011: Byte-selection SRAM
0100: SDRAM
0101: PCMCIA
0110: Reserved (setting prohibited)
0111: Burst ROM (clock synchronous)
1000: Reserved (setting prohibited)
1001: Reserved (setting prohibited)
1010: Reserved (setting prohibited)
1011: Reserved (setting prohibited)
1100: Reserved (setting prohibited)
1101: Reserved (setting prohibited)
1110: Reserved (setting prohibited)
1111: Reserved (setting prohibited)
Note: Memory type for area 0 immediately after reset is
normal space. The normal space, burst ROM (clock
asynchronous), or burst ROM (clock synchronous) can
be selected by these bits.
For details on memory type in each area, see tables 9.2 and
9.3.
11 0 R Reserved
This bit is always read as 0. The write value should always
be 0.
Initial
Bit Bit Name Value R/W Description
10 BSZ1 1* R/W Data Bus Width
9 BSZ0 1* R/W Specify the data bus width of spaces.
00: Reserved (setting prohibited)
01: 8-bit size
10: 16-bit size
11: 32-bit size
Notes: 1. The data bus width for area 0 is specified by the
external pin. The BSZ1 and BSZ0 bit settings in
CS0BCR are ignored.
2. If area 5 or area 6 is specified as PCMCIA space,
the bus width can be specified as either 8 bits or
16 bits.
3. If area 2 or area 3 is specified as SDRAM space,
the bus width can be specified as either 16 bits or
32 bits.
8 to 0 All 0 R Reserved
These bits are always read as 0. The write value should
always be 0.
Note: * CS0BCR samples the external pins (MD3 and MD4) that specify the bus width at
power-on reset.
This register specifies various wait cycles for memory accesses. The bit configuration of this
register varies as shown below according to the memory type (TYPE3, TYPE2, TYPE1, or
TYPE0) specified by the CSn space bus control register (CSnBCR). Specify CSnWCR before
accessing the target area. Specify CSnBCR first, then specify CSnWCR.
• CS0WCR, CS6BWCR
Initial
Bit Bit Name Value R/W Description
31 to 21 All 0 R Reserved
These bits are always read as 0. The write value should
always be 0.
20 BAS 0 R/W Byte Access Selection for Byte-Selection SRAM
Specifies the WEn (BEn) and RD/WR signal timing when
the byte-selection SRAM interface is used.
0: Asserts the WEn (BEn) signal at the read/write timing
and asserts the RD/WR signal during the write access
cycle.
1: Asserts the WEn (BEn) signal during the read/write
access cycle and asserts the RD/WR signal at the write
timing.
19 to 13 All 0 R Reserved
These bits are always read as 0. The write value should
always be 0.
12 SW1 0 R/W Number of Delay Cycles from Address, CSn Assertion to
11 SW0 0 R/W RD, WEn (BEn) Assertion
Specify the number of delay cycles from address and CSn
assertion to RD and WEn (BEn) assertion.
00: 0.5 cycle
01: 1.5 cycles
10: 2.5 cycles
11: 3.5 cycles
Initial
Bit Bit Name Value R/W Description
10 WR3 1 R/W Number of Access Wait Cycles
9 WR2 0 R/W Specify the number of wait cycles that are necessary for
8 WR1 1 R/W read or write access.
Initial
Bit Bit Name Value R/W Description
1 HW1 0 R/W Number of Delay Cycles from RD, WEn (BEn) negation to
0 HW0 0 R/W Address, CSn negation
Specify the number of delay cycles from RD and WEn
(BEn) negation to address and CSn negation.
00: 0.5 cycle
01: 1.5 cycles
10: 2.5 cycles
11: 3.5 cycles
• CS2WCR, CS3WCR
Initial
Bit Bit Name Value R/W Description
31 to 21 All 0 R Reserved
These bits are always read as 0. The write value should
always be 0.
20 BAS 0 R/W Byte Access Selection for Byte-Selection SRAM
Specifies the WEn (BEn) and RD/WR signal timing when
the byte-selection SRAM interface is used.
0: Asserts the WEn (BEn) signal at the read/write timing
and asserts the RD/WR signal during the write access
cycle.
1: Asserts the WEn (BEn) signal during the read/write
access cycle and asserts the RD/WR signal at the write
timing.
19 to 11 All 0 R Reserved
These bits are always read as 0. The write value should
always be 0.
Initial
Bit Bit Name Value R/W Description
10 WR3 1 R/W Number of Access Wait Cycles
9 WR2 0 R/W Specify the number of wait cycles that are necessary for
8 WR1 1 R/W read or write access.
• CS4WCR
Initial
Bit Bit Name Value R/W Description
31 to 21 All 0 R Reserved
These bits are always read as 0. The write value should
always be 0.
20 BAS 0 R/W Byte Access Selection for Byte-Selection SRAM
Specifies the WEn (BEn) and RD/WR signal timing when
the byte-selection SRAM interface is used.
0: Asserts the WEn (BEn) signal at the read/write timing
and asserts the RD/WR signal during the write access
cycle.
1: Asserts the WEn (BEn) signal during the read/write
access cycle and asserts the RD/WR signal at the write
timing.
19 0 R Reserved
This bit is always read as 0. The write value should always
be 0.
18 WW2 0 R/W Number of Write Access Wait Cycles
17 WW1 0 R/W Specify the number of cycles that are necessary for write
16 WW0 0 R/W access.
000: The same cycles as WR3 to WR0 setting (read or
write access wait)
001: 0 cycles
010: 1 cycle
011: 2 cycles
100: 3 cycles
101: 4 cycles
110: 5 cycles
111: 6 cycles
15 to 13 All 0 R Reserved
These bits are always read as 0. The write value should
always be 0.
Initial
Bit Bit Name Value R/W Description
12 SW1 0 R/W Number of Delay Cycles from Address, CSn Assertion to
11 SW0 0 R/W RD, WEn (BEn) Assertion-
Specify the number of delay cycles from address and CSn
assertion to RD and WEn (BEn) assertion.
00: 0.5 cycle
01: 1.5 cycles
10: 2.5 cycles
11: 3.5 cycles
10 WR3 1 R/W Number of Access Wait Cycles
9 WR2 0 R/W Specify the number of wait cycles that are necessary for
8 WR1 1 R/W read or write access.
Initial
Bit Bit Name Value R/W Description
5 to 2 All 0 R Reserved
These bits are always read as 0. The write value should
always be 0.
1 HW1 0 R/W Number of Delay Cycles from RD, WEn (BEn) negation to
0 HW0 0 R/W Address, CSn negation
Specify the number of delay cycles from RD and WEn
(BEn) negation to address and CSn negation.
00: 0.5 cycle
01: 1.5 cycles
10: 2.5 cycles
11: 3.5 cycles
• CS5AWCR
Initial
Bit Bit Name Value R/W Description
31 to 19 All 0 R Reserved
These bits are always read as 0. The write value should
always be 0.
18 WW2 0 R/W Number of Write Access Wait Cycles
17 WW1 0 R/W Specify the number of cycles that are necessary for write
16 WW0 0 R/W access.
000: The same cycles as WR3 to WR0 setting (read or
write access wait)
001: 0 cycles
010: 1 cycle
011: 2 cycles
100: 3 cycles
101: 4 cycles
110: 5 cycles
111: 6 cycles
15 to 13 All 0 R Reserved
These bits are always read as 0. The write value should
always be 0.
Initial
Bit Bit Name Value R/W Description
12 SW1 0 R/W Number of Delay Cycles from Address, CSn Assertion to
11 SW0 0 R/W RD, WEn (BEn) Assertion
Specify the number of delay cycles from address and CSn
assertion to RD and WEn (BEn) assertion.
00: 0.5 cycle
01: 1.5 cycles
10: 2.5 cycles
11: 3.5 cycles
10 WR3 1 R/W Number of Access Wait Cycles
9 WR2 0 R/W Specify the number of wait cycles that are necessary for
8 WR1 1 R/W read or write access.
Initial
Bit Bit Name Value R/W Description
5 to 2 All 0 R Reserved
These bits are always read as 0. The write value should
always be 0.
1 HW1 0 R/W Number of Delay Cycles from RD, WEn (BEn) negation to
0 HW0 0 R/W Address, CSn negation
Specify the number of delay cycles from RD and WEn
(BEn) negation to address and CSn negation.
00: 0.5 cycle
01: 1.5 cycles
10: 2.5 cycles
11: 3.5 cycles
• CS5BWCR
Initial
Bit Bit Name Value R/W Description
31 to 21 All 0 R Reserved
These bits are always read as 0. The write value should
always be 0.
20 BAS 0 R/W Byte Access Selection for Byte-Selection SRAM
Specifies the WEn (BEn) and RD/WR signal timing when
the byte-selection SRAM interface is used.
0: Asserts the WEn (BEn) signal at the read/write timing
and asserts the RD/WR signal during the write access
cycle.
1: Asserts the WEn (BEn) signal during the read/write
access cycle and asserts the RD/WR signal at the write
timing.
19 0 R Reserved
This bit is always read as 0. The write value should always
be 0.
Initial
Bit Bit Name Value R/W Description
18 WW2 0 R/W Number of Write Access Wait Cycles
17 WW1 0 R/W Specify the number of cycles that are necessary for write
16 WW0 0 R/W access.
000: The same cycles as WR3 to WR0 setting (read or
write access wait)
001: 0 cycles
010: 1 cycle
011: 2 cycles
100: 3 cycles
101: 4 cycles
110: 5 cycles
111: 6 cycles
15 to 13 All 0 R Reserved
These bits are always read as 0. The write value should
always be 0.
12 SW1 0 R/W Number of Delay Cycles from Address, CSn Assertion to
11 SW0 0 R/W RD, WEn (BEn) Assertion
Specify the number of delay cycles from address and CSn
assertion to RD and WEn (BEn) assertion.
00: 0.5 cycle
01: 1.5 cycles
10: 2.5 cycles
11: 3.5 cycles
Initial
Bit Bit Name Value R/W Description
10 WR3 1 R/W Number of Access Wait Cycles
9 WR2 0 R/W Specify the number of wait cycles that are necessary for read
8 WR1 1 R/W or write access.
• CS6AWCR
Initial
Bit Bit Name Value R/W Description
31 to 13 All 0 R Reserved
These bits are always read as 0. The write value should
always be 0.
12 SW1 0 R/W Number of Delay Cycles from Address, CSn Assertion to
11 SW0 0 R/W RD, WEn (BEn) Assertion
Specify the number of delay cycles from address and CSn
assertion to RD and WEn (BEn) assertion.
00: 0.5 cycle
01: 1.5 cycles
10: 2.5 cycles
11: 3.5 cycles
10 WR3 1 R/W Number of Access Wait Cycles
9 WR2 0 R/W Specify the number of wait cycles that are necessary for
8 WR1 1 R/W read or write access.
Initial
Bit Bit Name Value R/W Description
5 to 2 All 0 R Reserved
These bits are always read as 0. The write value should
always be 0.
1 HW1 0 R/W Number of Delay Cycles from RD, WEn (BEn) negation to
0 HW0 0 R/W Address, CSn negation
Specify the number of delay cycles from RD and WEn
(BEn) negation to address and CSn negation.
00: 0.5 cycle
01: 1.5 cycles
10: 2.5 cycles
11: 3.5 cycles
• CS0WCR
Initial
Bit Bit Name Value R/W Description
31 to 21 All 0 R Reserved
These bits are always read as 0. The write value should
always be 0.
20 BEN 0 R/W Burst Enable Specification
Enables or disables 8-burst access for a 16-bit bus width or
16-burst access for an 8-bit bus width during 16-byte access.
If this bit is set to 1, 2-burst access is performed four times
when the bus width is 16 bits and 4-burst access is
performed four times when the bus width is 8 bits.
To use a device that does not support 8-burst access or 16-
burst access, set this bit to 1.
0: Enables 8-burst access for a 16-bit bus width and 16-burst
access for an 8-bit bus width.
1: Disables 8-burst access for a 16-bit bus width and 16-burst
access for an 8-bit bus width.
19, 18 All 0 R Reserved
These bits are always read as 0. The write value should
always be 0.
Initial
Bit Bit Name Value R/W Description
17 BW1 0 R/W Number of Burst Wait Cycles
16 BW0 0 R/W Specify the number of wait cycles to be inserted between
the second or later access cycles in burst access.
00: 0 cycles
01: 1 cycle
10: 2 cycles
11: 3 cycles
15 to 11 All 0 R Reserved
These bits are always read as 0. The write value should
always be 0.
10 W3 1 R/W Number of Access Wait Cycles
9 W2 0 R/W Specify the number of wait cycles to be inserted in the first
8 W1 1 R/W access cycle.
Initial
Bit Bit Name Value R/W Description
6 WM 0 R/W External Wait Mask Specification
Specify whether or not the external wait input is valid. The
specification by this bit is valid even when the number of
access wait cycles is 0.
0: External wait is valid
1: External wait is ignored
5 to 0 All 0 R Reserved
These bits are always read as 0. The write value should
always be 0.
• CS4WCR
Initial
Bit Bit Name Value R/W Description
31 to 21 All 0 R Reserved
These bits are always read as 0. The write value should
always be 0.
20 BEN 0 R/W Burst Enable Specification
Enables or disables 8-burst access for a 16-bit bus width or
16- burst access for an 8-bit bus width during 16-byte access.
If this bit is set to 1, 2-burst access is performed four times
when the bus width is 16 bits and 4-burst access is
performed four times when the bus width is 8 bits.
To use a device that does not support 8-burst access or 16-
burst access, set this bit to 1.
0: Enables 8-burst access for a 16-bit bus width and 16-burst
access for an 8-bit bus width.
1: Disables 8-burst access for a 16-bit bus width and 16-burst
access for an 8-bit bus width.
19, 18 All 0 R Reserved
These bits are always read as 0. The write value should
always be 0.
Initial
Bit Bit Name Value R/W Description
17 BW1 0 R/W Number of Burst Wait Cycles
16 BW0 0 R/W Specify the number of wait cycles to be inserted between the
second or later access cycles in burst access.
00: 0 cycles
01: 1 cycle
10: 2 cycles
11: 3 cycles
15 to 13 All 0 R Reserved
These bits are always read as 0. The write value should
always be 0.
12 SW1 0 R/W Number of Delay Cycles from Address, CSn Assertion to RD,
11 SW0 0 R/W WEn (BEn) Assertion
Specify the number of delay cycles from address and CSn
assertion to RD and WEn (BEn) assertion. These bits can be
specified only in area 4.
00: 0.5 cycle
01: 1.5 cycles
10: 2.5 cycles
11: 3.5 cycles
Initial
Bit Bit Name Value R/W Description
10 W3 1 R/W Number of Access Wait Cycles
9 W2 0 R/W Specify the number of wait cycles to be inserted in the first
8 W1 1 R/W access cycle.
(3) SDRAM
• CS2WCR
Initial
Bit Bit Name Value R/W Description
31 to 9 All 0 R Reserved
These bits are always read as 0. The write value should
always be 0.
8 A2CL1 1 R/W CAS Latency for Area 2
7 A2CL0 0 R/W Specify the CAS latency for area 2.
00: 1 cycle
01: 2 cycles
10: 3 cycles
11: 4 cycles
6 to 0 All 0 R Reserved
These bits are always read as 0. The write value should
always be 0.
• CS3WCR
Initial
Bit Bit Name Value R/W Description
31 to 15 All 0 R Reserved
These bits are always read as 0. The write value should
always be 0.
14 TRP1 0 R/W Number of Cycles from Auto-Precharge/PRE Command to
13 TRP0 0 R/W ACTV Command
Specify the number of minimum cycles from the start of auto-
precharge or issuing of PRE command to the issuing of
ACTV command for the same bank. The setting for areas 2
and 3 is common.
00: 1 cycle
01: 2 cycles
10: 3 cycles
11: 4 cycles
12 0 R Reserved
This bit is always read as 0. The write value should always be
0.
Initial
Bit Bit Name Value R/W Description
11 TRCD1 0 R/W Number of Cycles from ACTV Command to
10 TRCD0 1 R/W READ(A)/WRIT(A) Command
Specify the number of minimum cycles from issuing ACTV
command to issuing READ(A)/WRIT(A) command. The
setting for areas 2 and 3 is common.
00: 1 cycle
01: 2 cycles
10: 3 cycles
11: 4 cycles
9 0 R Reserved
This bit is always read as 0. The write value should always
be 0.
8 A3CL1 1 R/W CAS Latency for Area 3.
7 A3CL0 0 R/W Specify the CAS latency for area 3.
00: 1 cycle
01: 2 cycles
10: 3 cycles
11: 4 cycles
When connecting the SDRAM to area 2 and area 3, set
the CAS latency to the bits 8 and 7 in the CS2WCR
register and the SDMR2 and SDMR3 registers for SDRAM
mode setting. (See table 9.19.)
6, 5 All 0 R Reserved
These bits are always read as 0. The write value should
always be 0.
4 TRWL1 0 R/W Number of Cycles from WRITA/WRIT Command to Auto-
3 TRWL0 0 R/W Precharge/PRE Command
Specifies the number of cycles from issuing WRITA/WRIT
command to the start of auto-precharge or to issuing PRE
command. The setting for areas 2 and 3 is common.
00: 0 cycles
01: 1 cycle
10: 2 cycles
11: 3 cycles
Initial
Bit Bit Name Value R/W Description
2 0 R Reserved
This bit is always read as 0. The write value should always
be 0.
1 TRC1 0 R/W Number of Cycles from REF Command/Self-Refresh
0 TRC0 0 R/W Release to ACTV Command
Specify the number of minimum cycles from issuing the
REF command or releasing self-refresh to issuing the
ACTV command. The setting for areas 2 and 3 is
common.
00: 3 cycles
01: 4 cycles
10: 6 cycles
11: 9 cycles
Note: * If both areas 2 and 3 are specified as SDRAM, TRP1/0, TRCD0/1, TRWL1/0, and
TRC1/0 bit settings are common.
If only one area is connected to the SDRAM, specify area 3. In this case, specify area 2
as normal space or byte-selection SRAM.
(4) PCMCIA
• CS5BWCR, CS6BWCR
Initial
Bit Bit Name Value R/W Description
31 to 22 All 0 R Reserved
These bits are always read as 0. The write value should
always be 0.
21 SA1 0 R/W Space Attribute Specification
20 SA0 0 R/W Specify memory card interface or I/O card interface when the
PCMCIA interface is selected.
SA1
0: Specifies memory card interface when A25 = 1
1: Specifies I/O card interface when A25 = 1
SA0
0: Specifies memory card interface when A25 = 0
1: Specifies I/O card interface when A25 = 0
Note: When using the PC card controller, specifies the
following settings.
When the bit 4 (P0USE) in the PCC0GCR register of
PCC is 1 and the bit 5 (P0PCCT) of the PCC0GCR
register is 0, both SA1 and SA0 should be 0. When
the bit 4 (P0USE) and the bit 5 (P0PCCT) in the
PCC0GCR register of PCC are 1, both SA1 and SA0
should be 1.
19 to 15 All 0 R Reserved
These bits are always read as 0. The write value should
always be 0.
Initial
Bit Bit Name Value R/W Description
14 TED3 0 R/W Delay from Address to RD or WE Assert
13 TED2 0 R/W Specify the delay time from address output to RD or WE
12 TED1 0 R/W assert in PCMCIA interface.
Initial
Bit Bit Name Value R/W Description
10 PCW3 1 R/W Number of Access Wait Cycles
9 PCW2 0 R/W Specify the number of wait cycles to be inserted.
8 PCW1 1 R/W 0000: 3 cycles
7 PCW0 0 R/W 0001: 6 cycles
0010: 9 cycles
0011: 12 cycles
0100: 15 cycles
0101: 18 cycles
0110: 22 cycles
0111: 26 cycles
1000: 30 cycles
1001: 33 cycles
1010: 36 cycles
1011: 38 cycles
1100: 52 cycles
1101: 60 cycles
1110: 64 cycles
1111: 80 cycles
6 WM 0 R/W External Wait Mask Specification
Specify whether or not the external wait input is valid. The
specification by this bit is valid even when the number of
access wait cycle is 0.
0: External wait is valid
1: External wait is ignored
5, 4 All 0 R Reserved
These bits are always read as 0. The write value should
always be 0.
Initial
Bit Bit Name Value R/W Description
3 TEH3 0 R/W Delay from RD or WE Negate to Address
2 TEH2 0 R/W Specify the address hold time from RD or WE negate in the
1 TEH1 0 R/W PCMCIA interface.
• CS0WCR
Initial
Bit Bit Name Value R/W Description
31 to 18 All 0 R Reserved
These bits are always read as 0. The write value should
always be 0.
17 BW1 0 R/W Number of Burst Wait Cycles
16 BW0 0 R/W Specify the number of wait cycles to be inserted between the
second or later access cycles in burst access.
00: 0 cycles
01: 1 cycle
10: 2 cycles
11: 3 cycles
15 to 11 All 0 R Reserved
These bits are always read as 0. The write value should
always be 0.
10 W3 1 R/W Number of Access Wait Cycles
9 W2 0 R/W Specify the number of wait cycles to be inserted in the first
8 W1 1 R/W access cycle.
Initial
Bit Bit Name Value R/W Description
6 WM 0 R/W External Wait Mask Specification
Specify whether or not the external wait input is valid. The
specification by this bit is valid even when the number of
access wait cycles is 0.
0: External wait is valid
1: External wait is ignored
5 to 0 All 0 R Reserved
These bits are always read as 0. The write value should
always be 0.
SDCR specifies the method to refresh and access SDRAM, and the types of SDRAMs to be
connected.
Initial
Bit Bit Name Value R/W Description
31 to 21 All 0 R Reserved
These bits are always read as 0. The write value should
always be 0.
20 A2ROW1 0 R/W Number of Bits of Row Address for Area 2
19 A2ROW0 0 R/W Specify the number of bits of row address for area 2.
00: 11 bits
01: 12 bits
10: 13 bits
11: Reserved (setting prohibited)
18 0 R Reserved
This bit is always read as 0. The write value should always
be 0.
17 A2COL1 0 R/W Number of Bits of Column Address for Area 2
16 A2COL0 0 R/W Specify the number of bits of column address for area 2.
00: 8 bits
01: 9 bits
10: 10 bits
11: Reserved (setting prohibited)
15, 14 All 0 R Reserved
These bits are always read as 0. The write value should
always be 0.
13 DEEP 0 R/W Deep Power-Down Mode
This bit is valid for low-power SDRAM. If the RMODE bit is
set to 1 while this bit is set to 1, the deep power-down entry
command is issued and the low-power SDRAM enters the
deep power-down mode.
0: Self-refresh mode
1: Deep power-down mode
Initial
Bit Bit Name Value R/W Description
12 0 R Reserved
This bit is always read as 0. The write value should always
be 0.
11 RFSH 0 R/W Refresh Control
Specifies whether or not the refresh operation of the SDRAM
is performed.
0: No refresh
1: Refresh
10 RMODE 0 R/W Refresh Control
Specifies whether to perform auto-refresh or self-refresh
when the RFSH bit is 1. When the RFSH bit is 1 and this bit
is 1, self-refresh starts immediately. When the RFSH bit is 1
and this bit is 0, auto-refresh starts according to the contents
that are set in RTCSR, RTCNT, and RTCOR.
0: Auto-refresh is performed
1: Self-refresh is performed
9 PDOWN 0 R Power-Down Mode
Specifies whether the SDRAM is entered in power-down
mode or not after the access to SDRAM is completed. If this
bit is set to 1, the CKE pin is pulled to low to place the
SDRAM to power-down mode.
0: Does not place the SDRAM in power-down mode after
access completion.
1: Places the SDRAM in power-down mode after access
completion.
Initial
Bit Bit Name Value R/W Description
8 BACTV 0 R/W Bank Active Mode
Specifies to access whether in auto-precharge mode (using
READA and WRITA commands) or in bank active mode
(using READ and WRIT commands).
0: Auto-precharge mode (using READA and WRITA
commands)
1: Bank active mode (using READ and WRIT commands)
Note: Bank active mode can be used only in area 3. In this
case, the bus width can be selected as 16 or 32 bits.
When both areas 2 and 3 are set to SDRAM, specify
auto-precharge mode.
7 to 5 All 0 R Reserved
These bits are always read as 0. The write value should
always be 0.
4 A3ROW1 0 R/W Number of Bits of Row Address for Area 3
3 A3ROW0 0 R/W Specify the number of bits of the row address for area 3.
00: 11 bits
01: 12 bits
10: 13 bits
11: Reserved (setting prohibited)
2 0 R Reserved
This bit is always read as 0. The write value should always
be 0.
1 A3COL1 0 R/W Number of Bits of Column Address for Area 3
0 A3COL0 0 R/W Specify the number of bits of the column address for area 3.
00: 8 bits
01: 9 bits
10: 10 bits
11: Reserved (setting prohibited)
When RTCSR is written, the upper 16 bits of the write data must be H'A55A to cancel write
protection.
Initial
Bit Bit Name Value R/W Description
31 to 8 All 0 R Reserved
These bits are always read as 0. The write value should
always be 0.
7 CMF 0 R/W Compare Match Flag
Indicates that a compare match occurs between the refresh
timer counter (RTCNT) and refresh time constant register
(RTCOR). This bit is set or cleared in the following
conditions.
0: Clearing condition: When 0 is written in CMF after reading
out RTCSR during CMF = 1.
1: Setting condition: When the condition RTCNT = RTCOR is
satisfied.
6 CMIE 0 R/W Compare Match Interrupt Enable
Enables or disables a CMF interrupt request when the CMF
bit of RTCSR is set to 1.
0: Disables the CMF interrupt request
1: Enables the CMF interrupt request
5 CKS2 0 R/W Clock Select
4 CKS1 0 R/W Select the clock input to count-up the refresh timer counter
3 CKS0 0 R/W (RTCNT).
000: Stop the counting-up
001: Bφ/4
010: Bφ/16
011: Bφ/64
100: Bφ/256
101: Bφ/1024
110: Bφ/2048
111: Bφ/4096
Initial
Bit Bit Name Value R/W Description
2 RRC2 0 R/W Refresh Count
1 RRC1 0 R/W Specify the number of continuous refresh cycles, when the
0 RRC0 0 R/W refresh request occurs after the coincidence of the values of
the refresh timer counter (RTCNT) and the refresh time
constant register (RTCOR). These bits can make the period
of occurrence of refresh long.
000: Once
001: Twice
010: 4 times
011: 6 times
100: 8 times
101: Reserved (setting prohibited)
110: Reserved (setting prohibited)
111: Reserved (setting prohibited)
RTCNT is an 8-bit counter that increments using the clock selected by bits CKS2 to CKS0 in
RTCSR. When RTCNT matches RTCOR, RTCNT is cleared to 0. The value in RTCNT returns to
0 after counting up to 255. When the RTCNT is written, the upper 16 bits of the write data must
be H'A55A to cancel write protection.
Initial
Bit Bit Name Value R/W Description
31 to 8 All 0 R Reserved
These bits are always read as 0. The write value should
always be 0.
7 to 0 All 0 R/W 8-bit Counter
RTCOR is an 8-bit register. When RTCOR matches RTCNT, the CMF bit in RTCSR is set to 1
and RTCNT is cleared to 0.
When the RFSH bit in SDCR is 1, a memory refresh request is issued by this matching signal.
This request is maintained until the refresh operation is performed. If the request is not processed
when the next matching occurs, the previous request is ignored.
If the CMIE bit of the RTCSR is set to 1, an interrupt is requested by this matching signal. This
request is maintained until the CMF bit in RTCSR is cleared to 0. Clearing the CMF bit in RTCSR
affects only interrupts and does not affect refresh requests. This makes it possible to count the
number of refresh requests during refresh by interrupts, and to specify the refresh and interval
timer interrupts simultaneously. When the RTCOR is written, the upper 16 bits of the write data
must be H'A55A to cancel write protection.
Initial
Bit Bit Name Value R/W Description
31 to 8 All 0 R Reserved
These bits are always read as 0. The write value should
always be 0.
7 to 0 All 0 R/W 8-bit Counter
For the settings of SDRAM mode registers (SDMR2 and SDMR3), see table 9.19.
9.5 Operation
This LSI supports big endian, in which the 0 address is the most significant byte (MSByte) in the
byte data and little endian, in which the 0 address is the least significant byte (LSByte) in the byte
data. Endian is specified on power-on reset by the external pin (MD5). When MD5 pin is low
level on power-on reset, the endian will become big endian and when MD5 pin is high level on
power-on reset, the endian will become little endian.
Three data bus widths (8 bits, 16 bits, and 32 bits) are available for normal memory and byte-
selection SRAM. Two data bus widths (16 bits and 32 bits) are available for SDRAM. Two data
bus widths (8 bits and 16 bits) are available for PCMCIA interface. Data alignment is performed
in accordance with the data bus width of the device and endian. This also means that when
longword data is read from a byte-width device, the read operation must be done four times. In
this LSI, data alignment and conversion of data length is performed automatically between the
respective interfaces.
Tables 9.6 to 9.11 show the relationship between endian, device data width, and access unit.
Table 9.6 32-Bit External Device/Big Endian Access and Data Alignment
Table 9.7 16-Bit External Device/Big Endian Access and Data Alignment
Table 9.8 8-Bit External Device/Big Endian Access and Data Alignment
Table 9.9 32-Bit External Device/Little Endian Access and Data Alignment
Table 9.10 16-Bit External Device/Little Endian Access and Data Alignment
Table 9.11 8-Bit External Device/Little Endian Access and Data Alignment
For access to a normal space, this LSI uses strobe signal output in consideration of the fact that
mainly static RAM will be directly connected. When using SRAM with a byte-selection pin, see
section 9.5.7, Byte-Selection SRAM Interface. Figure 9.3 shows the basic timings of normal space
access. A no-wait normal access is completed in two cycles. The BS signal is asserted for one
cycle to indicate the start of a bus cycle.
T1 T2
CKIO
CSn
RD/WR
Read RD
RD/WR
WEn(BEn)
Write
D
BS
DACKn *
There is no access size specification when reading. The correct access start address is output in the
least significant bit of the address, but since there is no access size specification, 32 bits are always
read in case of a 32-bit device, and 16 bits in case of a 16-bit device. When writing, only the WEn
(BEn) signal for the byte to be written is asserted.
It is necessary to output the data that has been read using RD when a buffer is established in the
data bus. The RD/WR signal is in a read state (high output) when no access has been carried out.
Therefore, care must be taken when controlling the external data buffer, to avoid collision.
Figures 9.4 and 9.5 show the basic timings of normal space accesses. If the WM bit of the
CSnWCR is cleared to 0, a Tnop cycle is inserted to evaluate the external wait (figure 9.4). If the
WM bit of the CSnWCR is set to 1, external waits are ignored and no Tnop cycle is inserted
(figure 9.5).
T1 T2 Tnop T1 T2
CKIO
A25 to A0
CSn
RD/WR
RD
Read
D15 to D0
WEn(BEn)
Write
D15 to D0
BS
DACKn*
WAIT
Figure 9.4 Continuous Access for Normal Space 1, Bus Width = 16 bits, Longword Access,
CSnWCR.WM Bit = 0 (Access Wait = 0, Cycle Wait = 0)
T1 T2 T1 T2
CKIO
A25 to A0
CSn
RD/WR
RD
Read
D15 to D0
WEn(BEn)
Write
D15 to D0
BS
DACKn*
WAIT
Figure 9.5 Continuous Access for Normal Space 2, Bus Width = 16 bits, Longword Access,
CSnWCR.WM Bit = 1 (Access Wait = 0, Cycle Wait = 0)
128k × 8-bit
This LSI SRAM
A18 A16
••••
••••
••••
••••
A2 A0
CSn CS
RD OE
D31 I/O7
••••
••••
••••
••••
D24 I/O0
WE3(BE3) WE
D23
••••
••••
D16 A16
WE2(BE2)
••••
••••
D15 A0
••••
•••• CS
D8 OE
WE1(BE1) I/O7
••••
••••
D7
••••
••••
I/O0
D0 WE
WE0(BE0)
A16
••••
••••
A0
CS
OE
I/O7
••••
••••
I/O0
WE
A16
••••
••••
A0
CS
OE
I/O7
••••
••••
I/O0
WE
128k × 8-bit
This LSI SRAM
A17 A16
••••
••••
••••
••••
A1 A0
CSn CS
RD OE
D15 I/O7
••••
••••
••••
••••
D8 I/O0
WE1(BE1) WE
D7
••••
••••
D0 A16
WE0(BE0)
••••
••••
A0
CS
OE
I/O7
••••
••••
I/O0
WE
128 k x 8 bits
This LSI SRAM
A16 A16
...
...
A0 A0
CSn CS
RD OE
D7 I/O7
...
...
D0 I/O0
WE0(BE0) WE
Wait cycle insertion on a normal space access can be controlled by the settings of bits WR3 to
WR0 in CSnWCR. It is possible for areas 4, 5A, and 5B to insert wait cycles independently in
read access and in write access. The areas other than 4, 5A, and 5B have common access wait for
read cycle and write cycle. The specified number of Tw cycles is inserted as wait cycles in a
normal space access shown in figure 9.9.
T1 Tw T2
CKIO
A25 to A0
CSn
RD/WR
RD
Read
D31 to D0
WEn(BEn)
Write
D31 to D0
BS
DACKn*
Figure 9.9 Wait Timing for Normal Space Access (Software Wait Only)
When the WM bit in CSnWCR is cleared to 0, the external wait input WAIT signal is also
sampled. WAIT pin sampling is shown in figure 9.10. A 2-cycle wait is specified as a software
wait. The WAIT signal is sampled on the falling edge of CKIO at the transition from the T1 or Tw
cycle to the T2 cycle.
CKIO
A25 to A0
CSn
RD/WR
RD
Read
D31 to D0
WEn(BEn)
Write
D31 to D0
WAIT
BS
DACKn*
The number of cycles from CSn assertion to RD and WEn (BEn) assertion can be specified by
setting bits SW1 and SW0 in CSnWCR. The number of cycles from RD and WEn (BEn) negation
to CSn negation can be specified by setting bits HW1 and HW0. Therefore, a flexible interface to
an external device can be obtained. Figure 9.11 shows an example. A Th cycle and a Tf cycle are
added before and after an ordinary cycle, respectively. In these cycles, RD and WEn (BEn) are not
asserted, while other signals are asserted. The data output is prolonged to the Tf cycle, and this
prolongation is useful for devices with slow writing operations.
Th T1 T2 Tf
CKIO
A25 to A0
CSn
RD/WR
RD
Read
D31 to D0
WEn(BEn)
Write
D31 to D0
BS
DACKn*
The SDRAM that can be connected to this LSI is a product that has 11/12/13 bits of row address,
8/9/10 bits of column address, 4 or less banks, and uses the A10 pin for setting precharge mode in
read and write command cycles.
The control signals for direct connection of SDRAM are RAS, CAS, RD/WR, DQMUU,
DQMUL, DQMLU, DQMLL, CKE, CS2, and CS3. All the signals other than CS2 and CS3 are
common to all areas, and signals other than CKE are valid when CS2 or CS3 is asserted. SDRAM
can be connected to up to 2 spaces. The data bus width of the area that is connected to SDRAM
can be set to 32 or 16 bits.
Burst read/single write (burst length 1) and burst read/burst write (burst length 1) are supported as
the SDRAM operating mode.
Commands for SDRAM can be specified by RAS, CAS, RD/WR, and specific address signals.
These commands are shown below.
• NOP
• Auto-refresh (REF)
• Self-refresh (SELF)
• All banks precharge (PALL)
• Specified bank precharge (PRE)
• Bank active (ACTV)
• Read (READ)
• Read with precharge (READA)
• Write (WRIT)
• Write with precharge (WRITA)
• Write mode register (MRS)
The byte to be accessed is specified by DQMUU, DQMUL, DQMLU, and DQMLL. Reading or
writing is performed for a byte whose corresponding DQMxx is low. For details on the
relationship between DQMxx and the byte to be accessed, refer to section 9.5.1, Endian/Access
Size and Data Alignment.
Figures 9.12 and 9.13 show examples of the connection of the SDRAM with the LSI.
64-Mbit SDRAM
This LSI (1M x 16 bits x 4 banks)
A15 A13
...
...
A2 A0
CKE CKE
CKIO CLK
CSn CS
RAS RAS
CAS CAS
RD/WR WE
D31 I/O15
...
...
D16 I/O0
DQMUU DQMU
DQMUL DQML
D15
...
A13
D0
...
DQMLU
A0
DQMLL
CKE
CLK
CS
RAS
CAS
WE
I/O15
...
I/O0
DQMU
DQML
64-Mbit SDRAM
This LSI (1M x 16 bits x 4 banks)
A14 A13
...
...
A1 A0
CKE CKE
CKIO CLK
CSn CS
RAS RAS
CAS CAS
RD/WR WE
D15 I/O15
...
...
D0 I/O0
DQMLU DQMU
DQMLL DQML
When the data bus width is 16 bits (BSZ[1:0] =B'10), A0 of SDRAM specifies a word address.
Therefore, connect this A0 pin of SDRAM to the A1 pin of the LSI; the A1 pin of SDRAM to the
A2 pin of the LSI, and so on. When the data bus width is 32 bits (BSZ[1:0] =B'11), the A0 pin of
SDRAM specifies a longword address. Therefore, connect this A0 pin of SDRAM to the A2 pin of
the LSI; the A1 pin of SDRAM to the A3 pin of the LSI, and so on.
Setting
A2/3 A2/3 A2/3
BSZ ROW COL
[1:0] [1:0] [1:0]
11 (32 bits) 00 (11 bits) 00 (8 bits)
Output Pin of Row Address Column Address Synchronous
This LSI Output Output DRAM Pin Function
A17 A25 A17 Unused
A16 A24 A16
A15 A23 A15
2
A14 A22* A22*2 A12 (BA1) Specifies bank
2 2
A13 A21* A21* A11 (BA0)
A12 A20 L/H*1 A10/AP Specifies
address/precharge
A11 A19 A11 A9 Address
A10 A18 A10 A8
A9 A17 A9 A7
A8 A16 A8 A6
A7 A15 A7 A5
A6 A14 A6 A4
A5 A13 A5 A3
A4 A12 A4 A2
A3 A11 A3 A1
A2 A10 A2 A0
A1 A9 A1 Unused
A0 A8 A0
Example of connected memory
64-Mbit product (512 kwords x 32 bits x 4 banks, column 8 bits product): 1
16-Mbit product (512 kwords x 16 bits x 2 banks, column 8 bits product): 2
Notes: 1. L/H is a bit used in the command specification; it is fixed at low or high according to the
access mode.
2. Bank address specification
Setting
A2/3 A2/3 A2/3
BSZ ROW COL
[1:0] [1:0] [1:0]
11 (32 bits) 01 (12 bits) 00 (8 bits)
Output Pin of Row Address Column Address Synchronous
This LSI Output Output DRAM Pin Function
A17 A24 A17 Unused
A16 A23 A16
2
A15 A23* A23*2 A13 (BA1) Specifies bank
2 2
A14 A22* A22* A12 (BA0)
A13 A21 A13 A11 Address
A12 A20 L/H*1 A10/AP Specifies
address/precharge
A11 A19 A11 A9 Address
A10 A18 A10 A8
A9 A17 A9 A7
A8 A16 A8 A6
A7 A15 A7 A5
A6 A14 A6 A4
A5 A13 A5 A3
A4 A12 A4 A2
A3 A11 A3 A1
A2 A10 A2 A0
A1 A9 A1 Unused
A0 A8 A0
Example of connected memory
128-Mbit product (1 Mword x 32 bits x 4 banks, column 8 bits product): 1
64-Mbit product (1 Mword x 16 bits x 4 banks, column 8 bits product): 2
Notes: 1. L/H is a bit used in the command specification; it is fixed at low or high according to the
access mode.
2. Bank address specification
Setting
A2/3 A2/3 A2/3
BSZ ROW COL
[1:0] [1:0] [1:0]
11 (32 bits) 01 (12 bits) 01 (9 bits)
Output Pin of Row Address Column Address Synchronous
This LSI Output Output DRAM Pin Function
A17 A26 A17 Unused
A16 A25 A16
2
A15 A24* A24*2 A13 (BA1) Specifies bank
2 2
A14 A23* A23* A12 (BA0)
A13 A22 A13 A11 Address
A12 A21 L/H*1 A10/AP Specifies
address/precharge
A11 A20 A11 A9 Address
A10 A19 A10 A8
A9 A18 A9 A7
A8 A17 A8 A6
A7 A16 A7 A5
A6 A15 A6 A4
A5 A14 A5 A3
A4 A13 A4 A2
A3 A12 A3 A1
A2 A11 A2 A0
A1 A10 A1 Unused
A0 A9 A0
Example of connected memory
256-Mbit product (2 Mwords x 32 bits x 4 banks, column 9 bits product): 1
128-Mbit product (2 Mwords x 16 bits x 4 banks, column 9 bits product): 2
Notes: 1. L/H is a bit used in the command specification; it is fixed at low or high according to the
access mode.
2. Bank address specification
Setting
A2/3 A2/3 A2/3
BSZ ROW COL
[1:0] [1:0] [1:0]
11 (32 bits) 01 (12 bits) 10 (10 bits)
Output Pin of Row Address Column Address Synchronous
This LSI Output Output DRAM Pin Function
A17 A27 A17 Unused
A16 A26 A16
2
A15 A25* A25*2 A13 (BA1) Specifies bank
2 2
A14 A24* A24* A12 (BA0)
A13 A23 A13 A11 Address
A12 A22 L/H*1 A10/AP Specifies
address/precharge
A11 A21 A11 A9 Address
A10 A20 A10 A8
A9 A19 A9 A7
A8 A18 A8 A6
A7 A17 A7 A5
A6 A16 A6 A4
A5 A15 A5 A3
A4 A14 A4 A2
A3 A13 A3 A1
A2 A12 A2 A0
A1 A11 A1 Unused
A0 A10 A0
Example of connected memory
512-Mbit product (4 Mwords x 32 bits x 4 banks, column 10 bits product): 1
256-Mbit product (4 Mwords x 16 bits x 4 banks, column 10 bits product): 2
Notes: 1. L/H is a bit used in the command specification; it is fixed at low or high according to the
access mode.
2. Bank address specification
Setting
A2/3 A2/3 A2/3
BSZ ROW COL
[1:0] [1:0] [1:0]
11 (32 bits) 10 (13 bits) 01 (9 bits)
Output Pin of Row Address Column Address Synchronous
This LSI Output Output DRAM Pin Function
A17 A26 A17 Unused
2 2
A16 A25* A25* A14 (BA1) Specifies bank
2 2
A15 A24* A24* A13 (BA0)
A14 A23 A14 A12 Address
A13 A22 A13 A11
A12 A21 L/H*1 A10/AP Specifies
address/precharge
A11 A20 A11 A9 Address
A10 A19 A10 A8
A9 A18 A9 A7
A8 A17 A8 A6
A7 A16 A7 A5
A6 A15 A6 A4
A5 A14 A5 A3
A4 A13 A4 A2
A3 A12 A3 A1
A2 A11 A2 A0
A1 A10 A1 Unused
A0 A9 A0
Example of connected memory
512-Mbit product (4 Mwords x 32 bits x 4 banks, column 9 bits product): 1
256-Mbit product (4 Mwords x 16 bits x 4 banks, column 9 bits product): 2
Notes: 1. L/H is a bit used in the command specification; it is fixed at low or high according to the
access mode.
2. Bank address specification
Setting
A2/3 A2/3 A2/3
BSZ ROW COL
[1:0] [1:0] [1:0]
10 (16 bits) 00 (11 bits) 00 (8 bits)
Output Pin of Row Address Column Address Synchronous
This LSI Output Output DRAM Pin Function
A17 A25 A17 Unused
A16 A24 A16
A15 A23 A15
A14 A22 A14
2
A13 A21* A21*2 A12 (BA1) Specifies bank
A12 A20*2 A20*2 A11 (BA0)
1
A11 A19 L/H* A10/AP Specifies
address/precharge
A10 A18 A10 A9 Address
A9 A17 A9 A8
A8 A16 A8 A7
A7 A15 A7 A6
A6 A14 A6 A5
A5 A13 A5 A4
A4 A12 A4 A3
A3 A11 A3 A2
A2 A10 A2 A1
A1 A9 A1 A0
A0 A8 A0 Unused
Example of connected memory
16-Mbit product (512 kwords x 16 bits x 2 banks, column 8 bits product): 1
Notes: 1. L/H is a bit used in the command specification; it is fixed at low or high according to the
access mode.
2. Bank address specification
Setting
A2/3 A2/3 A2/3
BSZ ROW COL
[1:0] [1:0] [1:0]
10 (16 bits) 01 (12 bits) 00 (8 bits)
Output Pin of Row Address Column Address Synchronous
This LSI Output Output DRAM Pin Function
A17 A25 A17 Unused
A16 A24 A16
A15 A23 A15
2
A14 A22* A22*2 A13 (BA1) Specifies bank
2 2
A13 A21* A21* A12 (BA0)
A12 A20 A12 A11 Address
1
A11 A19 L/H* A10/AP Specifies
address/precharge
A10 A18 A10 A9 Address
A9 A17 A9 A8
A8 A16 A8 A7
A7 A15 A7 A6
A6 A14 A6 A5
A5 A13 A5 A4
A4 A12 A4 A3
A3 A11 A3 A2
A2 A10 A2 A1
A1 A9 A1 A0
A0 A8 A0 Unused
Example of connected memory
64-Mbit product (1 Mword x 16 bits x 4 banks, column 8 bits product): 1
Notes: 1. L/H is a bit used in the command specification; it is fixed at low or high according to the
access mode.
2. Bank address specification
Setting
A2/3 A2/3 A2/3
BSZ ROW COL
[1:0] [1:0] [1:0]
10 (16 bits) 01 (12 bits) 01 (9 bits)
Output Pin of Row Address Column Address Synchronous
This LSI Output Output DRAM Pin Function
A17 A26 A17 Unused
A16 A25 A16
A15 A24 A15
2
A14 A23* A23*2 A13 (BA1) Specifies bank
2 2
A13 A22* A22* A12 (BA0)
A12 A21 A12 A11 Address
1
A11 A20 L/H* A10/AP Specifies
address/precharge
A10 A19 A10 A9 Address
A9 A18 A9 A8
A8 A17 A8 A7
A7 A16 A7 A6
A6 A15 A6 A5
A5 A14 A5 A4
A4 A13 A4 A3
A3 A12 A3 A2
A2 A11 A2 A1
A1 A10 A1 A0
A0 A9 A0 Unused
Example of connected memory
128-Mbit product (2 Mwords x 16 bits x 4 banks, column 9 bits product): 1
Notes: 1. L/H is a bit used in the command specification; it is fixed at low or high according to the
access mode.
2. Bank address specification
Setting
A2/3 A2/3 A2/3
BSZ ROW COL
[1:0] [1:0] [1:0]
10 (16 bits) 01 (12 bits) 10 (10 bits)
Output Pin of Row Address Column Address Synchronous
This LSI Output Output DRAM Pin Function
A17 A27 A17 Unused
A16 A26 A16
A15 A25 A15
2
A14 A24* A24*2 A13 (BA1) Specifies bank
2 2
A13 A23* A23* A12 (BA0)
A12 A22 A12 A11 Address
1
A11 A21 L/H* A10/AP Specifies
address/precharge
A10 A20 A10 A9 Address
A9 A19 A9 A8
A8 A18 A8 A7
A7 A17 A7 A6
A6 A16 A6 A5
A5 A15 A5 A4
A4 A14 A4 A3
A3 A13 A3 A2
A2 A12 A2 A1
A1 A11 A1 A0
A0 A10 A0 Unused
Example of connected memory
256-Mbit product (4 Mwords x 16 bits x 4 banks, column 10 bits product): 1
Notes: 1. L/H is a bit used in the command specification; it is fixed at low or high according to the
access mode.
2. Bank address specification
Setting
A2/3 A2/3 A2/3
BSZ ROW COL
[1:0] [1:0] [1:0]
10 (16 bits) 10 (13 bits) 01 (9 bits)
Output Pin of Row Address Column Address Synchronous
This LSI Output Output DRAM Pin Function
A17 A26 A17 Unused
A16 A25 A16
2
A15 A24* A24*2 A14 (BA1) Specifies bank
2 2
A14 A23* A23* A13 (BA0)
A13 A22 A13 A12 Address
A12 A21 A12 A11
1
A11 A20 L/H* A10/AP Specifies
address/precharge
A10 A19 A10 A9 Address
A9 A18 A9 A8
A8 A17 A8 A7
A7 A16 A7 A6
A6 A15 A6 A5
A5 A14 A5 A4
A4 A13 A4 A3
A3 A12 A3 A2
A2 A11 A2 A1
A1 A10 A1 A0
A0 A9 A0 Unused
Example of connected memory
256-Mbit product (4 Mwords x 16 bits x 4 banks, column 9 bits product): 1
Notes: 1. L/H is a bit used in the command specification; it is fixed at low or high according to the
access mode.
2. Bank address specification
Setting
A2/3 A2/3 A2/3
BSZ ROW COL
[1:0] [1:0] [1:0]
10 (16 bits) 10 (13 bits) 10 (10 bits)
Output Pin of Row Address Column Address Synchronous
This LSI Output Output DRAM Pin Function
A17 A27 A17 Unused
A16 A26 A16
2
A15 A25* A25*2 A14 (BA1) Specifies bank
2 2
A14 A24* A24* A13 (BA0)
A13 A23 A13 A12 Address
A12 A22 A12 A11
1
A11 A21 L/H* A10/AP Specifies
address/precharge
A10 A20 A10 A9 Address
A9 A19 A9 A8
A8 A18 A8 A7
A7 A17 A7 A6
A6 A16 A6 A5
A5 A15 A5 A4
A4 A14 A4 A3
A3 A13 A3 A2
A2 A12 A2 A1
A1 A11 A1 A0
A0 A10 A0 Unused
Example of connected memory
512-Mbit product (8 Mwords x 16 bits x 4 banks, column 10 bits product): 1
Notes: 1. L/H is a bit used in the command specification; it is fixed at low or high according to the
access mode.
2. Bank address specification
This LSI always accesses the SDRAM with burst length 1. For example, read access of burst
length 1 is performed consecutively four times to read 16-byte continuous data from the SDRAM
that is connected to a 32-bit data bus.
Table 9.18 shows the relationship between the access size and the number of bursts.
Figures 9.14 and 9.15 show a timing chart in burst read. In burst read, an ACTV command is
output in the Tr cycle, the READ command is issued in the Tc1, Tc2, and Tc3 cycles, the READA
command is issued in the Tc4 cycle, and the read data is received at the rising edge of the external
clock (CKIO) in the Td1 to Td4 cycles. The Tap cycle is used to wait for the completion of an
auto-precharge induced by the READ command in the SDRAM. In the Tap cycle, a new
command will not be issued to the same bank. However, access to another CS space or another
bank in the same SDRAM space is enabled. The number of Tap cycles is specified by the TRP1
and TRP0 bits in CS3WCR.
In this LSI, wait cycles can be inserted by specifying each bit in CSnWCR to connect the SDRAM
in variable frequencies. Figure 9.15 shows an example in which wait cycles are inserted. The
number of cycles from the Tr cycle where the ACTV command is output to the Tc1 cycle where
the READA command is output can be specified using the TRCD1 and TRCD0 bits in CS3WCR.
If the TRCD1 and TRCD0 bits specify two cycles or more, a Trw cycle where the NOT command
is issued is inserted between the Tr cycle and Tc1 cycle. The number of cycles from the Tc1 cycle
where the READA command is output to the Td1 cycle where the read data is latched can be
specified for the CS2 and CS3 spaces independently, using the A2CL1 and A2CL0 bits in
CS2WCR or the A3CL1 and A3CL0 bits in CS3WCR and TRCD0 bit in CS3WCR. The number
of cycles from Tc1 to Td1 corresponds to the synchronous DRAM CAS latency. The CAS latency
for the synchronous DRAM is normally defined as up to three cycles. However, the CAS latency
in this LSI can be specified as 1 to 4 cycles. This CAS latency can be achieved by connecting a
latch circuit between this LSI and the synchronous DRAM.
CKIO
A25 to A0
A12/A11*1
CSn
RAS
CAS
RD/WR
DQMxx
D31 to D0
BS
DACKn*2
CKIO
A25 to A0
A12/A11*1
CSn
RAS
CAS
RD/WR
DQMxx
D31 to D0
BS
DACKn*2
A read access ends in one cycle when data exists in non-cacheable region and the data bus width is
larger than or equal to access size. As the burst length is set to 1 in SDRAM burst read/single
write mode, only the required data is output. Consequently, no unnecessary bus cycles are
generated even when a cache-through area is accessed.
CKIO
A25 to A0
A12/A11*1
CSn
RAS
CAS
RD/WR
DQMxx
D31 to D0
BS
DACKn*2
This LSI always accesses SDRAM with burst length 1. For example, write access of burst length 1
is performed continuously 4 times to write 16-byte continuous data to the SDRAM that is
connected to a 32-bit data bus. The relationship between the access size and the number of bursts
is shown in table 9.18.
Figure 9.17 shows a timing chart for burst writes. In burst write, an ACTV command is output in
the Tr cycle, the WRIT command is issued in the Tc1, Tc2, and Tc3 cycles, and the WRITA
command is issued to execute an auto-precharge in the Tc4 cycle. In the write cycle, the write data
is output simultaneously with the write command. After the write command with the auto-
precharge is output, the Trw1 cycle that waits for the auto-precharge initiation is followed by the
Tap cycle that waits for completion of the auto-precharge induced by the WRITA command in the
SDRAM. In the Tap cycle, a new command will not be issued to the same bank. However, access
to another CS space or another bank in the same SDRAM space is enabled. The number of Trw1
cycles is specified by the TRWL1 and TRWL0 bits in CS3WCR. The number of Tap cycles is
specified by the TRP1 and TRP0 bits in CS3WCR.
CKIO
A25 to A0
A12/A11*1
CSn
RAS
CAS
RD/WR
DQMxx
D31 to D0
BS
DACKn*2
A write access ends in one cycle when data is written in non-cacheable region and the data bus
width is larger than or equal to access size.
CKIO
A25 to A0
A12/A11*1
CSn
RAS
CAS
RD/WR
DQMxx
D31 to D0
BS
DACKn*2
The SDRAM bank function is used to support high-speed accesses to the same row address. When
the BACTV bit in SDCR is 1, accesses are performed using commands without auto-precharge
(READ or WRIT). This function is called bank-active function. This function is valid only for
either the upper or lower bits of area 3. When area 3 is set to bank-active mode, area 2 should be
set to normal space or byte-selection SRAM. When areas 2 and 3 are both set to SDRAM, auto-
precharge mode must be set.
When a bank-active function is used, precharging is not performed when the access ends. When
accessing the same row address in the same bank, it is possible to issue the READ or WRIT
command immediately, without issuing an ACTV command. As SDRAM is internally divided
into several banks, it is possible to activate one row address in each bank. If the next access is to a
different row address, a PRE command is first issued to precharge the relevant bank, then when
precharging is completed, the access is performed by issuing an ACTV command followed by a
READ or WRIT command. If this is followed by an access to a different row address, the access
time will be longer because of the precharging performed after the access request is issued. The
number of cycles between issuance of the PRE command and the ACTV command is determined
by the TRP[1:0] bits in CSnWCR.
In a write, when an auto-precharge is performed, a command cannot be issued to the same bank
for a period of Trwl + Tap cycles after issuance of the WRITA command. When bank active mode
is used, READ or WRIT commands can be issued successively if the row address is the same. The
number of cycles can thus be reduced by Trwl + Tap cycles for each write.
There is a limit on tRAS, the time for placing each bank in the active state. If there is no guarantee
that there will not be a cache hit and another row address will be accessed within the period in
which this value is maintained by program execution, it is necessary to set auto-refresh and set the
refresh cycle to no more than the maximum value of tRAS.
A burst read cycle without auto-precharge is shown in figure 9.19, a burst read cycle for the same
row address in figure 9.20, and a burst read cycle for different row addresses in figure 9.21.
Similarly, a single write cycle without auto-precharge is shown in figure 9.22, a single write cycle
for the same row address in figure 9.23, and a single write cycle for different row addresses in
figure 9.24.
In figure 9.20, a Tnop cycle in which no operation is performed is inserted before the Tc cycle that
issues the READ command. The Tnop cycle is inserted to acquire two cycles of CAS latency for
the DQMxx signal that specifies the read byte in the data read from the SDRAM. If the CAS
latency is specified as two cycles or more, the Tnop cycle is not inserted because the two cycles of
latency can be acquired even if the DQMxx signal is asserted after the Tc cycle.
When bank active mode is set, if only accesses to the respective banks in the area 3 space are
considered, as long as accesses to the same row address continue, the operation starts with the
cycle in figure 9.19 or 9.22, followed by repetition of the cycle in figure 9.20 or 9.23. An access to
a different area during this time has no effect. If there is an access to a different row address in the
bank active state, after this is detected the bus cycle in figure 9.21 or 9.24 is executed instead of
that in figure 9.20 or 9.23. In bank active mode, too, all banks become inactive after a refresh
cycle or after the bus is released as the result of bus arbitration.
CKIO
A25 to A0
A12/A11*1
CSn
RAS
CAS
RD/WR
DQMxx
D31 to D0
BS
DACKn*2
CKIO
A25 to A0
A12/A11*1
CSn
RAS
CAS
RD/WR
DQMxx
D31 to D0
BS
DACKn*2
Figure 9.20 Burst Read Timing (Bank Active, Same Row Address)
CKIO
A25 to A0
A12/A11*1
CSn
RAS
CAS
RD/WR
DQMxx
D31 to D0
BS
DACKn*2
Figure 9.21 Burst Read Timing (Bank Active, Different Row Addresses)
Tr Tc1
CKIO
A25 to A0
A12/A11*1
CSn
RAS
CAS
RD/WR
DQMxx
D31 to D0
BS
DACKn*2
Tnop Tc1
CKIO
A25 to A0
A12/A11*1
CSn
RAS
CAS
RD/WR
DQMxx
D31 to D0
BS
DACKn*2
Figure 9.23 Single Write Timing (Bank Active, Same Row Address)
Tp Tpw Tr Tc1
CKIO
A25 to A0
A12/A11*1
CSn
RAS
CAS
RD/WR
DQMxx
D31 to D0
BS
DACKn*2
Figure 9.24 Single Write Timing (Bank Active, Different Row Addresses)
(8) Refreshing
This LSI has a function for controlling SDRAM refreshing. Auto-refreshing can be performed by
clearing the RMODE bit to 0 and setting the RFSH bit to 1 in SDCR. A continuous refreshing can
be performed by setting the RRC[2:0] bits in RTCSR. If SDRAM is not accessed for a long
period, self-refresh mode, in which the power consumption for data retention is low, can be
activated by setting both the RMODE bit and the RFSH bit to 1.
(a) Auto-refreshing
Refreshing is performed at intervals determined by the input clock selected by bits CKS[2:0] in
RTCSR, and the value set by in RTCOR. The value of bits CKS[2:0] in RTCOR should be set so
as to satisfy the refresh interval stipulation for the SDRAM used. First make the settings for
RTCOR, RTCNT, and the RMODE and RFSH bits in SDCR, then make the CKS[2:0] and
RRC[2:0] settings. When the clock is selected by bits CKS[2:0], RTCNT starts counting up from
the value at that time. The RTCNT value is constantly compared with the RTCOR value, and if
the two values are the same, a refresh request is generated and an auto-refresh is performed for the
number of times specified by the RRC[2:0]. At the same time, RTCNT is cleared to 0 and the
count-up is restarted. Figure 9.25 shows the auto-refresh cycle timing.
After starting, the auto refreshing, PALL command is issued in the Tp cycle to make all the banks
to precharged state from active state when some bank is being precharged. Then REF command is
issued in the Trr cycle after inserting idle cycles of which number is specified by the TRP[1:0]bits
in CSnWCR. A new command is not issued for the duration of the number of cycles specified by
the TRC[1:0] bits in CSnWCR after the Trr cycle. The TRC[1:0] bits must be set so as to satisfy
the SDRAM refreshing cycle time stipulation (tRC). A NOP cycle is inserted between the Tp
cycle and Trr cycle when the setting value of the TRP[1:0] bits in CSnWCR is longer than or
equal to 2 cycles.
CKIO
A25 to A0
A12/A11*1
CSn
RAS
CAS
RD/WR
DQMxx
D31 to D0 Hi-z
BS
DACKn*2
(b) Self-refreshing
Self-refresh mode in which the refresh timing and refresh addresses are generated within the
SDRAM. Self-refreshing is activated by setting both the RMODE bit and the RFSH bit in SDCR
to 1. After starting the self-refreshing, PALL command is issued in Tp cycle after the completion
of the pre-charging bank. A SELF command is then issued after inserting idle cycles of which
number is specified by the TRP[1:0] bits in CSnWSR. SDRAM cannot be accessed while in the
self-refresh state. Self-refresh mode is cleared by clearing the RMODE bit to 0. After self-refresh
mode has been cleared, command issuance is disabled for the number of cycles specified by the
TRC[1:0] bits in CSnWCR.
Self-refresh timing is shown in figure 9.26. Settings must be made so that self-refresh clearing and
data retention are performed correctly, and auto-refreshing is performed at the correct intervals.
When self-refreshing is activated from the state in which auto-refreshing is set, or when exiting
standby mode other than through a power-on reset, auto-refreshing is restarted if the RFSH bit is
set to 1 and the RMODE bit is cleared to 0 when self-refresh mode is cleared. If the transition
from clearing of self-refresh mode to the start of auto-refreshing takes time, this time should be
taken into consideration when setting the initial value of RTCNT. Making the RTCNT value 1 less
than the RTCOR value will enable refreshing to be started immediately.
After self-refreshing has been set, the self-refresh state continues even if the chip standby state is
entered using the LSI standby function, and is maintained even after recovery from standby mode
by an interrupt.
In case of a power-on reset, the bus state controller's registers are initialized, and therefore the
self-refresh state is cleared.
CKIO
CKE
A25 to A0
A12/A11*1
CSn
RAS
CAS
RD/WR
DQMxx
D31 to D0 Hi-z
BS
DACKn*2
If a refresh request occurs during bus cycle execution, the refresh cycle must wait for the bus cycle
to be completed. If a refresh request occurs while the bus is released by the bus arbitration
function, the refresh will not be executed until the bus mastership is acquired. This LSI supports
requests by the REFOUT pin for the bus mastership while waiting for the refresh request. The
REFOUT pin is asserted low until the bus mastership is acquired.
If a new refresh request occurs while waiting for the previous refresh request, the previous refresh
request is deleted. To refresh correctly, a bus cycle longer than the refresh interval or the bus
mastership occupation must be prevented from occurring.
If a bus mastership is requested during self-refresh, the bus will not be released until the self-
refresh is completed.
If the PDOWN bit in SDCR is set to 1, the SDRAM is placed in the power-down mode by
bringing the CKE signal to the low level in the non-access cycle. This power-down mode can
effectively lower the power consumption in the non-access cycle. However, please note that if an
access occurs in power-down mode, a cycle of overhead occurs because a cycle that asserts the
CKE in order to cancel power-down mode is inserted.
CKIO
CKE
A25 to A0
A12/A11*1
CSn
RAS
CAS
RD/WR
DQMxx
D31 to D0
BS
DACKn*2
In order to use SDRAM, mode setting must first be performed after powering on. To perform
SDRAM initialization correctly, the bus state controller registers must first be set, followed by a
write to the SDRAM mode register. In SDRAM mode register setting, the address signal value at
that time is latched by a combination of the CSn, RAS, CAS, and RD/WR signals. If the value to
be set is X, the bus state controller provides for value X to be written to the SDRAM mode
register by performing a write to address H'A4FD4000 + X for area 2 SDRAM, and to address
H'A4FD5000 + X for area 3 SDRAM. In this operation the data is ignored, but the mode write is
performed as a byte-size access. To set burst read/single write, CAS latency 2 to 3, wrap type =
sequential, and burst length 1 supported by the LSI, arbitrary data is written in a byte-size access
to the addresses shown in table 9.19. In this time 0 is output at the external address pins of A12 or
later.
Mode register setting timing is shown in figure 9.28. A PALL command (all bank precharge
command) is firstly issued. A REF command (auto-refresh command) is then issued 8 times. An
MRS command (mode register write command) is finally issued. Idle cycles, of which number is
specified by the TRP[1:0] bits in CSnWCR, are inserted between the PALL and the first REF. Idle
cycles, of which number is specified by the TRC[1:0]bits in CSnWCR, are inserted between REF
and REF, and between the 8th REF and MRS. Idle cycles, of which number is one or more, are
inserted between the MRS and a command to be issued next.
It is necessary to keep idle time of certain cycles for SDRAM before issuing PALL command after
power-on. Refer the manual of the SDRAM for the idle time to be needed. When the pulse width
of the reset signal is longer then the idle time, mode register setting can be started immediately
after the reset, but care should be taken when the pulse width of the reset signal is shorter than the
idle time.
CKIO
A25 to A0
A12/A11*1
CSn
RAS
CAS
RD/WR
DQMxx
D31 to D0 Hi-Z
BS
DACKn*2
Figure 9.28 Write Timing for SDRAM Mode Register (Based on JEDEC)
The low-power SDRAM can be accessed using the same protocol as the normal SDRAM. The
differences between the low-power SDRAM and normal SDRAM are that partial refresh takes
place that puts only a part of the SDRAM in the self-refresh state during the self-refresh function,
and that power consumption is low during refresh under user conditions such as the operating
temperature. The partial refresh is effective in systems in which data in a work area other than the
specific area can be lost without severe repercussions. For details, refer to the data sheet for the
low-power SDRAM to be used.
The low-power SDRAM supports the extension mode register (EMRS) in addition to the mode
registers as the normal SDRAM. This LSI supports issuing of the EMRS command.
The EMRS command is issued according to the conditions specified in table 9.20. For example, if
data H'0YYYYYYY is written to address H'A4FD5XXX in long-word, the commands are issued
to the CS3 space in the following sequence: PALL -> REF × 8 -> MRS -> EMRS. In this case, the
MRS and EMRS issue addresses are H'0000XXX and H'YYYYYYY, respectively. If data
H'1YYYYYYY is written to address H'A4FD5XXX in long-word, the commands are issued to the
CS3 space in the following sequence: PALL -> MRS -> EMRS.
EMRS
Command to Access Write MRS Command Command Issue
be Issued Address Access Data Access Size Issue Address Address
CS2 MRS H'A4FD4XXX H'******** 16 bits H'0000XXX
CS3 MRS H'A4FD5XXX H'******** 16 bits H'0000XXX
CS2MRS H'A4FD4XXX H'0YYYYYYY 32 bits H'0000XXX H'YYYYYYY
+EMRS
(with refresh)
CS3 MRS H'A4FD5XXX H'0YYYYYYY 32 bits H'0000XXX H'YYYYYYY
+EMRS
(with refresh)
CS2 MRS H'A4FD4XXX H'1YYYYYYY 32 bits H'0000XXX H'YYYYYYY
+EMRS
(without
refresh)
CS3 MRS H'A4FD5XXX H'1YYYYYYY 32 bits H'0000XXX H'YYYYYYY
+EMRS
(without
refresh)
Tp Tpw Trr Trc Trc Trr Trc Trc Tmw Tnop Temw Tnop
PALL REF REF MRS EMRS
CKIO
A25 to A0
BA1*1
BA0*2
A12/A11*3
CSn
RAS
CAS
RD/WR
DQMxx
D31 to D0 Hi-Z
BS
DACKn*4
If the RMODE bit of the SDCR is set to 1 while the DEEP and RFSH bits of the SDCR are set to
1, the low-power SDRAM enters the deep power-down mode. If the RMODE bit is cleared to 0,
the CKE signal is pulled high to cancel the deep power-down mode. Before executing an access
after returning from the deep power-down mode, the power-up sequence must be re-executed.
CKIO
CKE
A25 to A0
A12/A11*1
CSn
RAS
CAS
RD/WR
DQMxx
D31 to D0 Hi-Z
BS
DACKn*2
The burst ROM (clock asynchronous) interface is used to access a memory with a high-speed read
function using a method of address switching called the burst mode or page mode. In a burst ROM
(clock asynchronous) interface, basically the same access as the normal space is performed, but
the 2nd and subsequent accesses are performed only by changing the address, without negating the
RD signal at the end of the 1st cycle. In the 2nd and subsequent accesses, addresses are changed at
the falling edge of the CKIO.
For the 1st access cycle, the number of wait cycles specified by the W[3:0] bits in CSnWCR is
inserted. For the 2nd and subsequent access cycles, the number of wait cycles specified by the
BW[1:0] bits in CSnWCR is inserted.
In the access to the burst ROM (clock asynchronous), the BS signal is asserted only to the first
access cycle. An external wait input is valid only to the first access cycle.
In the single access or write access that do not perform the burst operation in the burst ROM
(clock asynchronous) interface, access timing is same as a normal space.
Table 9.21 lists a relationship between bus width, access size, and the number of bursts. Figure
9.31 shows a timing chart.
Table 9.21 Relationship between Bus Width, Access Size, and Number of Bursts
Number of Number of
Bus Width BEN Bit Access Size Bursts Accesses
8 bits Not affected 8 bits 1 1
Not affected 16 bits 2 1
Not affected 32 bits 4 1
0 16 bytes 16 1
1 4 4
16 bits Not affected 8 bits 1 1
Not affected 16 bits 1 1
Not affected 32 bits 2 1
0 16 bytes 8 1
1 2 4
32 bits Not affected 8 bits 1 1
Not affected 16 bits 1 1
Not affected 32 bits 1 1
Not affected 16 bytes 4 1
CKIO
Address
CS
RD/WR
RD
Data
WAIT
BS
DACK
Figure 9.31 Burst ROM (Clock Asynchronous) Access (Bus Width = 32 Bits,
16-byte Transfer (Number of Bursts = 4), Access Wait for First Time = 2,
Access Wait for 2nd Time and after = 1)
The byte-selection SRAM interface is for access to an SRAM which has a byte-selection pin
(WEn (BEn)). This interface has 16-bit data pins and accesses SRAMs having upper and lower
byte selection pins, such as UB and LB.
When the BAS bit in CSnWCR is cleared to 0 (initial value), the write access timing of the byte-
selection SRAM interface is the same as that for the normal space interface. While in read access
of a byte-selection SRAM interface, the byte-selection signal is output from the WEn (BEn) pin,
which is different from that for the normal space interface. The basic access timing is shown in
figure 9.32. In write access, data is written to the memory according to the timing of the byte-
selection pin (WEn (BEn)). For details, refer to the data sheet for the corresponding memory.
If the BAS bit in CSnWCR is set to 1, the WEn (BEn) pin and RD/WR pin timings change. Figure
9.33 shows the basic access timing. In write access, data is written to the memory according to the
timing of the write enable pin (RD/WR). The data hold timing from RD/WR negation to data write
must be acquired by setting the HW[1:0] bits in CSnWCR. Figure 9.34 shows the access timing
when a software wait is specified.
T1 T2
CKIO
A25 to A0
CSn
WEn(BEn)
RD/WR
Read RD
D31 to D0
RD/WR
High
Write RD
D31 to D0
BS
DACKn*
T1 T2
CKIO
A25 to A0
CSn
WEn(BEn)
RD/WR
Read RD
D31 to D0
RD/WR
High
Write
RD
D31 to D0
BS
DACKn*
Th T1 Tw T2 Tf
CKIO
A25 to A0
CSn
WEn(BEn)
RD/WR
Read RD
D31 to D0
RD/WR
High
Write RD
D31 to D0
BS
DACKn*
Figure 9.34 Wait Timing for Byte-Selection SRAM (BAS = 1) (Software Wait Only)
64 k x 16 bits
This LSI SRAM
A17 A15
...
...
A2 A0
CSn CS
RD OE
RD/WR WE
D31
... I/O15
...
D16 I/O0
WE3(BE3) UB
WE2(BE2) LB
D15
...
A15
...
D0
WE1(BE1) A0
WE0(BE0) CS
OE
WE
I/O15
...
I/O0
UB
LB
64Kx16bit
This LSI SRAM
A16 A15
A1 A0
CSn CS
RD OE
RD/WR WE
D15 I/O 15
D0 I/O 0
WE1(BE1) UB
WE0(BE0) LB
With this LSI, if address map (2) is selected using the MAP bit in CMNCR, the PCMCIA
interface can be specified in areas 5 and 6. Areas 5 and 6 in the physical space can be used for the
IC memory card and I/O card interface defined in the JEIDA specifications version 4.2
(PCMCIA2.1 Rev. 2.1) by specifying the TYPE[3:0] bits of CSnBCR (n = 5B, 6B) to B'0101. In
addition, the SA[1:0] bits of CSnWCR (n = 5B, 6B) assign the upper or lower 32 Mbytes of each
area to an IC memory card or I/O card interface. For example, if the SA1 and SA0 bits of the
CS5BWCR are set to 1 and cleared to 0, respectively, the upper 32 Mbytes and the lower 32
Mbytes of area 5B are used as an IC memory card interface and I/O card interface, respectively.
When the PCMCIA interface is used, the bus size must be specified as 8 bits or 16 bits using the
BSZ[1:0] bits in CS5BBCR or CS6BBCR.
Figure 9.37 shows an example of a connection between this LSI and the PCMCIA card. To enable
insertion and removal of the PCMCIA card during system power-on, a three-state buffer must be
connected between the LSI and the PCMCIA card.
In the JEIDA and PCMCIA standards, operation in the big endian mode is not clearly defined.
Consequently, an original definition is provided for the PCMCIA interface in big endian mode in
this LSI.
PC card
This LSI (memory I/O)
A25 to A0 G
A25 to A0
D7 to D0
D15 to D8 D7 to D0
RD/WR
CE1A G
DIR
CE2A
D15 to D8
G
DIR
CE1
CE2
RD OE
WE WE/PGM
ICIORD IORD
ICIOWR IOWR
I/O Port REG
G
WAIT WAIT
IOIS16 IOIS16
Card
detection CD1,CD2
circuit
Figure 9.38 shows the basic timing of the PCMCIA IC memory card interface. If areas 5 and 6 in
the physical space are specified as the PCMCIA interface, accessing the common memory areas in
areas 5 and 6 automatically accesses the IC memory card interface. If the external bus frequency
(CKIO) increases, the setup times and hold times for the address pins (A25 to A0) to RD and WE,
card enable signals (CE1A, CE2A, CE1B, CE2B), and write data (D15 to D0) become
insufficient. To prevent this error, the LSI can specify the setup times and hold times for areas 5
and 6 in the physical space independently, using CS5BWCR and CS6BWCR. In the PCMCIA
interface, as in the normal space interface, a software wait or hardware wait can be inserted using
the WAIT pin. Figure 9.39 shows the PCMCIA memory bus wait timing.
CKIO
A25 to A0
CExx
RD/WR
RD
Read
D15 to D0
WE
Write
D15 to D0
BS
Figure 9.38 Basic Access Timing for PCMCIA Memory Card Interface
CKIO
A25 to A0
CExx
RD/WR
RD
Read
D15 to D0
WE
Write
D15 to D0
BS
WAIT
If all 32 Mbytes of the memory space are used as an IC memory card interface, the REG signal
that switches between the common memory and attribute memory can be generated by an I/O port.
If the memory space used for the IC memory card interface is 16 Mbytes or less, the A24 pin can
be used as the REG signal by using the memory space as a 16-Mbyte common memory space and
a 16-Mbyte attribute memory space.
PCMCIA interface area is 32 Mbytes (An I/O port is used as the REG)
Area 5 : H'14000000
Attribute memory/common memory
Area 5 : H'16000000
I/O space
Area 6 : H'18000000
Attribute memory/common memory
Area 6 : H'1A000000
I/O space
Area 5 : H'14000000
Attribute memory
Area 5 : H'15000000
Common memory
Area 5 : H'16000000
I/O space
H'17000000
Area 6 : H'18000000
Attribute memory
Area 6 : H'19000000
Common memory
Area 6 : H'1A000000
I/O space
H'1B000000
Figures 9.41 and 9.42 show the basic timings for the PCMCIA I/O card interface.
The I/O card and IC memory card interfaces can be switched using an address to be accessed. If
area 5 of the physical space is specified as the PCMCIA, the I/O card interface can automatically
be accessed by accessing the physical addresses from H'16000000 to H'17FFFFFF. If area 6 of the
physical space is specified as the PCMCIA, the I/O card interface can automatically be accessed
by accessing the physical addresses from H'1A000000 to H'1BFFFFFF.
Note that areas to be accessed as the PCMCIA I/O card must be non-cached if they are virtual
space (space P2 or P3) areas, or a non-cached area specified by the MMU.
If the PCMCIA card is accessed as an I/O card in little endian mode, dynamic bus sizing for the
I/O bus can be achieved using the IOIS16 signal. If the IOIS16 signal is brought high in a word-
size I/O bus cycle while the bus width of area 6 is specified as 16 bits, the bus width is recognized
as 8 bits and data is accessed twice in 8-bit units in the I/O bus cycle to be executed.
The IOIS16 signal is sampled at the falling edge of CKIO in the Tpci0, Tpci0w, and Tpci1 cycles
when the TED[3:0] bits are specified as 1.5 cycles or more, and is reflected in the CE2 signal 1.5
cycles after the CKIO sampling point. The TED[3:0] bits must be specified appropriately to satisfy
the setup time from ICIORD and ICIOWR of the PC card to CEn.
Note that the IOIS16 signal is not supported in big endian mode. In the big endian mode, the
IOIS16 signal must be fixed low.
CKIO
A25 to A0
CExx
RD/WR
ICIORD
Read
D15 to D0
ICIOWR
Write
D15 to D0
BS
CKIO
A25 to A0
CExx
RD/WR
ICIORD
Read
D15 to D0
ICIOWR
Write
D15 to D0
BS
WAIT
IOIS16
Tpci0 Tpci0w Tpci1 Tpci1w Tpci1w Tpci1w Tpci1w Tpci2 Tpci2w Tpci0 Tpci0w Tpci1 Tpci1w Tpci1w Tpci1w Tpci1w Tpci2 Tpci2w
CKIO
A25 to A0
CE1x
CE2x
RD/WR
ICIORD
Read
D15 to D0
ICIOWR
Write
D15 to D0
BS
WAIT
IOIS16
Figure 9.43 Timing for Dynamic Bus Sizing of PCMCIA I/O Card Interface
(TED[3:0] = B'0010, TEH[3:0] = B'0001, Software Waits = 3)
The burst ROM (clock synchronous) interface is supported to access a ROM with a synchronous
burst function at high speed. The burst ROM interface accesses the burst ROM in the same way as
a normal space. This interface is valid only for area 0.
In the first access cycle, wait cycles are inserted. In this case, the number of wait cycles to be
inserted is specified by the W[3:0] bits of the CS0WCR. In the second and subsequent cycles, the
number of wait cycles to be inserted is specified by the BW[1:0] bits of the CS0WCR.
While the burst ROM is accessed (clock synchronous), the BS signal is asserted only for the first
access cycle and an external wait input is also valid for the first access cycle.
If the bus width is 16 bits, the burst length must be specified as 8. If the bus width is 32 bits, the
burst length must be specified as 4. The burst ROM interface does not support the 8-bit bus width
for the burst ROM. The burst ROM interface performs burst operations for all read accesses. For
example, in a longword access over a 16-bit bus, valid 16-bit data is read two times and invalid
16-bit data is read six times.
These invalid data read cycles increase the memory access time and degrade the program
execution speed and DMA transfer speed. To prevent this problem, a 16-byte read by cache fill or
16-byte read by the DMA should be used. The burst ROM interface performs write accesses in the
same way as normal space access.
T1 Tw Tw T2B Twb T2B Twb T2B Twb T2B Twb T2B Twb T2B Twb T2B Twb T2
CKIO
Address
CSn
RD/WR
RD
D15 to D0
WAIT
BS
DACKn*
As the operating frequency of LSIs becomes higher, the off-operation of the data buffer often
collides with the next data access when the read operation from devices with slow access speed is
completed. As a result of these collisions, the reliability of the device is low and malfunctions may
occur. This LSI has a function that avoids data collisions by inserting wait cycles between
continuous access cycles.
The number of wait cycles between access cycles can be set by bits IWW[2:0], IWRWD[2:0],
IWRWS[2:0], IWRRD[2:0], and IWRRS[2:0] in CSnBCR, and bits DMAIW[2:0] and DMAIWA
in CMNCR. The conditions for setting the wait cycles between access cycles (idle cycles) are
shown below.
To prevent device malfunction while the bus mastership is transferred between master and slave,
the LSI negates all of the bus control signals before bus release. When the bus mastership is
received, all of the bus control signals are first negated and then driven appropriately. In this case,
output buffer contention can be prevented because the master and slave drive the same signals
with the same values. In addition, to prevent noise while the bus control signal is in the high
impedance state, pull-up resistors must be connected to these control signals.
Bus mastership is transferred at the boundary of bus cycles. Namely, bus mastership is released
immediately after receiving a bus request when a bus cycle is not being performed. The release of
bus mastership is delayed until the bus cycle is complete when a bus cycle is in progress. Even
when from outside the LSI it looks like a bus cycle is not being performed, a bus cycle may be
performing internally, started by inserting wait cycles between access cycles. Therefore, it cannot
be immediately determined whether or not bus mastership has been released by looking at the CSn
signal or other bus control signals. The states that do not allow bus mastership release are shown
below.
Bits DPRTY[1:0] in CMNCR can select whether or not the bus request is received during DMAC
burst transfer.
This LSI has the bus mastership until a bus request is received from another device. Upon
acknowledging the assertion (low level) of the external bus request signal BREQ, the LSI releases
the bus at the completion of the current bus cycle and asserts the BACK signal. After the LSI
acknowledges the negation (high level) of the BREQ signal that indicates the slave has released
the bus, it negates the BACK signal and resumes the bus usage.
The SDRAM issues an all bank precharge command (PALL) when active banks exist and releases
the bus after completion of a PALL command.
The bus sequence is as follows. The address bus and data bus are placed in a high-impedance state
synchronized with the rising edge of CKIO. The bus mastership enable signal is asserted 0.5
cycles after the above timing, synchronized with the falling edge of CKIO. The bus control signals
(BS, CSn, RAS, CAS, DQMxx, WEn (BEn), RD, and RD/WR) are placed in the high-impedance
state at subsequent rising edges of CKIO. Bus request signals are sampled at the falling edge of
CKIO.
The sequence for reclaiming the bus mastership from a slave is described below. 1.5 cycles after
the negation of BREQ is detected at the falling edge of CKIO, the bus control signals are driven
high. The BACK is negated at the next falling edge of the clock. The fastest timing at which actual
bus cycles can be resumed after bus control signal assertion is at the rising edge of the CKIO
where address and data signals are driven. Figure 9.45 shows the bus arbitration timing.
In an original slave device designed by the user, multiple bus accesses are generated continuously
to reduce the overhead caused by bus arbitration. In this case, to execute SDRAM refresh
correctly, the slave device must be designed to release the bus mastership within the refresh
interval time. To achieve this, the LSI instructs the REFOUT pin to request the bus mastership
while the SDRAM waits for the refresh. The LSI asserts the REFOUT pin until the bus mastership
is received. If the slave releases the bus, the LSI acquires the bus mastership to execute the
SDRAM refresh.
The bus release by the BREQ and BACK signal handshaking requires some overhead. If the slave
has many tasks, multiple bus cycles should be executed in a bus mastership acquisition. Reducing
the cycles required for master to slave bus mastership transitions streamlines the system design.
CKIO
BREQ
BACK
A25 to A0
D31 to D0
CSn
Other bus
control signals
The bus state controller (BSC) can be initialized completely only at power-on reset. At power-on
reset, all signals are negated and output buffers are turned off regardless of the bus cycle state. All
control registers are initialized. In standby, sleep, and manual reset, control registers of the bus
state controller are not initialized. At manual reset, the current bus cycle being executed is
completed and then the access wait state is entered. If a 16-byte transfer is performed by a cache
or if another LSI on-chip bus master module is executed when a manual reset occurs, the current
access is cancelled in longword units because the access request is cancelled by the bus master at
manual reset. If a manual reset is requested during cache fill operations, the contents of the cache
cannot be guaranteed. Since the RTCNT continues counting up during manual reset signal
assertion, a refresh request occurs to initiate the refresh cycle. In addition, a bus arbitration request
by the BREQ signal can be accepted during manual reset signal assertion.
Some flash memories may specify a minimum time from reset release to the first access. To
ensure this minimum time, the bus state controller supports a 5-bit counter (RWTCNT). At power-
on reset, the RWTCNT is cleared to 0. After power-on reset, RWTCNT is counted up
synchronously together with CKIO and an external access will not be generated until RWTCNT is
counted up to H′001F. At manual reset, RWTCNT is not cleared.
(2) Access from the Site of the LSI Internal Bus Master
There are three types of LSI internal buses: a cache bus, internal bus, and peripheral bus. The CPU
and cache memory are connected to the cache bus. Internal bus masters other than the CPU and
bus state controller are connected to the internal bus. Low-speed peripheral modules are connected
to the peripheral bus. Internal memories other than the cache memory and debugging modules
such as a UBC and AUD are connected bidirectionally to the cache bus and internal bus. Access
from the cache bus to the internal bus is enabled but access from the internal bus to the cache bus
is disabled. This gives rise to the following problems.
Internal bus masters such as DMAC other than the CPU can access on-chip memory other than the
cache memory but cannot access the cache memory. If an on-chip bus master other than the CPU
writes data to an external memory other than the cache, the contents of the external memory may
differ from that of the cache memory. To prevent this problem, if the external memory whose
contents is cached is written by an on-chip bus master other than the CPU, the corresponding
cache memory should be purged by software.
If the CPU initiates read access for the cache, the cache is searched. If the cache stores data, the
CPU latches the data and completes the read access. If the cache does not store data, the CPU
performs four contiguous longword read cycles to perform cache fill operations via the internal
bus. If a cache miss occurs in byte or word operand access or at a branch to an odd word boundary
(4n + 2), the CPU performs four contiguous longword accesses to perform a cache fill operation
on the external interface. For a cache-through area, the CPU performs access according to the
actual access addresses. For an instruction fetch to an even word boundary (4n), the CPU performs
longword access. For an instruction fetch to an odd word boundary (4n + 2), the CPU performs
word access.
For a read cycle of a cache-through area or an on-chip peripheral module, the read cycle is first
accepted and then read cycle is initiated. The read data is sent to the CPU via the cache bus.
In a write cycle for the cache area, the write cycle operation differs according to the cache write
methods.
In write-back mode, the cache is first searched. If data is detected at the address corresponding to
the cache, the data is then re-written to the cache. In the actual memory, data will not be re-written
until data in the corresponding address is re-written. If data is not detected at the address
corresponding to the cache, the cache is modified. In this case, data to be modified is first saved to
the internal buffer, 16-byte data including the data corresponding to the address is then read, and
data in the corresponding access of the cache is finally modified. Following these operations, a
write-back cycle for the saved 16-byte data is executed.
In write-through mode, the cache is first searched. If data is detected at the address corresponding
to the cache, the data is re-written to the cache simultaneously with the actual write via the internal
bus. If data is not detected at the address corresponding to the cache, the cache is not modified but
an actual write is performed via the internal bus.
Since the bus state controller (BSC) incorporates a one-stage write buffer, the BSC can execute an
access via the internal bus before the previous external bus cycle is completed in a write cycle. If
the on-chip module is read or written after the external low-speed memory is written, the on-chip
module can be accessed before the completion of the external low-speed memory write cycle.
In read cycles, the CPU is placed in the wait state until read operation has been completed. To
continue the process after the data write to the device has been completed, perform a dummy read
to the same address to check for completion of the write before the next process to be executed.
The write buffer of the BSC functions in the same way for an access by a bus master other than the
CPU such as the DMAC. Accordingly, to perform dual address DMA transfers, the next read cycle
is initiated before the previous write cycle is completed. Note, however, that if both the DMA
source and destination addresses exist in external memory space, the next write cycle will not be
initiated until the previous write cycle is completed.
To access an on-chip module register, two or more peripheral module clock (Pφ) cycles are
required. Care must be taken in system design.
BREQ > Refresh > LCDC > USBH > DMAC > CPU
Note that next transfer is not performed until current transfer (e.g. burst transfer) has completed.
The DMAC can be used in place of the CPU to perform high-speed transfers between external
devices that have DACK (transfer request acknowledge signal), external memory, on-chip
memory, memory-mapped external devices, and on-chip peripheral modules.
10.1 Features
• Six channels (two channels can receive an external request)
• 4-Gbyte physical address space
• Data transfer unit is selectable: Byte, word (2 bytes), longword (4 bytes), and 16 bytes
(longword × 4)
• Maximum transfer count: 16,777,216 transfers
• Address mode: Dual address mode or single address mode can be selected.
• Transfer requests:
External request, on-chip peripheral module request, or auto request can be selected.
The following modules can issue an on-chip peripheral module request.
SCIF0, SIOF1, MMC, CMT (channels 0 to 4), SIM, USBF, SIOF0, SIOF1, ADC, and
SDHI
• Selectable bus modes:
Cycle steal mode (normal mode and intermittent mode) or burst mode can be selected.
• Selectable channel priority levels:
The channel priority levels are selectable between fixed mode and round-robin mode.
• Interrupt request: An interrupt request can be generated to the CPU after transfers end by the
specified counts.
• External request detection: There are following four types of DREQ input detection.
Low level detection
High level detection
Rising edge detection
Falling edge detection
• Transfer request acknowledge signal:
Active levels for DACK and TEND can be set independently.
DMAC module
Iteration SARn
On-chip
control
memory
DARn
On-chip peripheral
Register
module
control
Peripheral bus
Internal bus
DMATCRn
Start-up
control CHCRn
DMA transfer
request signal DMAOR
Request
DMA transfer acknowledge signal priority
DEIn control DMARS0 to
Interrupt controller DMARS2
External Bus
ROM interface
External
RAM
External
I/O (memory
mapped) [Legend]
Bus state SARn: DMA source address register
External controller DARn: DMA destination address register
I/O (with DMATCRn: DMA transfer count register
acknowledge- CHCRn: DMA channel control register
ment) DMAOR: DMA operation register
DMARS0 to
DMARS2: DMA extended resource selector 0 to 2
DACK0, DACK1
DEIn: DMA transfer-end interrupt request to the CPU
TEND0, TEND1 n: 0, 1, 2, 3, 4, 5
DREQ0, DREQ1
(1) Channel 0
(2) Channel 1
(3) Channel 2
(4) Channel 3
(5) Channel 4
(6) Channel 5
(7) Common
SAR are 32-bit readable/writable registers that specify the source address of a DMA transfer.
During a DMA transfer, these registers indicate the next source address. When the data is
transferred from an external device with the DACK in single address mode, the SAR is ignored.
To transfer data in 16 bits or in 32 bits, specify the address with 16-bit or 32-bit address boundary.
When transferring data in 16-byte units, a 16-byte boundary must be set for the source address
value. The initial value is undefined.
DAR are 32-bit readable/writable registers that specify the destination address of a DMA transfer.
During a DMA transfer, these registers indicate the next destination address. When the data is
transferred from an external device with the DACK in single address mode, the DAR is ignored.
To transfer data in 16 bits or in 32 bits, specify the address with 16-bit or 32-bit address boundary.
When transferring data in 16-byte units, a 16-byte boundary must be set for the destination address
value. The initial value is undefined.
DMATCR are 32-bit readable/writable registers that specify the DMA transfer count. The number
of transfers is 1 when the setting is H'00000001, 16,777,215 when H'00FFFFFF is set, and
16,777,216 (the maximum) when H'00000000 is set. During a DMA transfer, these registers
indicate the remaining transfer count.
The upper eight bits of DMATCR are always read as 0, and the write value should always be 0. To
transfer data in 16 bytes, one 16-byte transfer (128 bits) counts one. The initial value is undefined.
CHCR are 32-bit readable/writable registers that control the DMA transfer mode.
Initial
Bit Bit Name Value R/W Descriptions
31 to 24 All 0 R Reserved
These bits are always read as 0. The write value should
always be 0.
23 DO 0 R/W DMA Overrun
Selects whether DREQ is detected by overrun 0 or by
overrun 1. This bit is valid only in CHCR_0 and
CHCR_1. This bit is always reserved and read as 0 in
CHCR_2 to CHCR_5. The write value should always be
0.
0: Detects DREQ by overrun 0
1: Detects DREQ by overrun 1
22 TL 0 R/W Transfer End Level
Specifies whether the TEND signal output is high active
or low active.
This bit is valid only in CHCR_0 and CHCR_1. This bit
is always reserved and read as 0 in CHCR2 to
CHCR_5. The write value should always be 0.
0: Low-active output of TEND
1: High-active output of TEND
21 to 18 All 0 R Reserved
These bits are always read as 0. The write value should
always be 0.
17 AM 0 R/W Acknowledge Mode
Selects whether DACK is output in data read cycle or in
data write cycle in dual address mode.
In single address mode, DACK is always output
regardless of the specification by this bit.
This bit is valid only in CHCR_0 and CHCR_1. This bit
is always reserved and read as 0 in CHCR_2 to
CHCR_5. The write value should always be 0.
0: DACK output in read cycle (dual address mode)
1: DACK output in write cycle (dual address mode)
Initial
Bit Bit Name Value R/W Descriptions
16 AL 0 R/W Acknowledge Level
Specifies whether the DACK signal output is high active
or low active.
This bit is valid only in CHCR_0 and CHCR_1. This bit
is always reserved and read as 0 in CHCR_2 to
CHCR_5. The write value should always be 0.
0: Low-active output of DACK
1: High-active output of DACK
15 DM1 0 R/W Destination Address Mode 1, 0
14 DM0 0 R/W Specify whether the DMA destination address is
incremented, decremented, or left fixed. (In single
address mode, the DM1 and DM0 bits are ignored
when data is transferred to an external device with
DACK.)
00: Fixed destination address (setting prohibited in 16-
byte transfer)
01: Destination address is incremented (+1 in byte-unit
transfer, +2 in word-unit transfer, +4 in longword-
unit transfer, +16 in 16-byte transfer)
10: Destination address is decremented (–1 in byte-unit
transfer, –2 in word-unit transfer, –4 in longword-
unit transfer; setting prohibited in 16-byte transfer)
11: Setting prohibited
13 SM1 0 R/W Source Address Mode 1, 0
12 SM0 0 R/W Specify whether the DMA source address is
incremented, decremented, or left fixed. (In single
address mode, SM1 and SM0 bits are ignored when
data is transferred from an external device with DACK.)
00: Fixed source address (setting prohibited in 16-byte
transfer)
01: Source address is incremented (+1 in byte-unit
transfer, +2 in word-unit transfer, +4 in longword-
unit transfer, +16 in 16-byte transfer)
10: Source address is decremented (–1 in byte-unit
transfer, –2 in word-unit transfer, –4 in longword-
unit transfer; setting prohibited in 16-byte transfer)
11: Setting prohibited
Initial
Bit Bit Name Value R/W Descriptions
11 RS3 0 R/W Resource Select 3 to 0
10 RS2 0 R/W Specify which transfer requests will be sent to the DMAC.
9 RS1 0 R/W The changing of transfer request source should be done
in the state that the DMA enable bit (DE) is set to 0.
8 RS0 0 R/W
0 0 0 0 External request, dual address mode
0 0 0 1 Setting prohibited
0 0 1 0 External request, single address mode
External address space → External device with
DACK
0 0 1 1 External request, single address mode
External device with DACK → External address
space
0 1 0 0 Auto request
0 1 0 1 Setting prohibited
0 1 1 0 Setting prohibited
0 1 1 1 Setting prohibited
1 0 0 0 Selected by DMA extended resource selector
1 0 0 1 Setting prohibited
1 0 1 0 Setting prohibited
1 0 1 1 Setting prohibited
1 1 0 0 Setting prohibited
1 1 0 1 Setting prohibited
1 1 1 0 ADC
1 1 1 1 Setting prohibited
Note: External request specification is valid only in
CHCR_0 and CHCR_1. None of the external
request can be selected in CHCR_2 to CHCR_5.
Initial
Bit Bit Name Value R/W Descriptions
7 DL 0 R/W DREQ Level and DREQ Edge Select
6 DS 0 R/W Specify the detecting method of the DREQ pin input and
the detecting level.
These bits are valid only in CHCR_0 and CHCR_1.
These bits are always reserved and read as 0 in CHCR_2
to CHCR_5. The write value should always be 0.
In channels 0 and 1, also, if the transfer request source is
specified as an on-chip peripheral module or if an auto-
request is specified, these bits are invalid.
00: DREQ detected in low level
01: DREQ detected at falling edge
10: DREQ detected in high level
11: DREQ detected at rising edge
5 TB 0 R/W Transfer Bus Mode
Specifies the bus mode when DMA transfers data.
0: Cycle steal mode
1: Burst mode
4 TS1 0 R/W Transfer Size 1, 0
3 TS0 0 R/W Specify the size of data to be transferred.
Select the size of data to be transferred when the source
or destination is an on-chip peripheral module register of
which transfer size is specified.
00: Byte size
01: Word size (2 bytes)
10: Longword size (4 bytes)
11: 16-byte unit (four longword transfers)
2 IE 0 R/W Interrupt Enable
Specifies whether or not an interrupt request is generated
to the CPU at the end of the DMA transfer. Setting this bit
to 1 generates an interrupt request (DEI) to the CPU
when the TE bit is set to 1.
0: Interrupt request is disabled.
1: Interrupt request is enabled.
Initial
Bit Bit Name Value R/W Descriptions
1 TE 0 R/(W)* Transfer End Flag
Shows that DMA transfer ends. The TE bit is set to 1
when data transfer ends when DMATCR becomes to 0.
The TE bit is not set to 1 in the following cases.
• DMA transfer ends due to an NMI interrupt or DMA
address error before DMATCR is cleared to 0.
• DMA transfer is ended by clearing the DE bit and
DME bit in the DMA operation register (DMAOR).
To clear the TE bit, the TE bit should be written to 0 after
reading 1.
Even if the DE bit is set to 1 while this bit is set to 1,
transfer is not enabled.
0: During the DMA transfer or DMA transfer has been
interrupted
[Clearing condition]
Writing 0 after TE = 1 read
1: DMA transfer ends by the specified count (DMATCR =
0)
0 DE 0 R/W DMA Enable
Enables or disables the DMA transfer. In auto request
mode, DMA transfer starts by setting the DE bit and DME
bit in DMAOR to 1. In this time, all of the bits TE, NMIF,
and AE in DMAOR must be 0. In an external request or
peripheral module request, DMA transfer starts if DMA
transfer request is generated by the devices or peripheral
modules after setting the bits DE and DME to 1. In this
case, however, all of the bits TE, NMIF, and AE must be
0, which is the same as in the case of auto request
mode. Clearing the DE bit to 0 can terminate the DMA
transfer.
0: DMA transfer disabled
1: DMA transfer enabled
Note: * Writing 0 is possible to clear the flag.
DMAOR is a 16-bit readable/writable register that specifies the priority level of channels at the
DMA transfer. This register shows the DMA transfer status.
Initial
Bit Bit Name Value R/W Description
15, 14 All 0 R Reserved
These bits are always read as 0. The write value should
always be 0.
13 CMS1 0 R/W Cycle Steal Mode Select 1, 0
12 CMS0 0 R/W Select either normal mode or intermittent mode in cycle
steal mode.
It is necessary that all channel's bus modes are set to
cycle steal mode to make valid intermittent mode.
00: Normal mode
01: Setting prohibited
10: Intermittent mode 16
Executes one DMA transfer in each of 16 clocks of an
external bus clock.
11: Intermittent mode 64
Executes one DMA transfer in each of 64 clocks of an
external bus clock.
11, 10 All 0 R Reserved
These bits are always read as 0. The write value should
always be 0.
9 PR1 0 R/W Priority Mode 1, 0
8 PR0 0 R/W Select the priority level between channels when there are
transfer requests for multiple channels simultaneously.
00: CH0 > CH1 > CH2 > CH3 > CH4 > CH5
01: CH0 > CH2 > CH3 > CH1 > CH4 > CH5
10: Setting prohibited
11: Round-robin mode
7 to 3 All 0 R Reserved
These bits are always read as 0. The write value should
always be 0.
Initial
Bit Bit Name Value R/W Description
2 AE 0 R/(W)* Address Error Flag
Indicates that an address error occurred during DMA
transfer. If this bit is set, DMA transfer is disabled even if
the DE bit in CHCR and the DME bit in DMAOR are set to
1. This bit can only be cleared by writing 0 after reading
1.
0: No DMAC address error
[Clearing condition]
Writing AE = 0 after AE = 1 read
1: DMAC address error occurs
1 NMIF 0 R/(W)* NMI Flag
Indicates that an NMI interrupt occurred. If this bit is set,
DMA transfer is disabled even if the DE bit in CHCR and
the DME bit in DMAOR are set to 1. This bit can only be
cleared by writing 0 after reading 1.
When the NMI is input, the DMA transfer in progress can
be done in one transfer unit. When the DMAC is not in
operational, the NMIF bit is set to 1 even if the NMI
interrupt was input.
0: No NMI interrupt
[Clearing condition]
Writing NMIF = 0 after NMIF = 1 read
1: NMI interrupt occurs
0 DME 0 R/W DMA Master Enable
Enables or disables DMA transfers on all channels. If the
DME bit and the DE bit in CHCR are set to 1, transfer is
enabled. In this time, all of the bits TE in CHCR, NMIF,
and AE in DMAOR must be 0. If this bit is cleared during
transfer, transfers in all channels are terminated.
0: Disables DMA transfers on all channels
1: Enables DMA transfers on all channels
Note: * Writing 0 is possible to clear the flag.
DMARS are 16-bit readable/writable registers that specify the DMA transfer sources from
peripheral modules in each channel. DMARS0 specifies for channels 0 and 1, DMARS1 specifies
for channels 2 and 3, and DMARS2 specifies for channels 4 and 5. This register can set the
transfer request of SCIF0, SIOF1, MMC, CMT (channels 0 to 4), SIM, USBF, SIOF0, SIOF1, and
SDHI.
When MID/RID other than the values listed in table 10.2 is set, the operation of this LSI is not
guaranteed. The transfer request from DMARS is valid only when the resource select bits (RS3 to
RS0) have been set to B'1000 for CHCR_0 to CHCR_5 registers. Otherwise, even if DMARS has
been set, transfer request source is not accepted.
• DMARS0
Initial
Bit Bit Name Value R/W Description
15 C1MID5 0 R/W Transfer request module ID5 to ID0 for DMA channel 1
14 C1MID4 0 R/W (MID)
12 C1MID2 0 R/W
11 C1MID1 0 R/W
10 C1MID0 0 R/W
9 C1RID1 0 R/W Transfer request register ID1 and ID0 for DMA channel 1
8 C1RID0 0 R/W (RID)
See table 10.2.
7 C0MID5 0 R/W Transfer request module ID5 to ID0 for DMA channel 0
6 C0MID4 0 R/W (MID)
4 C0MID2 0 R/W
3 C0MID1 0 R/W
2 C0MID0 0 R/W
1 C0RID1 0 R/W Transfer request register ID1 and ID0 for DMA channel 0
0 C0RID0 0 R/W (RID)
See table 10.2.
• DMARS1
Initial
Bit Bit Name Value R/W Description
15 C3MID5 0 R/W Transfer request module ID5 to ID0 for DMA channel 3
14 C3MID4 0 R/W (MID)
12 C3MID2 0 R/W
11 C3MID1 0 R/W
10 C3MID0 0 R/W
9 C3RID1 0 R/W Transfer request register ID1 and ID0 for DMA channel 3
8 C3RID0 0 R/W (RID)
See table 10.2.
7 C2MID5 0 R/W Transfer request module ID5 to ID0 for DMA channel 2
6 C2MID4 0 R/W (MID)
4 C2MID2 0 R/W
3 C2MID1 0 R/W
2 C2MID0 0 R/W
1 C2RID1 0 R/W Transfer request register ID1 and ID0 for DMA channel 2
0 C2RID0 0 R/W (RID)
See table 10.2.
• DMARS2
Initial
Bit Bit Name Value R/W Description
15 C5MID5 0 R/W Transfer request module ID5 to ID0 for DMA channel 5
14 C5MID4 0 R/W (MID)
12 C5MID2 0 R/W
11 C5MID1 0 R/W
10 C5MID0 0 R/W
9 C5RID1 0 R/W Transfer request register ID1 and ID0 for DMA channel 5
8 C5RID0 0 R/W (RID)
See table 10.2.
7 C4MID5 0 R/W Transfer request module ID5 to ID0 for DMA channel 4
6 C4MID4 0 R/W (MID)
4 C4MID2 0 R/W
3 C4MID1 0 R/W
2 C4MID0 0 R/W
1 C4RID1 0 R/W Transfer request register ID1 and ID0 for DMA channel 4
0 C4RID0 0 R/W (RID)
See table 10.2.
10.4 Operation
When there is a DMA transfer request, the DMAC starts the transfer according to the
predetermined channel priority; when the transfer end conditions are satisfied, it ends the transfer.
Transfers can be requested in three modes: auto request, external request, and on-chip peripheral
module request. In bus mode, burst mode or cycle steal mode can be selected.
After the DMA source address registers (SAR), DMA destination address registers (DAR), DMA
transfer count registers (DMATCR), DMA channel control registers (CHCR), DMA operation
register (DMAOR), and DMA extended resource selectors (DMARS) are set, the DMAC transfers
data according to the following procedure:
Start
Initial settings
(SAR, DAR, DMATCR, CHCR, DMAOR, DMARS)
Yes
Transfer request No *2
occurs?*1
Bus mode,
Yes *3 transfer request mode,
DREQ detection selection
Transfer (1 transfer unit); system
DMATCR – 1 → DMATCR, SAR and DAR
updated
NMIF = 1 No
No
DMATCR = 0? or AE = 1 or DE = 0
or DME = 0?
Yes
Yes
TE = 1 Transfer aborted
NMIF = 1 No
or AE = 1 or DE = 0
or DME = 0?
Yes
Transfer end Normal end
Notes: 1. In auto-request mode, transfer begins when the NMIF, AE, and TE bits are all 0 and the DE and
DME bits are set to 1.
2. DREQ = level detection in burst mode (external request) or cycle-steal mode.
3. DREQ = edge detection in burst mode (external request), or auto-request mode in burst mode.
DMA transfer requests are basically generated in either the data transfer source or destination, but
they can also be generated by external devices or on-chip peripheral modules that are neither the
source nor the destination. Transfers can be requested in three modes: auto request, external
request, and on-chip peripheral module request. The request mode is selected in the RS3 to RS0
bits in CHCR0 to CHCR3, and DMARS0 to DMARS2.
In this mode, a transfer is performed at the request signals (DREQ0 and DREQ1) of an external
device. This mode is valid only in channel 0 and channel 1. Choose one of the modes shown in
table 10.3 according to the application system. When this mode is selected, if the DMA transfer is
enabled (DE = 1, DME = 1, TE = 0, AE = 0, NMIF = 0), a transfer is performed upon a request at
the DREQ input.
Choose to detect DREQ by either the edge or level of the signal input with the DL bit and DS bit
in CHCR_0 and CHCR_1 as shown in table 10.4. The source of the transfer request does not have
to be the data transfer source or destination.
CHCR_0 or CHCR_1
DL DS Detection of External Request
0 0 Low level detection
1 Falling edge detection
1 0 High level detection
1 Rising edge detection
When DREQ is accepted, the DREQ pin becomes request accept disabled state. After issuing
acknowledge signal DACK for the accepted DREQ, the DREQ pin again becomes request accept
enabled state.
When DREQ is used by level detection, there are following two cases by the timing to detect the
next DREQ after outputting DACK.
• Overrun 0: Transfer is aborted after the same number of transfer has been performed as
requests.
• Overrun 1: Transfer is aborted after transfers have been performed for (the number of requests
plus 1) times.
CHCR_0 or CHCR_1
DO External Request
0 Overrun 0
1 Overrun 1
In this mode, a transfer is performed at the transfer request signal of an on-chip peripheral module.
Transfer request signals comprise the transmit data empty transfer request and receive data full
transfer request from the ADC set by CHCR0 to CHCR5 and the SCIF0, SCIF1, MMC, USBF,
SIM, SIOF0, SIOF1, and SDHI set by DMARS0/1/2, and the compare-match timer transfer
request from the CMT (channels 0 to 4).
When this mode is selected, if the DMA transfer is enabled (DE = 1, DME = 1, TE = 0, AE = 0,
NMIF = 0), a transfer is performed upon the input of a transfer request signal.
When a transmit data empty transfer request of the SCIF0 is set as the transfer request, the transfer
destination must be the SCIF0's transmit data register. Likewise, when receive data full transfer
request of the SCIF0 is set as the transfer request, the transfer source must be the SCIF0's receive
data register. These conditions also apply to the SIOF1, MMC, USBF, SIM, SIOF0, SIOF1, and
SDHI. When the ADC is set as the transfer request, the transfer source must be the A/D data
register. Any address can be specified for data source and destination, when transfer request is
generated by the CMT (channels 0 to 4).
The number of the receive FIFO triggers can be set as a transfer request depending on an on-chip
peripheral module. Data needs to be read after the DMA transfer is ended, because data may be
remained in the receive FIFO when the receive FIFO trigger condition is not satisfied.
Table 10.6 Selecting On-Chip Peripheral Module Request Modes with RS3 to RS0 Bits
CHCR DMARS DMA Transfer
Request DMA Transfer Bus
RS[3:0] MID RID Source Request Signal Source Destination Mode
1000 001000 01 SCIF0 TXI0 (transmit FIFO data Any SCFTDR0 Cycle
transmitter empty interrupt) steal
10 SCIF0 RXI0 (receive FIFO data SCFRDR0 Any Cycle
receiver full interrupt) steal
001010 01 SCIF1transmitt TXI1 (transmit FIFO data Any SITDR Cycle
er empty interrupt) steal
10 SCIF1 RXI1 (receive FIFO data SCFRDR1 Any Cycle
receiver full interrupt) steal
000000 11 CMT Compare-match transfer Any Any Cycle
(channel 0) request steal/
burst
000001 11 CMT Compare-match transfer Any Any Cycle
(channel 1) request steal/
burst
000010 11 CMT Compare-match transfer Any Any Cycle
(channel 2) request steal/
burst
000011 11 CMT Compare-match transfer Any Any Cycle
(channel 3) request steal/
burst
000100 11 CMT Compare-match transfer Any Any Cycle
(channel 4) request steal/
burst
When the DMAC receives simultaneous transfer requests on two or more channels, it transfers
data according to a predetermined priority. Two modes (fixed mode and round-robin mode) are
selected by the PR1 and PR0 bits in DMAOR.
In this mode, the priority levels among the channels remain fixed. There are two kinds of fixed
modes as follows:
• CH0 > CH1 > CH2 > CH3 > CH4 > CH5
• CH0 > CH2 > CH3 > CH1 > CH4 > CH5
These are selected by the PR1 and the PR0 bits in DMAOR.
In round-robin mode each time data of one transfer unit (word, byte, longword, or 16-byte unit) is
transferred on one channel, the priority is rotated. The channel on which the transfer was just
finished rotates to the bottom of the priority. The round-robin mode operation is shown in figure
10.3. The priority of round-robin mode is CH0 > CH1 > CH2 > CH3 > CH4 > CH5 immediately
after a reset. When round-robin mode is specified, the same bus mode, either cycle steal mode or
burst mode, must be specified for all of the channels.
Initial priority order CH0 > CH1 > CH2 > CH3 > CH4 > CH5 Channel 0 becomes bottom
priority
Priority order
CH1 > CH2 > CH3 > CH4 > CH5 > CH0
after transfer
Initial priority order CH0 > CH1 > CH2 > CH3 > CH4 > CH5 Priority order does not change.
Priority order
CH0 > CH1 > CH2 > CH3 > CH4 > CH5
after transfer
Figure 10.4 shows how the priority changes when channel 0 and channel 3 transfers are requested
simultaneously and a channel 1 transfer is requested during the channel 0 transfer. The DMAC
operates as follows:
DMA transfer has two types; single address mode transfer and dual address mode transfer. They
depend on the number of bus cycles of access to source and destination. A data transfer timing
depends on the bus mode, which has cycle steal mode and burst mode. The DMAC supports the
transfers shown in table 10.7.
Destination
Memory-
External Mapped On-Chip
Device with External External Peripheral X/Y Memory
Source DACK Memory Device Module U Memory
External device with DACK Not Dual, Dual, Not Not
available single single available available
External memory Dual, single Dual Dual Dual Dual
Memory-mapped external Dual, single Dual Dual Dual Dual
device
On-chip peripheral module Not Dual Dual Dual Dual
available
X/Y memory Not Dual Dual Dual Dual
available
Notes: 1. Dual: Dual address mode
2. Single: Single address mode
3. For on-chip peripheral modules, 16-byte transfer is available only by registers which
can be accessed in longword units.
In dual address mode, both the transfer source and destination are accessed by an address. The
source and destination can be located externally or internally.
DMA transfer requires two bus cycles because data is read from the transfer source in a data read
cycle and written to the transfer destination in a data write cycle. At this time, transfer data is
temporarily stored in the DMAC. In the transfer between external memories as shown in figure
10.5, data is read to the DMAC from one external memory in a data read cycle, and then that data
is written to the other external memory in a write cycle.
DMAC
SAR Memory
Address bus
DAR
Transfer source
Data bus
module
Transfer destination
Data buffer
module
The SAR value is an address, data is read from the transfer source module,
and the data is temporarily stored in the DMAC.
DMAC
SAR Memory
Address bus
Data bus
DAR
Transfer source
module
Transfer destination
Data buffer
module
The DAR value is an address and the value stored in the data buffer in the
DMAC is written to the transfer destination module.
Second bus cycle
Auto request, external request, and on-chip peripheral module request are available for the transfer
request. DACK can be output in read cycle or write cycle in dual address mode. The channel
control register (CHCR) can specify whether the DACK is output in read cycle or write cycle.
Figure 10.6 shows an example of DMA transfer timing in dual address mode.
CKIO
CSn
D31 to D0
RD
WEn
DACKn
(Active-low)
Note: In transfer between external memories, with DACK output in the read cycle,
DACK output timing is the same as that of CSn.
In single address mode, either the transfer source or transfer destination peripheral device is
accessed (selected) by means of the DACK signal, and the other device is accessed by an address.
In this mode, the DMAC performs one DMA transfer in one bus cycle, accessing one of the
external devices by outputting the DACK transfer request acknowledge signal to it, and at the
same time outputting an address to the other device involved in the transfer. For example, in the
case of transfer between external memory and an external device with DACK shown in figure
10.7, when the external device outputs data to the data bus, that data is written to the external
memory in the same bus cycle.
This LSI
External
DMAC memory
External device
with DACK
DACK
DREQ
Data flow
Two kinds of transfer are possible in single address mode: (1) transfer between an external device
with DACK and a memory-mapped external device, and (2) transfer between an external device
with DACK and external memory. In both cases, only the external request signal (DREQ) is used
for transfer requests.
Figure 10.8 shows an example of DMA transfer timing in single address mode.
CKIO
(a) External device with DACK → external memory space (ordinary memory)
CKIO
(b) External memory space (ordinary memory) → external device with DACK
There are two bus modes: cycle steal mode and burst mode. Select the mode in the TB bits in the
channel control register (CHCR).
• Normal mode
In cycle-steal normal mode, the bus mastership is given to another bus master after a one-
transfer-unit (byte, word, longword, or 16-byte unit) DMA transfer. When another transfer
request occurs, the bus mastership is obtained from the other bus master and a transfer is
performed for one transfer unit. When that transfer ends, the bus mastership is passed to the
other bus master. This is repeated until the transfer end conditions are satisfied.
In cycle-steal normal mode, transfer areas are not affected regardless of settings of the transfer
request source, transfer source, and transfer destination.
Figure 10.9 shows an example of DMA transfer timing in cycle-steal normal mode. Transfer
conditions shown in the figure are:
Dual address mode
DREQ low level detection
DREQ
Bus cycle CPU CPU CPU DMAC DMAC CPU DMAC DMAC CPU
Read/Write Read/Write
This intermittent mode can be used for all transfer section; transfer request source, transfer
source, and transfer destination. The bus modes, however, must be cycle steal mode in all
channels.
Figure 10.10 shows an example of DMA transfer timing in cycle steal intermittent mode.
Transfer conditions shown in the figure are:
Dual address mode
DREQ low level detection
DREQ
More than 16 or 64 Bφ
(change by the CPU, LCDC, and USBH states of using bus)
Bus cycle CPU CPU CPU DMAC DMAC CPU CPU DMAC DMAC CPU
Read/Write Read/Write
In burst mode, once the DMAC obtains the bus mastership, the transfer is performed continuously
without releasing the bus mastership until the transfer end condition is satisfied. In external
request mode with level detection of the DREQ pin, however, when the DREQ pin is not active,
the bus mastership passes to the other bus master after the DMAC transfer request that has already
been accepted ends, even if the transfer end conditions have not been satisfied.
Burst mode cannot be used for other than CMT (channels 0 to 4) when the on-chip peripheral
module is the transfer request source.
DREQ
Bus cycle CPU CPU CPU DMAC DMAC DMAC DMAC DMAC DMAC CPU
Read Write Read Write Read Write
(3) Relationship between Request Modes and Bus Modes by DMA Transfer Category
Table 10.8 shows the relationship between request modes and bus modes by DMA transfer
category.
Table 10.8 Relationship between Request Modes and Bus Modes by DMA Transfer
Category
Notes: 1. External requests, auto requests, and on-chip peripheral module requests are all
available. In the case of on-chip peripheral module requests, however, the CMT
(channels 0 to 4) are only available.
2. External requests, auto requests, and on-chip peripheral module requests are all
available. However, with the exception of the CMT (channels 0 to 4) as the transfer
request source, the request source register must be designated as the transfer source
or the transfer destination.
3. Only cycle steal except for the CMT (channels 0 to 4) as the transfer request source.
4. Access size permitted for the on-chip peripheral module register functioning as the
transfer source or transfer destination.
5. If the transfer request is an external request, channels 0 and 1 are only available.
When the priority is set in fixed mode (CH0 > CH1), even though channel 1 is transferring in burst
mode, if there is a transfer request to channel 0 which has a higher priority, the transfer of channel
0 will begin immediately.
At this time, if channel 0 is also operating in burst mode, the channel 1 transfer will continue when
the channel 0 transfer with a higher priority has completely finished.
If channel 0 is operating in cycle steal mode, immediately after channel 0 with a higher priority
completes the transfer of one transfer unit, the channel 1 transfer will begin again without
releasing the bus mastership. Transfer will then switch between the two in the order of channel 0,
channel 1, channel 0, and channel 1. For the bus state, the CPU cycle after cycle steal mode
transfer finishes is replaced with a burst mode transfer cycle (hereafter referred to as burst mode
high-priority execution).
This example is illustrated in figure 10.12. If there are channels with conflicting burst transfers,
transfer for the channel with the highest priority is performed first.
In DMA transfer for more than one channel, the DMAC does not give the bus mastership to the
bus master until all conflicting burst transfers have finished.
CPU DMAC CH1 DMAC CH0 and CH1 DMAC CH1 CPU
Burst mode Cycle-steal mode Burst mode
In round-robin mode, the priority changes according to the specifications shown in figure 10.3.
Note that a channel operating in cycle steal mode cannot be handled together with a channel
operating in burst mode.
10.4.5 Number of Bus Cycle States and DREQ Pin Sampling Timing
When the DMAC is the bus master, the number of bus cycle states is controlled by the bus state
controller (BSC) in the same way as when the CPU is the bus master. For details, see section 9,
Bus State Controller (BSC).
Figures 10.13, 10.14, 10.15, and 10.16 show the sample timing of the DREQ input in each bus
mode, respectively.
CKIO
DACK
(High-active) Acceptance started
Figure 10.13 Example of DREQ Input Detection in Cycle Steal Mode Edge Detection
CKIO
CKIO
Figure 10.14 Example of DREQ Input Detection in Cycle Steal Mode Level Detection
CKIO
DACK
(High-active)
Figure 10.15 Example of DREQ Input Detection in Burst Mode Edge Detection
CKIO
CKIO
Figure 10.16 Example of DREQ Input Detection in Burst Mode Level Detection
CKIO
DREQ
DACK
TEND
Figure 10.17 Example of DMA Transfer End in Cycle Steal Mode Level Detection
When an 8-bit or 16-bit external device is accessed in longword units, or when an 8-bit external
device is accessed in word units, the DACK output is divided because of the data alignment. This
example is illustrated in figure 10.18.
T1 T2 Taw T1 T2
CKIO
Address
CSn
RD
Data
WEn
DACKn
(Active-low)
WAIT
When burst mode and cycle steal mode are simultaneously set in two or more channels, an
additional DACK may be asserted at the end of burst transfer. This phenomenon will occur when
all of the conditions described below are satisfied.
1. When the DMA transfer is simultaneously performed in two or more channels support both
burst mode and cycle steal mode
2. When the channel to be used in burst mode is set to dual address mode, and DACK is output in
data write cycle
3. When the DMAC cannot obtain the bus mastership consecutively even though a transfer
demand of cycle steal has been received after the completion of burst transfer
• Measure 1
After confirming the completion of burst transfer (TE bit = 1), perform the DMA transfer of
other cycle steal mode
• Measure 2
The channel to be used in burst mode should not be set to output DACK in data write cycle
• Measure 3
When the DMA transfer is simultaneously performed in two or more channels, set all of the
channels to burst mode or cycle steal mode
(1) Overview
When DACK is divided for output while the DMAC is accessing an external device, sampling of
DREQ may be accepted once more during the access.
Conditions: In the cases when DACK is divided for output during external access, specifically, the
following cases:
• 16-byte access
• 32-bit access in an 8-bit space
• 16-bit access in an 8-bit space
• 32-bit access in a 16-bit space,
Any one of the following inter-access idle cycle specifications has been made for that space:
Phenomena: For the access patterns above, the DREQ pin signal is detected with the timing shown
in figures 10.19 and 10.21. For other access patterns, DREQ is detected normally as shown in
figures 10.20 and 10.22.
For the external accesses under the conditions of 2 above, the problems can be avoided in the
following way:
1. Detection of DREQ edges: During the bus cycle, input a DREQ edge (rising edge) only once at
most.
2. When overrun-0 in DREQ level detection is specified: During the bus cycle, negate the DREQ
input after detection of the first DACK output negation but before the second DACK output
negation takes place.
3. When overrun-1 in DREQ level detection is specified: During the bus cycle, negate the DREQ
input after detection of the first DACK output assertion but before the second DACK output
assertion takes place.
CKIO
Figure 10.19 Timing of DREQ Input Detection by Edge Detection in Cycle Stealing Mode
(DACK is Divided into Four due to Idle Cycle Insertion between Access Cycles and So
DREQ Sampling is Accepted One Extra Time)
CKIO
Third
First acceptance Second acceptance acceptance
DREQ
(rising edge)
Dead zone Dead zone Dead zone
DACK
(active-high)
Acceptance Acceptance
started started
Figure 10.20 Timing of DREQ Input Detection by Edge Detection in Cycle Stealing Mode
(DACK is Not Divided By Idle Cycle Insertion between Access Cycles and So DREQ
Sampling is Accepted Normally)
CKIO
Second
DREQ First acceptance acceptance Third acceptance (possible)
(overrun 0,
high level)
Dead zone Dead zone
DACK
(active-high)
Acceptance started
CKIO
Figure 10.21 Timing of DREQ Input Detection by Level Detection in Cycle Stealing Mode
(DACK is Divided into Four due to Idle Cycle Insertion between Access Cycles and So
DREQ Sampling is Accepted One Extra Time)
CKIO
Figure 10.22 Timing of DREQ Input Detection by Edge Detection in Cycle Stealing Mode
(DACK is Not Divided By Idle Cycle Insertion between Access Cycles and So DREQ
Sampling is Accepted Normally)
1. Before making a transition to standby mode, either wait until DMA transfer finishes or
suspend DMA transfer.
2. If an on-chip peripheral module whose clock supply is to be stopped by the module standby
functio
