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Evaluation of AMD's advanced synchronization facility within a complete transactional memory stack | Proceedings of the 5th European conference on Computer systems

research-article

Evaluation of AMD's advanced synchronization facility within a complete transactional memory stack

Authors:

Jae-Woong Chung,

Stephan Diestelhorst,

Michael Hohmuth,

Martin Pohlack,

Christof Fetzer,

Torvald Riegel,

Patrick Marlier,

Etienne RivièreAuthors Info & Claims

EuroSys '10: Proceedings of the 5th European conference on Computer systems

Pages 27 - 40

https://doi.org/10.1145/1755913.1755918

Published: 13 April 2010 Publication History

Abstract

AMD's Advanced Synchronization Facility (ASF) is an x86 instruction set extension proposal intended to simplify and speed up the synchronization of concurrent programs. In this paper, we report our experiences using ASF for implementing transactional memory. We have extended a C/C++ compiler to support language-level transactions and generate code that takes advantage of ASF. We use a software fallback mechanism for transactions that cannot be committed within ASF (e.g., because of hardware capacity limitations). Our evaluation uses a cycle-accurate x86 simulator that we have extended with ASF support. Building a complete ASF-based software stack allows us to evaluate the performance gains that a user-level program can obtain from ASF. Our measurements on a wide range of benchmarks indicate that the overheads traditionally associated with software transactional memories can be significantly reduced with the help of ASF.

References

[1]

Software Optimization Guide for AMD Family 10h Proces-- sors. Advanced Micro Devices, Inc., 3.05 edition, Jan. 2007.

[2]

Advanced Synchronization Facility -- Proposed Architectural Specification.Advanced Micro Devices, Inc., 2.1 edition, Mar. 2009.

[3]

G. M. Amdahl. Validity of the single processor approach to achieving large scale computing capabilities. Readings in computer architecture, 2000.

Digital Library

[4]

P. Barham, B. Dragovic, K. Fraser, S. Hand, T. L. Harris, A. Ho, R. Neugebauer, I. Pratt, and A. Warfield. Xen and the art of virtualization. In Proceedings of the 19th ACM symposium on Operating systems principles (SOSP), Boston Landing, NY, USA, 2003.

Digital Library

[5]

E. D. Berger, K. S. McKinley, R. D. Blumofe, and P. R. Wilson. Hoard: A scalable memory allocator for multithreaded applications. In Proceedings of the 9th international conference on Architectural support for programming languages and operating systems (ASPLOS), 2000.

Digital Library

[6]

C. Cao Minh, J. Chung, C. Kozyrakis, and K. Olukotun. STAMP: Stanford transactional applications for multi-processing. In Proceedings of The IEEE International Symposium on Workload Characterization (IISWC), Seattle, WA, USA, Sept. 2008.

[7]

C. Cascaval, C. Blundell, M. Michael, H. W. Cain, P. Wu, S. Chiras, and S. Chatterjee. Software transactional memory: Why is it only a research toy? Commun. ACM, 51(11), 2008.

Digital Library

[8]

C. Click. Azul's experiences with hardware transactional memory. In HP Labs -- Bay Area Workshop on Transactional Memory, Jan. 2009.

[9]

P. Damron, A. Fedorova, Y. Lev, V. Luchangco, M. Moir, and D. Nussbaum. Hybrid transactional memory. In Proceedings of the 12th international conference on Architectural support for programming languages and operating systems (ASPLOS), San Jose, CA, USA, 2006.

Digital Library

[10]

D. Dice, O. Shalev, and N. Shavit. Transactional locking II. In Proceedings of the 20th International Symposium on Distributed Computing (DISC), Stockholm, Sweden, 2006.

Digital Library

[11]

D. Dice, Y. Lev, M. Moir, and D. Nussbaum. Early experience with a commercial hardware transactional memory implementation. In Proceeding of the 14th international conference on Architectural support for programming languages and operating systems (ASPLOS), Washington, DC, USA, 2009.

Digital Library

[12]

S. Diestelhorst and M. Hohmuth. Hardware acceleration for lock-free data structures and software-transactional memory. In Proceedings of the Workshop on Exploiting Parallelism with Transactional Memory and other Hardware Assisted Methods (EPHAM), Boston, MA, USA, Apr. 2008.

[13]

P. Felber, C. Fetzer, U. Müller, T. Riegel, M. Süßkraut, and H. Sturzrehm. Transactifying applications using an open com-- piler framework. In Proceedings of the 2nd ACM SIGPLAN Workshop on Transactional Computing (TRANSACT), Portland, OR, USA, Aug. 2007.

[14]

P. Felber, C. Fetzer, and T. Riegel. Dynamic performance tuning of word-based software transactional memory. In Proceedings of the 13th ACM SIGPLAN Symposium on Principles and Practice of Parallel Programming (PPoPP), Salt Lake City, UT, USA, Feb. 2008.

Digital Library

[15]

M. Herlihy. A methodology for implementing highly concurrent data structures. In Proceedings of the 2nd ACM SIGPLAN Symposium on Principles and Practice of Parallel Programming (PPoPP), Seattle, WA, USA, 1990.

Digital Library

[16]

M. Herlihy and J. E. B. Moss. Transactional memory: Architectural support for lock-free data structures. In Proceedings of the International Symposium on Computer Architecture (ISCA), San Diego, CA, USA, May 1993.

Digital Library

[17]

Intel. Draft Specification of Transactional Language Constructs for C++. Intel, IBM, Sun, 1.0 edition, Aug. 2009.

[18]

Intel. Intel Transactional Memory Compiler and Runtime Application Binary Interface. Intel, 1.0.1 edition, Nov. 2008.

[19]

S. Kumar, M. Chu, C. J. Hughes, P. Kundu, and A. Nguyen. Hybrid transactional memory. In Proceedings of the 11th ACM SIGPLAN symposium on Principles and practice of parallel programming (PPoPP), New York City, NY, USA, Mar. 2006.

Digital Library

[20]

C. Lattner and V. Adve. LLVM: A compilation framework for lifelong program analysis & transformation. In Proceedings of the International Symposium on Code Generation and Optimization (CGO), Palo Alto, CA, USA, Mar. 2004.

Digital Library

[21]

Y. Lev, M. Moir, and D. Nussbaum. PhTM: Phased transactional memory. In Proceedings of the 2nd ACM SIGPLAN Workshop on Transactional Computing (TRANSACT), Portland, OR, USA, Aug. 2007.

[22]

S. Lie. Hardware support for unbounded transactional memory. Master's thesis, May 2004. Massachusetts Institute of Technology.

[23]

C. C. Minh, M. Trautmann, J. Chung, A. McDonald, N. Bronson, J. Casper, C. Kozyrakis, and K. Olukotun. An effective hybrid transactional memory system with strong isolation guarantees. SIGARCH Comput. Archit. News, 35(2), 2007.

Digital Library

[24]

J. E. B. Moss and A. L. Hosking. Nested transactional memory: model and architecture sketches. Sci. Comput. Program., 63(2), 2006. ISSN 0167--6423.

Digital Library

[25]

R. Rajwar and J. R. Goodman. Speculative lock elision: enabling highly concurrent multithreaded execution. In Proceedings of the 34th ACM/IEEE International Symposium on Microarchitecture (MICRO), Austin, TX, USA, Dec. 2001.

Digital Library

[26]

R. Rajwar, M. Herlihy, and K. Lai. Virtualizing transactional memory. In Proceedings of the 32nd Annual International Symposium on Computer Architecture (ISCA), Washington, DC, USA, 2005.

Digital Library

[27]

B. Saha, A.-R. Adl-Tabatabai, R. L. Hudson, C. C. Minh, and B. Hertzberg. McRT-STM: a high performance software transactional memory system for a multi-core runtime. In Proceedings of the 11th ACM SIGPLAN symposium on Principles and practice of parallel programming (PPoPP), New York, NY, USA, Mar. 2006.

Digital Library

[28]

B. Saha, A.-R. Adl-Tabatabai, and Q. Jacobson. Architectural support for software transactional memory. In Proceedings of the 39th Annual IEEE/ACM International Symposium on Microarchitecture (MICRO), Washington, DC, USA, 2006.

Digital Library

[29]

A. Shriraman, M. F. Spear, H. Hossain, V. Marathe, S. Dwarkadas, and M. L. Scott.An integrated hardware-software approach to flexible transactional memory. In Proceedings of the 34th annual international symposium on Computer architecture (ISCA), San Diego, CA, USA, 2007.

Digital Library

[30]

T. Skare and C. Kozyrakis. Early release: Friend or foe? In Workshop on Transactional Memory Workloads. Jun 2006.

[31]

L. Yen, J. Bobba, M. M. Marty, K. E. Moore, H. Volos, M. D. Hill, M. M. Swift, and D. A. Wood.LogTM-SE: Decoupling hardware transactional memory from caches. In Proceedings of the 13th IEEE International Symposium on High Performance Computer Architecture (HPCA). Phoenix, AR, USA, 2007.

Digital Library

[32]

M. T. Yourst. PTLsim: A cycle accurate full system x86-64 microarchitectural simulator. In Proceedings of the IEEE International Symposium on Performance Analysis of Systems and Software (ISPASS), Apr. 2007.

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Evaluation of AMD's advanced synchronization facility within a complete transactional memory stack

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cover image ACM Conferences

EuroSys '10: Proceedings of the 5th European conference on Computer systems

April 2010

388 pages

ISBN:9781605585772

DOI:10.1145/1755913

General Chair:
Christine Morin
INRIA Rennes, France
,
Program Chair:
Gilles Muller
INRIA/LIP6, France

Copyright © 2010 ACM.

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Published: 13 April 2010

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transactional memory

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EuroSys '10: Fifth EuroSys Conference 2010

April 13 - 16, 2010

Paris, France

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Overall Acceptance Rate 241 of 1,308 submissions, 18%

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https://doi.org/10.1109/IPDPS54959.2023.00021
Jain AKadiyala DDaglis A(2023)Safety Hints for HTM Capacity Abort Mitigation2023 IEEE International Symposium on High-Performance Computer Architecture (HPCA)10.1109/HPCA56546.2023.10071113(206-219)Online publication date: Feb-2023
https://doi.org/10.1109/HPCA56546.2023.10071113
Zhang JYi QPeterson CDechev D(2023)Compiler‐driven approach for automating nonblocking synchronization in concurrent data abstractionsConcurrency and Computation: Practice and Experience10.1002/cpe.793536:5Online publication date: 24-Oct-2023
https://doi.org/10.1002/cpe.7935
Gordon MBarca GLeang SPoole DRendell AGalvez Vallejo JWestheimer B(2020)Novel Computer Architectures and Quantum ChemistryThe Journal of Physical Chemistry A10.1021/acs.jpca.0c02249124:23(4557-4582)Online publication date: 7-May-2020
https://doi.org/10.1021/acs.jpca.0c02249
Zardoshti PZhou TBalaji PScott MSpear M(2019)Simplifying Transactional Memory Support in C++ACM Transactions on Architecture and Code Optimization10.1145/332879616:3(1-24)Online publication date: 25-Jul-2019
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Hahn EHashemi VHermanns HLahijanian MTurrini A(2019)Interval Markov Decision Processes with Multiple ObjectivesACM Transactions on Modeling and Computer Simulation10.1145/330968329:4(1-31)Online publication date: 18-Nov-2019
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Cheh CThakore UFawaz AChen BTemple WSanders W(2019)Data-driven Model-based Detection of Malicious Insiders via Physical Access LogsACM Transactions on Modeling and Computer Simulation10.1145/330954029:4(1-25)Online publication date: 18-Nov-2019
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de Carvalho JAraujo GBaldassin A(2019)The Case for Phase-Based Transactional MemoryIEEE Transactions on Parallel and Distributed Systems10.1109/TPDS.2018.286171230:2(459-472)Online publication date: 1-Feb-2019
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Wang ZKozuch MMowry TSeshadri V(2019)Multiversioned Page Overlays: Enabling Faster Serializable Hardware Transactional MemoryProceedings of the International Conference on Parallel Architectures and Compilation Techniques10.1109/PACT.2019.00038(394-407)Online publication date: 23-Sep-2019
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Zardoshti PZhou TLiu YSpear M(2019)Optimizing Persistent Memory TransactionsProceedings of the International Conference on Parallel Architectures and Compilation Techniques10.1109/PACT.2019.00025(219-231)Online publication date: 23-Sep-2019
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