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Massively Parallel Rule-Based Interpreter Execution on GPUs Using Thread Compaction

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Abstract

Interpreters are well researched in the field of compiler construction and program generation. They are typically used to realize program execution of different programming languages without a compilation step. However, they can also be used to model complex rule-based simulations: The interpreter applies all rules one after another. These can be iteratively applied on a globally updated state in order to get the final simulation result. Many simulations for domain-specific problems already leverage the parallel processing capabilities of Graphics Processing Units (GPUs). They use hardware-specific tuned rule implementations to achieve maximum performance. However, every interpreter-based system requires a high-level algorithm that detects active rules and determines when they are evaluated. A common approach in this context is the use of different interpreter routines for every problem domain. Executing such functions in an efficient way mainly involves dealing with hardware peculiarities like thread divergences, ALU computations and memory operations. Furthermore, the interpreter is often executed on multiple states in parallel these days. This is particularly important for heuristic search or what-if analyses, for instance. In this paper, we present a novel and easy-to-implement method based on thread compaction to realize generic rule-based interpreters in an efficient way on GPUs. It is optimized for many states using a specially designed memory layout. Benchmarks on our evaluation scenarios show that the performance can be significantly increased in comparison to existing commonly-used implementations.

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Notes

  1. A single SIMT unit will be referred to as a warp in the scope of this paper. Furthermore, every warp will be visualized with the help of eight lanes (threads). Groups will be visualized with the help of three warps.

  2. This perfectly fits to the common bank-size configuration of 4 bytes on common GPUs.

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Acknowledgements

The authors would like to thank Wladimir Panfilenko and Thomas Schmeyer for their suggestions and feedback regarding our method. Furthermore, we would like to thank Gian-Luca Kiefer for additional feedback on the paper. This work was funded by the German Ministry of Education and Research: Project Hybr-iT: Hybrid and Intelligent Human–Robot Collaboration (Grant Number 01IS16026A).

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  1. Saarland Informatics Campus, Campus D3.2, Saarbrücken, Saarland, Germany

    M. Köster, J. Groß & A. Krüger

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  1. M. Köster
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  2. J. Groß
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  3. A. Krüger
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Correspondence to M. Köster.

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Köster, M., Groß, J. & Krüger, A. Massively Parallel Rule-Based Interpreter Execution on GPUs Using Thread Compaction. Int J Parallel Prog 48, 675–691 (2020). https://doi.org/10.1007/s10766-020-00670-2

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