iBet uBet web content aggregator. Adding the entire web to your favor.
iBet uBet web content aggregator. Adding the entire web to your favor.



Link to original content: https://unpaywall.org/10.1007/S10617-022-09264-2
Selective register-file cache: an energy saving technique for embedded processor architecture | Design Automation for Embedded Systems Skip to main content
Springer Nature Link
Log in

Selective register-file cache: an energy saving technique for embedded processor architecture

  • Published:
Design Automation for Embedded Systems Aims and scope Submit manuscript

Abstract

Embedded system applications of present-day scenario consume profound energy in execution and its significant fraction is due to an intensive register-file access in the processor architecture. This paper presents a novel architecture incorporating a multi-banked register file organization and a selective replacement technique referred as selective register file cache to capture actively reused and short-lived register operands. This alleviates the load on register file while performing read and write operations. Thus, the proposed architecture achieved maximum energy saving of 68% while accessing a register file over a conventional embedded processor architecture. Subsequently, it consumes an average energy of 8.48 \(\upmu \)J which is 51% lesser than the energy consumption of reduced-instruction set-computer (RISC-V) baseline processor-architecture.

This is a preview of subscription content, log in via an institution to check access.

Access this article

Log in via an institution

Subscribe and save

Springer+ Basic
$34.99 /Month
  • Get 10 units per month
  • Download Article/Chapter or eBook
  • 1 Unit = 1 Article or 1 Chapter
  • Cancel anytime
Subscribe now

Buy Now

Price excludes VAT (USA)
Tax calculation will be finalised during checkout.

Instant access to the full article PDF.

Institutional subscriptions

Fig. 1
Fig. 2
Fig. 3
Fig. 4
Fig. 5
Fig. 6

Similar content being viewed by others

References

  1. Hennessy JL, Patterson DA (2011) Computer architecture: a quantitative approach, 5th edn. Morgan Kaufmann Publishers Inc., San Francisco

    MATH  Google Scholar 

  2. Gonzales DR (1999) Micro-RISC architecture for the wireless market. IEEE Micro 19(4):30–37

    Article  Google Scholar 

  3. Ayala JL, Lopez-Vallejo M, Veidenbaum A, Lopez CA (2003) Energy aware register file implementation through instruction predecode. In: IEEE international conference on application-specific systems, architectures, and processors, pp 86–96

  4. Shieh W-Y, Chen H-D (2008) Saving register-file static power by monitoring short-lived temporary-values in ROB. In: 13th Asia-pacific computer systems architecture conference (ACSAC), pp 1–8

  5. Wang S, Jin T, Zheng C, Duan G (2012) Low power aging-aware register file design by duty cycle balancing. In: Design, automation and test in Europe conference and exhibition (DATE), pp 546–549

  6. Gong N, Wang J, Jiang S, Sridhar R (2015) TM-RF: aging-aware power-efficient register file design for modern microprocessors. IEEE Trans Very Large Scale Integr VLSI Syst 23(7):1196–1209

    Article  Google Scholar 

  7. Tabkhi H, Schirner G (2014) Application-guided power gating reducing register file static power. IEEE Trans Very Large Scale Integr VLSI Syst 22(12):2513–2526

    Article  Google Scholar 

  8. Kim S (2007) Reducing ALU and register file energy by dynamic zero detection. In: IEEE international performance, computing, and communications conference, pp 365–371

  9. Balkan D, Sharkey J, Ponomarev D, Ghose K (2008) Predicting and exploiting transient values for reducing register file pressure and energy consumption. IEEE Trans Comput 57(1):82–95

    Article  MathSciNet  Google Scholar 

  10. Balkan D, Sharkey J, Ponomarev D, Ghose K (2008) Selective writeback: reducing register file pressure and energy consumption. IEEE Trans Very Large Scale Integr VLSI Syst 16(6):650–661

    Article  Google Scholar 

  11. Tseng JH, Asanovic K (2000) Energy-efficient register access. In: 13th Symposium on integrated circuits and systems design, pp 377–382

  12. Gonzalez R, Cristal A, Ortega D, Veidenbaum A, Valero M (2004) A content aware integer register file organization. In: 31st Annual international symposium on computer architecture, pp 314–324

  13. Zalamea J, Llosa J, Ayguade E, Valero M (2000) Two-level hierarchical register file organization for VLIW processors. In: 33rd Annual IEEE/ACM international symposium on microarchitecture, 2000. MICRO-33, pp 137–146

  14. Hui Zeng, NY Binghamton, Ghose K (2006) Register file caching for energy efficiency. In: Proceedings of the 2006 international symposium on low power electronics and design (ISLPED’06), pp 244–249

  15. Yung R, Wilhelm NC (1995) Caching processor general registers. In: 1995 IEEE international conference on computer design: VLSI in computers and processors, 1995. ICCD ’95. Proceedings, pp 307–312

  16. Shioya R, Horio K, Goshima M, Sakai S (2010) Register cache system not for latency reduction purpose. In: 2010 43rd Annual IEEE/ACM international symposium on microarchitecture, pp 301–312

  17. Hu Z, Martonosi M. Reducing register file power consumption by exploiting value lifetime characteristics. In: Workshop on complexity-effective design (WCED)

  18. Balasubramonian R, Dwarkadas S, Albonesi DH (2001) Reducing the complexity of the register file in dynamic superscalar processors. In: Proceedings of the 34th annual ACM/IEEE international symposium on microarchitecture, ser. MICRO 34. IEEE Computer Society, Washington, DC, USA, pp 237–248. [Online]. Available: http://dl.acm.org/citation.cfm?id=563998.564029

  19. Cruz J-L, González A, Valero M, Topham NP (2000) Multiple-banked register file architectures. In: Proceedings of the 27th annual international symposium on computer architecture, ser. ISCA ’00. ACM, New York, NY, USA, pp 316–325. [Online]. Available: https://doi.org/10.1145/339647.339708

  20. Tseng J H, Asanović K (2003) Banked multiported register files for high-frequency superscalar microprocessors. In: Proceedings of the 30th annual international symposium on computer architecture, ser. ISCA ’03. ACM, New York, NY, USA, pp 62–71. [Online]. Available: https://doi.org/10.1145/859618.859627

  21. Butts JA, Sohi GS (2004) Use-based register caching with decoupled indexing. In: Proceedings of the 31st annual international symposium on computer architecture, ser. ISCA ’04. IEEE Computer Society, Washington, DC, USA, pp 302. [Online]. Available: http://dl.acm.org/citation.cfm?id=998680.1006724

  22. Lozano LA, Gao GR (1995) Exploiting short-lived variables in superscalar processors. In: Proceedings of the 28th annual international symposium on microarchitecture, pp 292–302

  23. Swensen JA, Patt YN (1988) Hierarchical registers for scientific computers. In: Proceedings of the 2Nd international conference on supercomputing, ser. ICS ’88. ACM, New York, NY, USA, pp 346–354. [Online]. Available: https://doi.org/10.1145/55364.55398

  24. Jones TM, O’Boyle MFP, Abella J, González A, Ergin O (2009) Energy-efficient register caching with compiler assistance. ACM Trans Archit Code Optim 6(4):13:1-13:23. https://doi.org/10.1145/1596510.1596511

    Article  Google Scholar 

  25. Balfour J, Harting RC, Dally WJ (2009) Operand registers and explicit operand forwarding. IEEE Comput Archit Lett 8(2):60–63

    Article  Google Scholar 

  26. Zeng H, Ghose K (2006) Register file caching for energy efficiency. In: Proceedings of the 2006 international symposium on low power electronics and design, ser. ISLPED ’06. Minus. ACM, New York, NY, USA, pp 244–249. [Online]. Available: https://doi.org/10.1145/1165573.1165633

  27. Gebhart M, Johnson DR, Tarjan D, Keckler SW, Dally WJ, Lindholm E, Skadron K (2011) Energy-efficient mechanisms for managing thread context in throughput processors. In: Proceedings of the 38th annual international symposium on computer architecture, ser. ISCA ’11. ACM, New York, NY, USA, pp 235–246. [Online]. Available: https://doi.org/10.1145/2000064.2000093

  28. Muralimanohar N, Balasubramonian R, Jouppi NP (2009) CACTI 6.0: a tool to model large caches. HP Laboratories, pp 22–31

  29. Austin T, Larson E, Ernst D (2002) Simplescalar: an infrastructure for computer system modeling. Computer 35(2):59–67. https://doi.org/10.1109/2.982917

    Article  Google Scholar 

  30. Burger D, Austin TM (1997) The SimpleScalar tool set, Version 2.0

Download references

Author information

Authors and Affiliations

  1. Department of Computer Science, The University of Utah, Saltlake City, USA

    Sumanth Gudaparthi

  2. School of Computing and Electrical Engineering, Indian Institute of Technology Mandi, Mandi, India

    Rahul Shrestha

Authors
  1. Sumanth Gudaparthi
    View author publications

    You can also search for this author in PubMed Google Scholar

  2. Rahul Shrestha
    View author publications

    You can also search for this author in PubMed Google Scholar

Corresponding author

Correspondence to Rahul Shrestha.

Additional information

Publisher's Note

Springer Nature remains neutral with regard to jurisdictional claims in published maps and institutional affiliations.

Rights and permissions

Reprints and permissions

About this article

Check for updates. Verify currency and authenticity via CrossMark

Cite this article

Gudaparthi, S., Shrestha, R. Selective register-file cache: an energy saving technique for embedded processor architecture. Des Autom Embed Syst 26, 105–124 (2022). https://doi.org/10.1007/s10617-022-09264-2

Download citation

  • Received:

  • Accepted:

  • Published:

  • Issue Date:

  • DOI: https://doi.org/10.1007/s10617-022-09264-2

Keywords

Search

Navigation