iBet uBet web content aggregator. Adding the entire web to your favor.
iBet uBet web content aggregator. Adding the entire web to your favor.



Link to original content: https://unpaywall.org/10.1007/S10617-009-9040-8
Using method interception for hardware/software co-development | Design Automation for Embedded Systems Skip to main content
Log in

Using method interception for hardware/software co-development

  • Published:
Design Automation for Embedded Systems Aims and scope Submit manuscript

Abstract

In many embedded systems, the computational power of an instruction set processor is combined with hardware accelerators. Building such combined systems implies co-design of the software that runs on the processor and the hardware that accelerates the embedded application. During the co-design process, the application is partitioned into a software part (running on the processor) and a hardware part (running on the accelerator). In order to ease the iterative process of partitioning, we introduce a novel design methodology. In our methodology, the interface between hardware and software is transparent to the software designer, and is based on dynamic method interception. Because the interface is transparent and generated automatically, the initial all-software prototype of the system can more easily be refined and partitioned. We show that method interception is inexpensive, and we demonstrate method interception in a real-life application.

Using our methodology, embedded systems can be designed fast, reducing time-to-market, while still achieving a high run-time performance.

This is a preview of subscription content, log in via an institution to check access.

Access this article

Subscribe and save

Springer+ Basic
$34.99 /Month
  • Get 10 units per month
  • Download Article/Chapter or eBook
  • 1 Unit = 1 Article or 1 Chapter
  • Cancel anytime
Subscribe now

Buy Now

Price excludes VAT (USA)
Tax calculation will be finalised during checkout.

Instant access to the full article PDF.

Similar content being viewed by others

References

  1. Alpern B, Attanasio CR, Barton JJ, Burke MG, Cheng P, Choi JD, Cocchi A, Fink SJ, Grove D, Hind M, Hummel SF, Lieber D, Litvinov V, Mergen MF, Ngo T, Russel JR, Sarkar V, Serrano MJ, Shepherd JC, Smith SE, Sreedhar VC, Srinivasan H, Whaley J (2000) The Jalapeño virtual machine. IBM Syst J 39(1):211–238

    Google Scholar 

  2. Andrews D, Niehaus D, Jidin R, Finley M, Peck W, Frisbie M, Ortiz J, Komp E, Ashenden P (2004) Programming models for hybrid FPGA-CPU computational components: a missing link. IEEE Micro 24(4):42–53

    Article  Google Scholar 

  3. Beck ACS, Carro L (2005) Dynamic reconfiguration with binary translation: breaking the ILP barrier with software compatibility. In: Proceedings of the 42nd annual design automation conference (DAC). ACM, New York, pp 732–737

    Chapter  Google Scholar 

  4. Bertels P, Heirman W, D’Hollander E, Stroobandt D (2009) Efficient memory management for hardware accelerated java virtual machines. ACM Trans Des Automat Electron Syst (accepted)

  5. Birrell AD, Nelson BJ (1984) Implementing remote procedure calls. ACM Trans Comput Syst 2(1):39–59

    Article  Google Scholar 

  6. Blackburn SM, Garner R, Hoffman C, Khan AM, McKinley KS, Bentzur R, Diwan A, Feinberg D, Frampton D, Guyer SZ, Hirzel M, Hosking A, Jump M, Lee H, Moss JEB, Phansalkar A, Stefanović D, VanDrunen T, von Dincklage D, Wiedermann B (2006) The DaCapo benchmarks: Java benchmarking development and analysis. In: OOPSLA ’06: Proceedings of the 21st annual ACM SIGPLAN conference on object-oriented programing, systems, languages, and applications. ACM, New York, pp 169–190

    Chapter  Google Scholar 

  7. Borg A, Gao R, Audsley N (2006) A co-design strategy for embedded Java applications based on a hardware interface with invocation semantics. In: Proceedings of the 4th international workshop on Java technologies for real-time and embedded systems JTRES. ACM, New York, pp 58–67

    Chapter  Google Scholar 

  8. Bruneel K, Stroobandt D (2008) Automatic generation of run-time parameterizable configurations. In: Kebschull U, Platzner M, Jonas T (eds) Proceedings of the international conference on field programmable logic and applications. Kirchhoff Institute for Physics, Heidelberg, pp 361–366

    Chapter  Google Scholar 

  9. Cai L, Gajski D (2003) Transaction level modeling: an overview. In: Proceedings of the 1st IEEE/IFIP international conference on hardware/software codesign and system synthesis (CODES+ISSS). ACM, New York, pp 19–24

    Chapter  Google Scholar 

  10. Cardoso JMP, Neto HC (1999) Macro-based hardware compilation of Java bytecodes into a dynamic reconfigurable computing system. In: Proceedings of the 7th annual IEEE symposium on field-programmable custom computing machines (FCCM). IEEE Comput Soc, Los Alamitos

    Google Scholar 

  11. Chiba S (2000) Load-time structural reflection in Java. In: Proceedings of the European conference on object-oriented programming (ECOOP). LNCS, vol 1850. Springer, Berlin, pp 313–336

    Google Scholar 

  12. Chiba S, Sato Y, Tatsubori M (2003) Using HotSwap for implementing dynamic AOP systems. In: Proceedings of the 1st workshop on advancing the state-of-the-art in run-time inspection (ASARTI)

  13. De Micheli G, Gupta RK (1997) Hardware/software co-design. Proc IEEE 85(3):349–365

    Article  Google Scholar 

  14. DeGroat J, Raman A, Younis B (2003) A design project for system design with SystemC. In: Proceedings of the 2003 international conference on microelectronics systems education (MSE). IEEE Comput Soc, Los Alamitos, p 108

    Chapter  Google Scholar 

  15. Edwards M, Green P (2000) An object-oriented design method for reconfigurable computing systems. In: Proceedings of the conference on design, automation and test in Europe (DATE). ACM, New York, pp 692–696

    Chapter  Google Scholar 

  16. Eles P, Peng Z, Kuchcinski K, Doboli A (1997) System level hardware/software partitioning based on simulated annealing and tabu search. Des Autom Embed Syst 2(1):5–32

    Article  Google Scholar 

  17. Ernst R (1998) Codesign of embedded systems: Status and trends. IEEE Des Test Comput 15(2):45–54

    Article  Google Scholar 

  18. Faes Ph, Christiaens M, Buytaert D, Stroobandt D (2005) FPGA-aware garbage collection in Java. In: Proceedings of the international conference on field programmable logic and applications (FPL). IEEE Press, New York, pp 675–680

    Chapter  Google Scholar 

  19. Faes Ph, Minnaert B, Christiaens M, Bonnet E, Saeys Y, Stroobandt D, Van de Peer Y (2006) Scalable hardware accelerator for comparing DNA and protein sequences. In: InfoScale ’06: proceedings of the 1st international conference on scalable information systems. ACM, New York, p 33

    Chapter  Google Scholar 

  20. Faes Ph, Christiaens M, Stroobandt D (2007) Mobility of data in distributed hybrid computing systems. In: Proceedings of the 21st international parallel and distributed processing symposium (IPDPS). IEEE Comput Soc, Los Alamitos, p 386

    Google Scholar 

  21. Fleischmann J, Buchenrieder K, Kress R (1999) Java driven codesign and prototyping of networked embedded systems. In: Proceedings of the 36th annual design automation conference (DAC). ACM, New York, pp 794–797

    Google Scholar 

  22. Fowler M (1999) Refactoring improving the design of existing code. Addison-Wesley, Reading

    Google Scholar 

  23. Gotoh O (1982) An improved algorithm for matching biological sequences. J Mol Biol 162(3):705–708

    Article  Google Scholar 

  24. Ha Y, Vernalde S, Schaumont P, Engels M, Lauwereins R, De Man H (2002) Building a virtual framework for networked reconfigurable hardware and software objects. J Supercomput 21(2):131–144

    Article  MATH  Google Scholar 

  25. Helaihel R, Olukotun K (1997) Java as a specification language for hardware/software systems. In: Proceedings of the international conference on computer-aided design (ICCAD). IEEE Comput Soc, Los Alamitos, pp 690–697

    Chapter  Google Scholar 

  26. JSR-133: Java memory model and thread specification (2004) http://jcp.org/aboutJava/communityprocess/review/jsr133/index.html

  27. Kühn A, Huss SA (2004) Dynamically reconfigurable hardware for object-oriented processing. In: Proceedings of the international conference on parallel computing in electrical engineering (PARELEC). IEEE Comput Soc, Los Alamitos, pp 181–186

    Google Scholar 

  28. Kumfert G, Leek J, Epperly T (2007) Babel remote method invocation. In: Proceedings of the 21st international parallel and distributed processing symposium (IPDPS). IEEE Comput Soc, Los Alamitos

    Google Scholar 

  29. Lattanzi E, Gayasen A, Kandemir M, Vijaykrishnan N, Benini L, Bogliolo A (2005) Improving Java performance using dynamic method migration on FPGAs. Int J Embed Syst 1(3):228–236

    Article  Google Scholar 

  30. Lindholm T, Yellin F (1999) Java virtual machine specification, 2nd edn. Addison-Wesley, Reading. http://www.ic.uff.br/~cbraga/comp/vmspec/VMSpecTOC.doc.html

    Google Scholar 

  31. Lysecky R, Stitt G, Vahid F (2006) WARP processors. Trans Des Automat Electron Syst 11(3):659–681

    Article  Google Scholar 

  32. Maebe J, Ronsse M, De Bosschere K (2002) Diota: dynamic instrumentation, optimization and transformation of applications. In: Compendium of workshops and tutorials held in conjunction with the international conference on parallel architectures and compilation techniques (PACT)

  33. Maebe J, Buytaert D, Eeckhout L, De Bosschere K (2006) Javana: a system for building customized Java program analysis tools. ACM SIGPLAN Not 41(10):153–168

    Article  Google Scholar 

  34. Mattos JCB, Wong S, Carro L (2006) The MOLEN FemtoJava engine. In: Proceedings of the IEEE 17th international conference on application-specific systems, architectures and processors (ASAP). IEEE Comput Soc, Los Alamitos, pp 19–22

    Chapter  Google Scholar 

  35. McGhan H, O’Connor M (1998) PicoJava: A direct execution engine for Java bytecode. Computer 31(10):22–30

    Article  Google Scholar 

  36. Mignolet JY, Nollet V, Coene P, Verkest D, Vernalde S, Lauwereins R (2003) Infrastructure for design and management of relocatable tasks in a heterogeneous reconfigurable system-on-chip. In: Proceedings of the conference on design, automation and test in Europe (DATE). IEEE Comput Soc, Los Alamitos, p 10986

    Google Scholar 

  37. Niemann R, Marwedel P (1997) An algorithm for hardware/software partitioning using mixed integer linear programming. Des Autom Embed Syst 2(2):165–193

    Article  Google Scholar 

  38. Nollet V, Coene P, Verkest D, Vernalde S, Lauwereins R (2003) Designing an operating system for a heterogeneous reconfigurable SoC. In: Proceedings of the 17th international symposium on parallel and distributed processing (IPDPS). IEEE Comput Soc, Los Alamitos, p 174.1

    Google Scholar 

  39. Pugh W (1999) Fixing the Java memory model. In: Proceedings of the ACM conference on Java Grande (JAVA). ACM, New York, pp 89–98

    Chapter  Google Scholar 

  40. Smith TF, Waterman MS (1981) Identification of common molecular subsequences. J Mol Biol 147(1):195–197

    Article  Google Scholar 

  41. Standard Performance Evaluation Corporation (1998) Java virtual machine benchmarks (SPECjvm1998). http://www.spec.org/jvm98/

  42. Standard Performance Evaluation Corporation (2008) Java virtual machine benchmarks (SPECjvm2008). http://www.spec.org/jvm2008/

  43. Sun Microsystems (2002) The Java HotSpot virtual machine, version 1.4.1. Technical report

  44. SystemC: user’s Guide Update for SystemC 2.0.1 (2002). Available from the Open SystemC Initiative (OSCI) at http://www.systemc.org/

  45. SystemVerilog: Accellera’s extensions to Verilog, version 3.1. http://www.systemverilog.org/

  46. Uhrig S, Maier S, Kuzmanov G, Ungerer T (2006) Coupling of a reconfigurable architecture and a multithreaded processor core with integrated real-time scheduling. In: Proceedings of the 20th international parallel and distributed processing symposium (IPDPS). IEEE Comput Soc, Los Alamitos

    Google Scholar 

  47. Vassiliadis S, Wong S, Gaydadjiev G, Bertels K, Kuzmanov G, Panainte EM (2004) The MOLEN polymorphic processor. IEEE Trans Comput 53(11):1363–1375

    Article  Google Scholar 

Download references

Author information

Authors and Affiliations

Authors

Corresponding author

Correspondence to Dirk Stroobandt.

Rights and permissions

Reprints and permissions

About this article

Cite this article

Faes, P., Bertels, P., Van Campenhout, J. et al. Using method interception for hardware/software co-development. Des Autom Embed Syst 13, 223–243 (2009). https://doi.org/10.1007/s10617-009-9040-8

Download citation

  • Received:

  • Accepted:

  • Published:

  • Issue Date:

  • DOI: https://doi.org/10.1007/s10617-009-9040-8

Keywords

Navigation