Abstract
An allocation algorithm at the bit-level specially suited for data dominated applications is presented. In addition to classical low power methods, it implements novel design strategies to reduce power consumption. These new features consist of the successive transformation of specification operations until a circuit implementation with minimum power consumption in functional and storage units is obtained. Thus, some of the specification operations are executed over a set of narrower functional units, linked by some glue logic to propagate partial results and carry signals as necessary. Due to the operation transformations performed, the types of the functional units may be different from those of the operations executed over them. Experimental results show a substantial power consumption reduction in the implementations obtained, compared to other low power algorithms. In addition, circuit areas are dramatically smaller.
Supported by Spanish Government Grant CICYT TIC-2002/750
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Molina, M.C., Sautua, R.R., Mendías, J.M., Hermida, R. (2003). Bit-Level Allocation for Low Power in Behavioural High-Level Synthesis. In: Chico, J.J., Macii, E. (eds) Integrated Circuit and System Design. Power and Timing Modeling, Optimization and Simulation. PATMOS 2003. Lecture Notes in Computer Science, vol 2799. Springer, Berlin, Heidelberg. https://doi.org/10.1007/978-3-540-39762-5_68
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DOI: https://doi.org/10.1007/978-3-540-39762-5_68
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