Abstract
Developing a new microchip for an embedded application these days means that the engineer has to take many different design options into account. Evaluating the different processor cores regarding their runtime for a certain algorithm requires simulation tools which make emulation feasible. They come in two flavors: Cycle and instruction accurate simulation. The first one offers a high accuracy regarding the estimated time but is very slow. The second one offers a high simulation speed but only provides a very imprecise estimation of the real runtime. This paper shows a new approach that allows to combine these kinds of simulation to increase the exactness of the estimated time while limiting the additionally required simulation time.
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This work is supported by the Bavarian Research Foundation (BFS) as part of their research project “FORMUS3IC”.
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Rachuj, S., Herglotz, C., Reichenbach, M., Kaup, A., Fey, D. (2018). A Hybrid Approach for Runtime Analysis Using a Cycle and Instruction Accurate Model. In: Berekovic, M., Buchty, R., Hamann, H., Koch, D., Pionteck, T. (eds) Architecture of Computing Systems – ARCS 2018. ARCS 2018. Lecture Notes in Computer Science(), vol 10793. Springer, Cham. https://doi.org/10.1007/978-3-319-77610-1_7
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DOI: https://doi.org/10.1007/978-3-319-77610-1_7
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