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Link to original content: https://link.springer.com/doi/10.1007/s11554-011-0215-8
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A multi-processor NoC-based architecture for real-time image/video enhancement

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Abstract

The paper presents a multi-processor architecture for real-time and low-power image and video enhancement applications. Differently from other state-of-the-art parallel architectures the proposed solution is composed of heterogeneous tiles. The tiles have computational and memory capabilities, support different algorithmic classes and are connected by a novel Network-on-Chip (NoC) infrastructure. The proposed packet-switched data transfer scheme avoids communication bottlenecks when more tiles are working concurrently. The functional performances of the NoC-based multi-processor architecture are assessed by presenting the achieved results when the platform is programmed to support different enhancement algorithms for still images or videos. The implementation complexity of the NoC-based multi-tile platform, integrated in 65 nm CMOS technology, is reported and discussed.

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Acknowledgment

This work has been partially supported by the EU integrated project SHAPES of the 6th framework programme in collaboration with STMicroelectronics, particularly the group of Dr. M. Coppola (AST, Grenoble).

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Authors and Affiliations

  1. Department of Information Engineering, University of Pisa, via G. Caruso 16, 56122, Pisa, Italy

    Sergio Saponara & Luca Fanucci

  2. Consorzio Pisa Ricerche scarl, C.so Italia 116, 56125, Pisa, Italy

    Esa Petri

Authors
  1. Sergio Saponara
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  2. Luca Fanucci
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  3. Esa Petri
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Correspondence to Sergio Saponara.

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Saponara, S., Fanucci, L. & Petri, E. A multi-processor NoC-based architecture for real-time image/video enhancement. J Real-Time Image Proc 8, 111–125 (2013). https://doi.org/10.1007/s11554-011-0215-8

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  • DOI: https://doi.org/10.1007/s11554-011-0215-8

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