iBet uBet web content aggregator. Adding the entire web to your favor.
Link to original content: https://doi.org/10.1587/elex.18.20210224
2021 Volume 18 Issue 16 Pages 20210224
This paper presents a serial multi-channel front-end readout ASIC with a novel architecture and timing control scheme, for the application of flat-panel X-ray, linear detectors and other similar fields. The proposed architecture features the single multi-range selectable integrator, two multiplexed correlated double sampling (CDS) circuits, and the differential buffer output. With the proposed sequential timing control, each channel can output data to the corresponding CDS circuit with no delay when the integration state is ended. So, the channel circuit is simplified. In addition, the proposed architecture and timing control scheme enables the readout ASICs to be cascaded for more channels with tunable conversion rates. To verify the proposed architecture and timing control scheme, a 32-channel readout ASIC was fabricated in TSMC 250nm mixed CMOS signal process. The die size is 2.8 × 2mm2. At room temperature, the measured equivalent input noise (EIN) is 25ppm of full-scale value (FSR) with an integration range of 12pC. The measured integral non-linearity is less than 0.04%, and the average power consumption is 2mW per channel. When four ASICs are cascaded, 128 channels are achieved, and a conversion rate over than 30kS/s is measured.
