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Link to original content: https://doi.org/10.1145/3132402.3132433

Probabilistic replacement strategies for improving the lifetimes of NVM-based caches | Proceedings of the International Symposium on Memory Systems

research-article

Probabilistic replacement strategies for improving the lifetimes of NVM-based caches

Authors:

Elizabeth Reed,

Alaa R. Alameldeen,

Patrick StoltAuthors Info & Claims

MEMSYS '17: Proceedings of the International Symposium on Memory Systems

Pages 166 - 176

https://doi.org/10.1145/3132402.3132433

Published: 02 October 2017 Publication History

Abstract

Non-volatile memory (NVM) technologies present an opportunity to improve area efficiency and reduce energy consumption throughout the memory hierarchy. However, write endurance can hinder the adoption of NVM in lower-level caches. With an estimated write endurance of one trillion write cycles, Spin-Torque Transfer RAM (STT-RAM) is a more likely candidate for application as an L2 cache than Resistive RAM (ReRAM) or Phase-Change Memory (PCM). In resource-constrained systems where aggressive wear-leveling techniques cannot be applied, light-weight alternatives may be necessary to extend the lifetime of the cache.

In this paper, we propose and evaluate a hybrid-random replacement policy as a low-overhead approach to wear-leveling to improve the lifetime of a large non-volatile memory L2 cache. We investigate another probabilistic mechanism that utilizes approximate counters as an alternative method of injecting random events in the eviction stream. We show that our hybrid-random policy extends the lifetime of an NVM L2 cache by 0.5 to 16 years across many benchmarks over an LRU-replacement baseline. Our approximate counter approach further extends the lifetime by 1.7 to 19 years over the baseline but incurs a higher overhead.

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Cited By

Kargar SNawab F(2022)Challenges and future directions for energy, latency, and lifetime improvements in NVMsDistributed and Parallel Databases10.1007/s10619-022-07421-x41:3(163-189)Online publication date: 21-Sep-2022
https://doi.org/10.1007/s10619-022-07421-x
Kuan KAdegbija T(2020)Energy-Efficient Runtime Adaptable L1 STT-RAM Cache DesignIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems10.1109/TCAD.2019.291292039:6(1328-1339)Online publication date: Jun-2020
https://doi.org/10.1109/TCAD.2019.2912920
Saraf PMutyam M(2019)Endurance enhancement of write-optimized STT-RAM cachesProceedings of the International Symposium on Memory Systems10.1145/3357526.3357538(101-113)Online publication date: 30-Sep-2019
https://dl.acm.org/doi/10.1145/3357526.3357538
Show More Cited By

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MEMSYS '17: Proceedings of the International Symposium on Memory Systems

October 2017

409 pages

ISBN:9781450353359

DOI:10.1145/3132402

General Chair:
Bruce Jacob
University of Maryland

Copyright © 2017 ACM.

Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]

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Published: 02 October 2017

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MEMSYS 2017

MEMSYS 2017: The International Symposium on Memory Systems, 2017

October 2 - 5, 2017

Virginia, Alexandria

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Cited By

Kargar SNawab F(2022)Challenges and future directions for energy, latency, and lifetime improvements in NVMsDistributed and Parallel Databases10.1007/s10619-022-07421-x41:3(163-189)Online publication date: 21-Sep-2022
https://doi.org/10.1007/s10619-022-07421-x
Kuan KAdegbija T(2020)Energy-Efficient Runtime Adaptable L1 STT-RAM Cache DesignIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems10.1109/TCAD.2019.291292039:6(1328-1339)Online publication date: Jun-2020
https://doi.org/10.1109/TCAD.2019.2912920
Saraf PMutyam M(2019)Endurance enhancement of write-optimized STT-RAM cachesProceedings of the International Symposium on Memory Systems10.1145/3357526.3357538(101-113)Online publication date: 30-Sep-2019
https://dl.acm.org/doi/10.1145/3357526.3357538
Hameed FCastrillon J(2019)A Novel Hybrid DRAM/STT-RAM Last-Level-Cache Architecture for Performance, Energy, and Endurance EnhancementIEEE Transactions on Very Large Scale Integration (VLSI) Systems10.1109/TVLSI.2019.291838527:10(2375-2386)Online publication date: Oct-2019
https://doi.org/10.1109/TVLSI.2019.2918385
Kuan KAdegbija T(2019)Energy and Performance Analysis of STTRAM Caches for Mobile Applications2019 IEEE 13th International Symposium on Embedded Multicore/Many-core Systems-on-Chip (MCSoC)10.1109/MCSoC.2019.00044(257-264)Online publication date: Oct-2019
https://doi.org/10.1109/MCSoC.2019.00044

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