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Leakage control with efficient use of transistor stacks in single threshold CMOS

Authors:

Mark C. Johnson,

Dinesh Somasekhar,

Kaushik RoyAuthors Info & Claims

DAC '99: Proceedings of the 36th annual ACM/IEEE Design Automation Conference

Pages 442 - 445

https://doi.org/10.1145/309847.309976

Published: 01 June 1999 Publication History

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Cited By

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Tripathi B(2023)Subthreshold TransistorsAdvanced Ultra Low‐Power Semiconductor Devices10.1002/9781394167647.ch1(1-27)Online publication date: 27-Oct-2023
https://doi.org/10.1002/9781394167647.ch1
Wang TCui XLiao KLiao NYu DCui X(2018)Design of Low-Power High-Performance FinFET Standard CellsCircuits, Systems, and Signal Processing10.1007/s00034-017-0646-y37:5(1789-1806)Online publication date: 1-May-2018
https://dl.acm.org/doi/10.1007/s00034-017-0646-y
Naeini MDass SOoi CYoneda TInoue M(2017)An integrated DFT solution for power reduction in scan test applications by low power gating scan cellIntegration, the VLSI Journal10.1016/j.vlsi.2016.12.00957:C(108-124)Online publication date: 1-Mar-2017
https://dl.acm.org/doi/10.1016/j.vlsi.2016.12.009
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Index Terms

Leakage control with efficient use of transistor stacks in single threshold CMOS
1. Hardware
  1. Electronic design automation
    1. Physical design (EDA)

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Published In

DAC '99: Proceedings of the 36th annual ACM/IEEE Design Automation Conference

June 1999

1000 pages

ISBN:1581131097

DOI:10.1145/309847

Editor:
Mary Jane Irwin

Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]

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Association for Computing Machinery

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Publication History

Published: 01 June 1999

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DAC99: The 36th ACM/IEEE-CAS/EDAC Design Automation Conference

June 21 - 25, 1999

Louisiana, New Orleans, USA

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DAC '99 Paper Acceptance Rate 154 of 451 submissions, 34%;

Overall Acceptance Rate 1,770 of 5,499 submissions, 32%

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Cited By

View all

Tripathi B(2023)Subthreshold TransistorsAdvanced Ultra Low‐Power Semiconductor Devices10.1002/9781394167647.ch1(1-27)Online publication date: 27-Oct-2023
https://doi.org/10.1002/9781394167647.ch1
Wang TCui XLiao KLiao NYu DCui X(2018)Design of Low-Power High-Performance FinFET Standard CellsCircuits, Systems, and Signal Processing10.1007/s00034-017-0646-y37:5(1789-1806)Online publication date: 1-May-2018
https://dl.acm.org/doi/10.1007/s00034-017-0646-y
Naeini MDass SOoi CYoneda TInoue M(2017)An integrated DFT solution for power reduction in scan test applications by low power gating scan cellIntegration, the VLSI Journal10.1016/j.vlsi.2016.12.00957:C(108-124)Online publication date: 1-Mar-2017
https://dl.acm.org/doi/10.1016/j.vlsi.2016.12.009
Shin YSeomun JChoi KSakurai T(2010)Power gatingACM Transactions on Design Automation of Electronic Systems10.1145/1835420.183542115:4(1-37)Online publication date: 7-Oct-2010
https://dl.acm.org/doi/10.1145/1835420.1835421
Singh HRao RAgarwal KSylvester DBrown R(2010)Dynamically pulsed MTCMOS with bus encoding for reduction of total power and crosstalk noiseIEEE Transactions on Very Large Scale Integration (VLSI) Systems10.1109/TVLSI.2009.203129018:1(166-170)Online publication date: 1-Jan-2010
https://dl.acm.org/doi/10.1109/TVLSI.2009.2031290
Kao WChuang WLin HLi JManquinho V(2010)DFT and minimum leakage pattern generation for static power reduction during test and burn-inIEEE Transactions on Very Large Scale Integration (VLSI) Systems10.1109/TVLSI.2008.201104818:3(392-400)Online publication date: 1-Mar-2010
https://dl.acm.org/doi/10.1109/TVLSI.2008.2011048
Saemrow HCornelius CSill FTockhorn ATimmermann DSaraiva IRibas RPlett C(2009)Twin logic gatesProceedings of the 22nd Annual Symposium on Integrated Circuits and System Design: Chip on the Dunes10.1145/1601896.1601960(1-6)Online publication date: 31-Aug-2009
https://dl.acm.org/doi/10.1145/1601896.1601960
Xu HJone WVemuri RNassif SRoychowdhury J(2008)Accurate energy breakeven time estimation for run-time power gatingProceedings of the 2008 IEEE/ACM International Conference on Computer-Aided Design10.5555/1509456.1509501(161-168)Online publication date: 10-Nov-2008
https://dl.acm.org/doi/10.5555/1509456.1509501
Cheng LChen DWong M(2008)A fast simultaneous input vector generation and gate replacement algorithm for leakage power reductionACM Transactions on Design Automation of Electronic Systems10.1145/1344418.134443013:2(1-15)Online publication date: 23-Apr-2008
https://dl.acm.org/doi/10.1145/1344418.1344430
Hempstead MWei GBrooks DHong SWolf WFlautner KKim T(2006)Architecture and circuit techniques for low-throughput, energy-constrained systems across technology generationsProceedings of the 2006 international conference on Compilers, architecture and synthesis for embedded systems10.1145/1176760.1176805(368-378)Online publication date: 22-Oct-2006
https://dl.acm.org/doi/10.1145/1176760.1176805
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Estimation of standby leakage power in CMOS circuits considering accurate modeling of transistor stacks

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