Abstract
Mainstream processors implement the instruction scheduler using a monolithic CAM-based issue queue (IQ), which consumes increasingly high energy as its size scales. In particular, its instruction wakeup logic accounts for a major portion of the consumed energy. Our study shows that instructions with 2 non-ready operands (called 2OP instructions) are in small percentage, but tend to spend long latencies in the IQ. They can be effectively shelved in a small RAM-based waiting instruction buffer (WIB) and steered into the IQ at appropriate time. With this two-level shelving ability, half of the CAM tag comparators are eliminated in the IQ, which significantly reduces the energy of wakeup operation. In addition, we propose an adaptive banking scheme to downsize the IQ and reduce the bit-width of tag comparators. Experiments indicate that for an 8-wide issue superscalar or SMT processor, the energy consumption of the instruction scheduler can be reduced by 67%. Furthermore, the new design has potentially faster scheduler clock speed while maintaining close IPC to the monolithic scheduler design. Compared with the previous work on eliminating tags through prediction, our design is superior in terms of both energy reduction and SMT support.
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Supported by the National High Technology Development 863 Program of China under Grant No. 2004AA1Z1010.
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Zhao, YL., Li, XF., Tong, D. et al. An Energy-Efficient Instruction Scheduler Design with Two-Level Shelving and Adaptive Banking. J Comput Sci Technol 22, 15–24 (2007). https://doi.org/10.1007/s11390-007-9001-2
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DOI: https://doi.org/10.1007/s11390-007-9001-2