iBet uBet web content aggregator. Adding the entire web to your favor.
iBet uBet web content aggregator. Adding the entire web to your favor.



Link to original content: https://doi.org/10.1007/s11042-016-3736-0
Design and development of new reconfigurable architectures for LSB/multi-bit image steganography system | Multimedia Tools and Applications Skip to main content
Springer Nature Link
Log in

Design and development of new reconfigurable architectures for LSB/multi-bit image steganography system

  • Published:
Multimedia Tools and Applications Aims and scope Submit manuscript

Abstract

The most crucial task in real-time processing of steganography algorithms is to reduce the computational delay and increase the throughput of a system. This critical issue is effectively addressed by implementing steganography methods in reconfigurable hardware. In the proposed framework, a new high-speed reconfigurable architectures have been designed for Least Significant Bit (LSB) or multi-bit based image steganography algorithm that suits Field Programmable Gate Arrays (FPGAs) or Application Specific Integrated Circuits (ASICs) implementation. The architectures are designed and instantiated to implement the complete steganography system. The proposed system is competent enough to provide larger throughput, since high degrees of pipelining and parallel operations are incorporated at the module level. The evolved architectures are realized in Xilinx Virtex-II Pro XC2V500FG256-6 FPGA device using Register Transfer Level (RTL) compliant Verilog coding and has the capacity to work in real-time at the rate of 183.48 frames/second. Prior to the FPGA/ASIC implementation, the proposed steganography system is simulated in software to validate the concepts intended to implement. The hardware implemented algorithm is tested by varying embedding bit size as well as the resolution of a cover image. As it is clear from the results presented that the projected framework is superior in speed, area and power consumption compared to other researcher’s method.

This is a preview of subscription content, log in via an institution to check access.

Access this article

Log in via an institution

Subscribe and save

Springer+ Basic
$34.99 /Month
  • Get 10 units per month
  • Download Article/Chapter or eBook
  • 1 Unit = 1 Article or 1 Chapter
  • Cancel anytime
Subscribe now

Buy Now

Price excludes VAT (USA)
Tax calculation will be finalised during checkout.

Instant access to the full article PDF.

Institutional subscriptions

Fig. 1
Fig. 2
Fig. 3
Fig. 4
Fig. 5
Fig. 6
Fig. 7
Fig. 8
Fig. 9
Fig. 10
Fig. 11
Fig. 12
Fig. 13
Fig. 14
Fig. 15
Fig. 16
Fig. 17
Fig. 18
Fig. 19
Fig. 20
Fig. 21
Fig. 22

Similar content being viewed by others

References

  1. Al-Haj AM (2010) Advanced techniques in multimedia watermarking: image, video and audio applications. IGI Global

  2. Amirtharajan R, Rayappan JBB (2012) An intelligent chaotic embedding approach to enhance stego image quality. Inform Sci 193:115–124

    Article  Google Scholar 

  3. Cao Y, Zhao X, Feng D, Sheng R (2011) Video steganography with perturbed motion estimation. In: Information hiding. Springer 193–207

  4. Chang CC, Lin CC, Tseng CS, Tai WL (2007) Reversible hiding in DCT-based compressed images. Inform Sci 177(13):2768–2786

    Article  Google Scholar 

  5. Cheddad A, Condell J, Curran K, Mc Kevitt P (2010) Digital image steganography: survey and analysis of current methods. Signal Process 90(3):727–752

    Article  MATH  Google Scholar 

  6. Cox IJ, ML Miller, Bloom JA (2007) Digital watermarking and steganography. MorGan Kaufmann

  7. Crandall R (1998) Some notes on steganography. Posted on steganography mailing list

  8. Fan L, Gao T, Yang Q, Cao Y (2011) An extended matrix encoding algorithm for steganography of high embedding efficiency. Comput Electr Eng 37(6):973–981

    Article  Google Scholar 

  9. Fan L, Gao T, Cao Y (2013) Improving the embedding efficiency of weight matrix-based steganography for grayscale images. Comput Electr Eng 39(3):873–881

    Article  Google Scholar 

  10. Fan L, Gao T, Chang CC (2013) Mathematical analysis of extended matrix coding for steganography. In: Sensor Network Security Technology and Privacy Communication System (SNS & PCS). IEEE Int Conf 156–160

  11. Genovese M, Bifulco P, De Caro D, Napoli E, Petra N, Romano M, Cesarelli M, Strollo A (2015) Hardware implementation of a spatio-temporal average filter for real-time denoising of fluoroscopic images. Integr VLSI J 49:114–124

    Article  Google Scholar 

  12. Gomez-Hernandez E, Feregrino-Uribe C, Cumplido R (2008) FPGA hardware architecture of the steganographic context technique. In: Electronics, Communications and Com- puters, 2008. CONIELECOMP 2008. 18th Int Conf IEEE 123–128

  13. Hemalatha R, Santhiyakumari N, Suresh S (2015) Implementation of medical image segmentation using virtex FPGA kit. In: International Conference on Signal Processing and Communication Engineering Systems (SPACES-2015). IEEE 358–362

  14. Hines GD, Rahman Z-U, Jobson DJ, Woodell GA (2004) DSP implementation of the retinex image enhancement algorithm. In: Defense and security. Int Soc Opt Photon: 13–24

  15. Hussain M, Hussain M (2013) A survey of image steganography techniques

  16. Kipper G (2003) Investigator’s guide to steganography. CRC Press

  17. Mohd BJ, Abed S, Al-Hayajneh T, Alouneh S (2012) FPGA hardware of the LSB steganography method. In: Computer, Information and Telecommunication Systems (CITS). IEEE Int Conf 1–4

  18. Ntalianis KS, Doulamis AD, Doulamis ND, Kollias SD (2002) A robust steganographic wavelet based system for resistant message hiding under error prone net- works. In: Multimedia and expo, 2002. ICME’02. Proc IEEE Int Conf 2:561–564

  19. Ntalianis K, Tsapatsoulis N, Drigas A (2011) Video-object oriented biometrics hiding for user authentication under error-prone transmissions. EURASIP J Inf Secur

  20. Paul G, Davidson I, Mukherjee I, Ravi SS (2016) Keyless dynamic optimal multi-bit image steganography using energetic pixels. Multimedia Tools Appl 1–27

  21. Rajagopalan S, Prabhakar PJ, Kumar MS, Nikhil N, Upadhyay HN, Rayappan J, Amirtharajan R (2014) MSB based embedding with integrity: an adaptive RGB stego on FPGA platform. Inf Technol J 13:1945–1952

    Article  Google Scholar 

  22. Shah NN, Dalal UD (2015) Hardware efficient double diamond search block matching algorithm for fast video motion estimation. J Sig Process Syst 1–21

  23. Tseng YC, Chen YY, Pan HK (2002) A secure data hiding scheme for binary images. IEEE Trans Commun 50(8):1227–1231

    Article  Google Scholar 

  24. Upadhyay HN, Rayappan JBB (2012) Survey and analysis of hardware cryptographic and steganographic systems on FPGA. J Appl Sci 12(3):201–210

    Article  Google Scholar 

  25. Wang K, Lu ZM, Hu YJ (2013) A high capacity lossless data hiding scheme for JPEG images. J Syst Softw 86(7):1965–1975

    Article  Google Scholar 

  26. Xuan G, Shi YQ, Ni Z, Chai P, Cui X, Tong X (2007) Reversible data hiding for JPEG images based on histogram pairs. In: Image analysis and recognition. Springer 715–727

  27. Yan C, Zhang Y, Xu J, Dai F, Li L, Dai Q, Wu F (2014) A highly parallel frame-work for HEVC coding unit partitioning tree decision on many-core processors. IEEE Signal Process Lett 21(5):573–576

    Article  Google Scholar 

  28. Yan C, Zhang Y, Xu J, Dai F, Zhang J, Dai Q, Wu F (2014) Efficient parallel framework for HEVC motion estimation on many-core processors. IEEE Trans Circuits Syst Video Technol 24(12):2077–2089

    Article  Google Scholar 

  29. Zhu J, Wang RD, Li J, Yan DQ (2011) A Huffman coding section-based steganography for AAC audio. Inf Technol J 10(10):1983–1988

    Article  Google Scholar 

Download references

Author information

Authors and Affiliations

  1. Department of Electronics and Communication Engineering, JSS Academy of Technical Education, Bengaluru, India

    K. Sathish Shet

  2. Department of Telecommunication Engineering, Dayananda Sagar College of Engineering, Bengaluru, India

    A. R. Aswath

  3. Department of Electronics and Communication Engineering, BMS Institute of Technology and Management, Bengaluru, India

    M. C. Hanumantharaju

  4. Department of Electrical Engineering & Automation, Aalto University School of Electrical Engineering, Espoo, Finland

    Xiao-Zhi Gao

Authors
  1. K. Sathish Shet
    View author publications

    You can also search for this author in PubMed Google Scholar

  2. A. R. Aswath
    View author publications

    You can also search for this author in PubMed Google Scholar

  3. M. C. Hanumantharaju
    View author publications

    You can also search for this author in PubMed Google Scholar

  4. Xiao-Zhi Gao
    View author publications

    You can also search for this author in PubMed Google Scholar

Corresponding author

Correspondence to M. C. Hanumantharaju.

Rights and permissions

Reprints and permissions

About this article

Check for updates. Verify currency and authenticity via CrossMark

Cite this article

Sathish Shet, K., Aswath, A.R., Hanumantharaju, M.C. et al. Design and development of new reconfigurable architectures for LSB/multi-bit image steganography system. Multimed Tools Appl 76, 13197–13219 (2017). https://doi.org/10.1007/s11042-016-3736-0

Download citation

  • Received:

  • Revised:

  • Accepted:

  • Published:

  • Issue Date:

  • DOI: https://doi.org/10.1007/s11042-016-3736-0

Keywords

Search

Navigation