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Link to original content: https://doi.org/10.1007/s10710-011-9137-2
Accelerating floating-point fitness functions in evolutionary algorithms: a FPGA-CPU-GPU performance comparison | Genetic Programming and Evolvable Machines Skip to main content
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Accelerating floating-point fitness functions in evolutionary algorithms: a FPGA-CPU-GPU performance comparison

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Abstract

Many large combinatorial optimization problems tackled with evolutionary algorithms often require very high computational times, usually due to the fitness evaluation. This fact forces programmers to use clusters of computers, a computational solution very useful for running applications of intensive calculus but having a high acquisition price and operation cost, mainly due to the Central Processing Unit (CPU) power consumption and refrigeration devices. A low-cost and high-performance alternative comes from reconfigurable computing, a hardware technology based on Field Programmable Gate Array devices (FPGAs). The main objective of the work presented in this paper is to compare implementations on FPGAs and CPUs of different fitness functions in evolutionary algorithms in order to study the performance of the floating-point arithmetic in FPGAs and CPUs that is often present in the optimization problems tackled by these algorithms. We have taken advantage of the parallelism at chip-level of FPGAs pursuing the acceleration of the fitness functions (and consequently, of the evolutionary algorithms) and showing the parallel scalability to reach low cost, low power and high performance computational solutions based on FPGA. Finally, the recent popularity of GPUs as computational units has moved us to introduce these devices in our performance comparisons. We analyze performance in terms of computation times and economic cost.

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References

  1. S. Hauck, A. DeHon (eds.), Reconfigurable Computing, The Theory and Practice of FPGA-Based Computation (Morgan Kaufmann, Los Altos, 2008)

    MATH  Google Scholar 

  2. C. Maxfield, The Design Warrior’s Guide to FPGAs: Devices, Tools and Flows (Elsevier, Amsterdam, 2004)

    Google Scholar 

  3. D. Buell, T. El-Ghazawi, K. Gaj, V. Kindratenko, High-performance reconfigurable computing. Computer 40, 23–27 (2007)

    Article  Google Scholar 

  4. M. Gokhale, P. Graham, Reconfigurable Computing: Accelerating Computation with Field-Programmable Gate Arrays (Springer, Berlin, 2005)

    Google Scholar 

  5. Z. Michalewicz, D.B. Fogel, How to Solve It: Modern Heuristics (Springer, Berlin, 2004)

    MATH  Google Scholar 

  6. C.W. Ahn, Advances in Evolutionary Algorithms (Springer, Berlin, 2006)

    MATH  Google Scholar 

  7. J. Dreo, A. Petrowski, P. Siarry, E. Taillard, Metaheuristics for Hard Optimization (Springer, Berlin, 2006)

    MATH  Google Scholar 

  8. K. Glette, J. Torresen, A Flexible On-Chip Evolution System Implemented on a Xilinx Virtex-II Pro Device, in Evolvable Systems: From Biology to Hardware, ed. by J. Moreno, J. Madrenas, J. Cosp (Springer, Berlin, 2005), pp. 66–75

    Chapter  Google Scholar 

  9. R. Baraglia, et al., A parallel compact genetic algorithm for Multi-FPGA partitioning, in 9th Euromicro Workshop on Parallel and Distributed Processing (PDP ‘01), pp. 113–120

  10. H.E. Mostafa et al., Hardware implementation of genetic algorithm on FPGA, in 21th National Radio Science Conference (NRSC2004) (2004), pp. C9-1-9

  11. H. Emam et al., Introducing an FPGA based—genetic algorithms in the applications of blind signals separation, in The 3rd IEEE International Workshop on System-on-Chip for Real-Time Applications (IWSOC’03) (2003), pp. 123–127

  12. J. Wang, C.H. Lee, Complete FPGA Implemented Evolvable Image Filters, in MICAI 2006: Advances in Artificial Intelligence, ed. by A. Gelbukh, C.A. Reyes-Garcia (Springer, Berlin/Heidelberg, 2006), pp. 767–777

    Chapter  Google Scholar 

  13. M.A. Vega, R. Gutiérrez, J.M. Ávila, J.M. Sánchez, and J.A. Gómez, Genetic algorithms using parallelism and FPGAs: the tsp as case study. In IEEE international conference on parallel processing, 1st workshop on parallel bioinspired algorithms (IEEE Computer Society, Oslo, Norway, 2005), pp. 573–579

  14. F.C. Allaire, M. Tarbouchi, G. Labonté, G. Fusina, FPGA implementation of genetic algorithm for UAV real-time path planning. J. Intell. Robot. Syst 54, 495–510 (2009)

    Article  Google Scholar 

  15. John R. Koza, Stephen L. Bade, Martin A. Keane, Jeffrey L. Hutchings, Rapidly reconfigurable field-programmable gate arrays for accelerating fitness evaluation in genetic programming, Genetic Programming Conference (1997), pp. 121–131

  16. Q. Qiu, D. Burns, P. Mukre, Q. Wu, Hardware acceleration of multi-deme genetic algorithm for the application of DNA codeword, in 9th annual conference on Genetic and evolutionary computation (2007), pp. 1349–1356

  17. K.D. Underwood, K.S. Hemmert, Closing the gap: CPU and FPGA Trends in sustainable floating-point BLAS performance, in 12th Annual IEEE Symposium on Field-Programmable Custom Computing Machines (FCCM’04) (2004), IEEE Computer Society

  18. B. Sukhwani, M. Chiu, M.A. Khan, and M.C. Herbordt, Effective floating point application on FPGAs: examples from molecular modeling, in High Performance Embedded Computing (HPEC 2009) (2009), Lexington, MA, USA

  19. C. Pedraza, J. Castillo, J. Martínez, P. Huerta, J. Bosque, and J. Cano (2010, March). Genetic algorithm for Boolean minimization in an FPGA cluster. J. Supercomput. [Online]. Available: http://www.springerlink.com/content/654l37k832678t60

  20. F. Belleti et al., Ianus: An Adaptive FPGA Computer. Comput Sci. Eng. 8, 41–49 (2006)

    Article  Google Scholar 

  21. C. Patterson, S. Ellingson, B. Martin, K. Deshpande, J. Simonetti, M. Kavic, and S. Cutchin, Searching for Transient Pulses with the ETA Radio Telescope, ACM Transactions on Reconfigurable Technology and Systems1 (2009), pp. 1–20

  22. M. Yoshimi, Y. Nishikawa, M. Miki, T. Hiroyasu, H. Amano, and O. Mencer, A performance evaluation of CUBE: one-dimensional 512 FPGA cluster, in Reconfigurable Computing: Architectures, Tools and Applications (Ed: Springer, 2009), pp. 372–381

  23. V. Sriram, M. Leeser (eds.), FPGA Supercomputing Platforms, Architectures, and Techniques for Accelerating Computationally Complex Algorithms (Hindawi, Cairo, 2009)

    Google Scholar 

  24. R. Hamming, Error detecting and error correcting codes. Bell Syst. Tech. J 29, 147–160 (1950)

    MathSciNet  Google Scholar 

  25. K. Dontas, K.D. Jong, Discovery of maximal distance codes using genetic algorithms, in 2nd International IEEE Conference on Tools for Artificial Intelligence (IEEE Computer Society, 1990), pp. 905–811

  26. A.E. Gamal, L. Hemachandra, I. Shperling, V. Wei, Using simulated annealing to design good codes. IEEE Trans. Inf. Theory 33, 116–123 (1987)

    Article  Google Scholar 

  27. E. Alba, J.F. Chicano, Solving the error correcting code problem with parallel hybrid heuristics (ACM Symposium on Applied Computing, ACM, Nicosia, Cyprus, 2004), pp. 985–989

    Google Scholar 

  28. P. Calegari, F. Guidec, P. Kuonen, D. Kobler, Parallel island-based genetic algorithm for radio network design. J. Parallel Distrib. Comput. 47, 86–90 (1997)

    Article  Google Scholar 

  29. P. Calegari, F. Guidec, P. Kuonen, Combinatorial optimization algorithms for radio network planning. J. Theor. Comput. Sci. 263, 235–265 (2001)

    Article  MathSciNet  MATH  Google Scholar 

  30. E. Alba, Evolutionary Algorithms for Optimal Placement of Antennae in Radio Network Design (IEEE NIDISC, IEEE, Santa Fe, New Mexico, USA, 2004), pp. 168-174

  31. S. Khuri, T. Chiu, Heuristic algorithms for the terminal assignment problem (ACM Symposium on Applied Computing, 1997), pp. 245–251

  32. P. Thompson, D.E. Cox, J.B. Hastings, Rietveld refinement of Debye-Scherrer synchrotron X-ray data from Al2O3. J. Appl. Cryst 20, 79–83 (1987)

    Article  Google Scholar 

  33. T.H.D. Keijser, E.J. Mittemeijer, H.C.F. Rozendaal, The determination of crystallite-size and lattice-strain parameters in conjunction with the profile-refinement method for the determination of crystal structures. J. Appl. Cryst. 16, 309–316 (1983)

    Article  Google Scholar 

  34. S. Enzo, G. Fagherazzi, A. Benedetti, S. Polizzi, A profile-fitting procedure for analysis of broadened X-ray diffraction peaks. I. Methodology. J. Appl. Cryst 21, 536–542 (1988)

    Article  Google Scholar 

  35. F. Sánchez-Bajo, F.L. Cumbrera, The use of the Pseudo-Voigt function in the variance method of X-ray line-broadening analysis. J. Appl. Cryst. 30, 427–430 (1997)

    Article  Google Scholar 

  36. J. Gomez-Pulido, Hardware Designs for Fitness Performance (2010) Available: http://arco.unex.es/fitness_performance

  37. K. Ramamritham, K. Arya, System software for embedded applications, in 17th International Conference on VLSI Design (2004), pp. 22–24

  38. V. Kindratenko, D. Pointer, D. Raila, C. Steffen, Comparing CPU and FPGA Application performance, Tech. Report, 2006

  39. D.B. Thomas, L. Howes, W. Luk, A Comparison of CPUs, GPUs, FPGAs and Massively parallel processor arrays for random number generation, in ACM/SIGDA International Symposium on Field Programmable Gate Arrays (ACM New York, NY, USA, Monterey, California, USA, 2009), pp. 63–72

  40. S. Asano, T. Maruyama, Y. Yamaguchi, Performance comparison of FPGA, GPU and CPU in image processing, in IEEE 19th International Conference on Field Programmable Logic and Applications (Prague, Czech Republic, 2009), pp. 126–131

  41. D.A. Patterson, J.L. Hennessy, Computer Organization and Design—The Hardware/Software Interface (Morgan Kaufmann, Los Altos, 2009)

    MATH  Google Scholar 

  42. Intel Processors: http://www.intel.com/products/processor\_number, 2009

  43. Iberdrola Electric Rates: http://www.iberdrola.es, 2009

  44. S. Chey, J. Liz, J.W. Sheaffery, K. Skadrony, J. Lach, Accelerating compute-intensive applications with GPUs and FPGAs, in: IEEE Symposium on Application Specific Processors, 2008, pp. 101–107

  45. NVIDIA Quadro FX 580 Datasheet, NVIDIA Corporation, 2009

  46. D. Kirk, W.-M. Hwu, Programming Massively Parallel Processors: A Hands-on Approach (Morgan Kaufmann, Los Altos, 2010)

    Google Scholar 

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Acknowledgments

This work was partially funded by the Spanish Ministry of Science and Innovation and ERDF (the European Regional Development Fund), under the contract TIN2008-06491-C04-04 (the MSTAR project).

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Authors and Affiliations

  1. Department of Technologies of Computers and Communications, University of Extremadura, 10003, Caceres, Spain

    Juan A. Gomez-Pulido, Miguel A. Vega-Rodriguez & Juan M. Sanchez-Perez

  2. Department of Computer Science, School of Technology and Management, Polytechnic Institute of Leiria, 2410, Leiria, Portugal

    Silvio Priem-Mendes & Vitor Carreira

Authors
  1. Juan A. Gomez-Pulido
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  2. Miguel A. Vega-Rodriguez
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  3. Juan M. Sanchez-Perez
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Correspondence to Juan A. Gomez-Pulido.

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Gomez-Pulido, J.A., Vega-Rodriguez, M.A., Sanchez-Perez, J.M. et al. Accelerating floating-point fitness functions in evolutionary algorithms: a FPGA-CPU-GPU performance comparison. Genet Program Evolvable Mach 12, 403–427 (2011). https://doi.org/10.1007/s10710-011-9137-2

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