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Link to original content: https://doi.org/10.1007/s10703-019-00332-1
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TeLEx: learning signal temporal logic from positive examples using tightness metric

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Abstract

We propose a novel passive learning approach, TeLex, to infer signal temporal logic (STL) formulas that characterize the behavior of a dynamical system using only observed signal traces of the system. First, we present a template-driven learning approach that requires two inputs: a set of observed traces and a template STL formula. The unknown parameters in the template can include time-bounds of the temporal operators, as well as the thresholds in the inequality predicates. TeLEx finds the value of the unknown parameters such that the synthesized STL property is satisfied by all the provided traces and it is tight. This requirement of tightness is essential to generating interesting properties when only positive examples are provided and there is no option to actively query the dynamical system to discover the boundaries of legal behavior. We propose a novel quantitative semantics for satisfaction of STL properties which enables TeLEx to learn tight STL properties without multidimensional optimization. The proposed new metric is also smooth. This is critical to enable the use of gradient-based numerical optimization engines and it produces a 30x to 100x speed-up with respect to the state-of-art gradient-free optimization. Second, we present a novel technique for automatically learning the structure of the STL formula by incrementally constructing more complex formula guided by the robustness metric of subformula. We demonstrate the effectiveness of the overall approach for learning STL formulas from only positive examples on a set of synthetic and real-world benchmarks.

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Notes

  1. https://github.com/susmitjha/TeLEX.

  2. https://github.com/susmitjha/TeLEX/blob/master/tests/twoagent.py.

  3. https://github.com/udacity/self-driving-car/tree/master/challenges/challenge-2.

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Acknowledgements

This work is supported in part by US National Science Foundation (NSF) under Award Numbers CNS-1740079, CNS-1750009 and US ARL Cooperative Agreement W911NF-17-2-0196. All opinions expressed are those of the authors and not necessarily of the US NSF or ARL.

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Authors and Affiliations

  1. CSL, SRI International, Menlo Park, USA

    Susmit Jha, Ashish Tiwari & Natarajan Shankar

  2. EECS, UC Berkeley, Berkeley, USA

    Sanjit A. Seshia

  3. United Technologies Research Center, Berkeley, CA, USA

    Tuhin Sahai

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  1. Susmit Jha
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  2. Ashish Tiwari
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  3. Sanjit A. Seshia
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  4. Tuhin Sahai
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  5. Natarajan Shankar
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Correspondence to Susmit Jha.

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Jha, S., Tiwari, A., Seshia, S.A. et al. TeLEx: learning signal temporal logic from positive examples using tightness metric. Form Methods Syst Des 54, 364–387 (2019). https://doi.org/10.1007/s10703-019-00332-1

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