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Link to original content: https://doi.org/10.1007/978-3-642-70087-3_5
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VLSI-Realisierungen von Sortieralgorithmen

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Fachgespräche auf der 14. GI-Jahrestagung

Part of the book series: Informatik-Fachberichte ((INFORMATIK,volume 89))

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Zusammenfassung

Die Entwicklung der VLSI-Technologie erlaubt im Vergleich zu früheren Technologien einen nahezu unbegrenzten Parallelitätsgrad. Entscheidend für die Bewertung von Algorithmen, die mit Hilfe der VLSI-Technologie implementiert werden sollen, ist das Hardware-Modell, auf das sich die Algorithmenanalyse stützt. Alle aus der Literatur bekannten Modelle betrachten ein VLSI-chip als einen G-raphen, dessen Knoten Recheneinheiten (z.B. Addierer, Vergleicher mit wenigen Registern) und dessen Kanten Verbindungsleitungen sind.

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Schröder, H. (1984). VLSI-Realisierungen von Sortieralgorithmen. In: Ehrich, HD. (eds) Fachgespräche auf der 14. GI-Jahrestagung. Informatik-Fachberichte, vol 89. Springer, Berlin, Heidelberg. https://doi.org/10.1007/978-3-642-70087-3_5

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  • DOI: https://doi.org/10.1007/978-3-642-70087-3_5

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