Abstract
Image-pyramid generator is an important component for many computer vision applications. Due to the complexity of image scaling operations, embedded application processors usually generate three- or four-level image pyramids for vision applications. In this paper, we present an image pyramid accelerator for embedded processors that generates image pyramids of up to 24-levels of down-sampled resolutions for the input image. Since image pyramids are crucial for the coarse-to-fine analysis of many computer vision problems, more resolution levels in the image pyramid can improve the parameter-estimation accuracy. Furthermore, the down-sampling filters used in the proposed design is based on a long-tap Sine-windowed Sinc function filter. Therefore, it preserves more image details than other low-complexity filters such as the bilinear or the bicubic interpolation filter. The proposed circuit is verified on an FPGA development board with a Xilinx Kintex-7 device and will be made open-source. The experimental results show that the design is very promising for real-time computer vision applications.
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Adelson, E.H., Anderson, C.H., Bergen, J.R., Burt, P.J., Ogden, J.M.: Pyramid methods in image processing. RCA Eng. 29–6, 33–41 (1984)
Nuno-Maganda, M.A., Arias-Estrada, M.O., Feregrino-Uribe, C.: Three video applications using an FPGA-based pyramid implementation: tracking, mosaics and stabilization. In Proceedings of IEEE International Conference on Field Programmable Technology (FPT), Tokyo, Japan (2003)
Lee, B.: Design and implementation of image-pyramid. J. Korea Multimedia Soc., 19–7 (2016)
Horn, B., Schunck, B.: Determining optical flow. Artif. Intell. 17, 185–203 (1981)
Deqing, S., Roth, S., Black, M.J.: Secrets of optical flow estimation and their principles. In: IEEE International Conference on Computer Vision and Pattern Recognition (CVPR’10) 13–18 2010, San Francisco, pp. 2432-2439 (2010)
Farabet, C., Poulet, C., Han, J.Y., LeCun, Y.: CNP: an FPGA-based processor for convolutional networks. In: Proceedings of 2009 International Conference on Field Programmable Logic and Applications, Prague, pp. 32–37 (2009)
Sun, S., Reichel, J.: AHG Report on Spatial Scalability Resampling, JVT-R006. The 18th Meeting of the Joint Video Team. Bangkok, Thailand (2006)
Agrawal, K., Chowdhury, S.R.: Real-time multisensor Laplacian fusion on FPGA. In: Proceedings of the 19th International Symposium on VLSI Design and Test (2015)
Nuno-Maganda, M.A., Arias-Estrada, M.O.: Real-time FPGA-based architecture for bicubic interpolation: an application for digital image scaling. In: Proceedings of International Conference on Reconfigurable Computing and FPGAs (ReConFig’05), Puebla City, Mexico, pp. 28–30 (2005)
Ramachandran, S., Srinivasan, S.: Design and FPGA implementation of an MPEG based video scalar with reduced on-chip memory utilization. J. Syst. Architect. 51, 435–450 (2005). Elsevier
Xiao, J., Zou, X., Liu, Z., Guo, X.: Adaptive interpolation algorithm for real-time image resizing. In: Proceedings of the 1st International Conference on Innovative Computing, Information and Control - Volume I (ICICIC’06). Beijin, China (2006)
Suryavanshi, R.A., Sheelvant, S.: Review of implementation of image scaling algorithm on FPGA. Int. J. Innov. Adv. Comput. Sci. 4–7, 96-99 (2015). Academic Science
Zhu, Q., Garg, N., Tsai, Y.-T., Pulli, K.: An energy efficient time-sharing pyramid pipeline for multi-resolution computer vision. In: Proceeedings of IFIP/IEEE 21st International Conference on Very Large Scale Integration (VLSI-SoC), Istanbul, Turkey, pp. 278–281 (2013)
Schmid, M., Reiche, O., Schmitt, C., Hanning, F., Teich, J.: Code generation for high-level synthesis of multiresolution applications on FPGAs (2014). arXiv:1408.4721
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Tsai, CJ., Wang, CY. (2020). A Fine-Granularity Image Pyramid Accelerator for Embedded Processors. In: Orailoglu, A., Jung, M., Reichenbach, M. (eds) Embedded Computer Systems: Architectures, Modeling, and Simulation. SAMOS 2020. Lecture Notes in Computer Science(), vol 12471. Springer, Cham. https://doi.org/10.1007/978-3-030-60939-9_6
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