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Link to original content: https://dblp.uni-trier.de/rec/journals/tcad/SafieddineZKER19.xml
Maya H. Safieddine Fadi A. Zaraket Rouwaida Kanj Ali S. Elzein Wolfgang Roesner Verification at RTL Using Separation of Design Concerns. 1529-1542 2019 38 IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 8 https://doi.org/10.1109/TCAD.2018.2848589 db/journals/tcad/tcad38.html#SafieddineZKER19