Maya H. SafieddineFadi A. ZaraketRouwaida KanjAli S. ElzeinWolfgang RoesnerVerification at RTL Using Separation of Design Concerns.1529-1542201938IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.8https://doi.org/10.1109/TCAD.2018.2848589db/journals/tcad/tcad38.html#SafieddineZKER19