Maya H. Safieddine et al.: Verification at RTL Using Separation of Design Concerns. (2019)journals/tcad/SafieddineZKER1910.1109/TCAD.2018.2848589Verification at RTL Using Separation of Design Concerns.5Maya H. Safieddine1Fadi A. Zaraket2Rouwaida Kanj3Ali S. Elzein4Wolfgang Roesner51529-1542IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.3882019provenance information for RDF data of dblp record 'journals/tcad/SafieddineZKER19'2023-09-30T10:27:50+0200