Yeon-Jae Jung et al.: A dual-loop delay-locked loop using multiple voltage-controlled delay lines. (2001)journals/jssc/JungLSKKC0110.1109/4.918916A dual-loop delay-locked loop using multiple voltage-controlled delay lines.6Yeon-Jae Jung1Seung-Wook Lee2Daeyun Shim3Wonchan Kim4Changhyun Kim5Soo-In Cho6784-791IEEE J. Solid State CircuitsIEEE J. Solid State Circuits3652001provenance information for RDF data of dblp record 'journals/jssc/JungLSKKC01'2022-04-04T09:47:50+0200