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https://dblp.uni-trier.de/rec/journals/iet-cds/PanSY18.nt
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"Jeng-Shyang Pan et al.: Efficient digit-serial modular multiplication algorithm on FPGA. (2018)" .
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_:ID_7faac209bbfe9666d0e7d6aa2857d067 . _:ID_7faac209bbfe9666d0e7d6aa2857d067
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"journals/iet-cds/PanSY18" .
_:ID_aed82d8966fcf6e36c4cb76051dc1a85 . _:ID_aed82d8966fcf6e36c4cb76051dc1a85
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"10.1049/IET-CDS.2017.0300" .
"Efficient digit-serial modular multiplication algorithm on FPGA." .
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"3"^^
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_:Sig_430361c81787f5aa9440766883e12fab_1 . _:Sig_430361c81787f5aa9440766883e12fab_1
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"Jeng-Shyang Pan 0001" . _:Sig_430361c81787f5aa9440766883e12fab_1
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"1"^^
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_:Sig_430361c81787f5aa9440766883e12fab_2 . _:Sig_430361c81787f5aa9440766883e12fab_2
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"Pengfei Song" . _:Sig_430361c81787f5aa9440766883e12fab_2
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"2"^^
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_:Sig_430361c81787f5aa9440766883e12fab_3 . _:Sig_430361c81787f5aa9440766883e12fab_3
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"Chun-Sheng Yang" . _:Sig_430361c81787f5aa9440766883e12fab_3
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"3"^^
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"662-668" .
"IET Circuits Devices Syst." .
"IET Circuits Devices Syst." .
"12" .
"5" .
"2018"^^
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"provenance information for RDF data of dblp record 'journals/iet-cds/PanSY18'" .
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"2020-09-10T14:36:25+0200" .