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Link to original content: https://dblp.uni-trier.de/rec/journals/ieicet/ChungSPK05.xml
In-Young Chung Youngsoo Sohn Wonki Park Changhyun Kim Design Techniques of Delay-Locked Loop for Jitter Minimization in DRAM Applications. 753-759 2005 88-C IEICE Trans. Electron. 4 https://doi.org/10.1093/ietele/e88-c.4.753 db/journals/ieicet/ieicet88c.html#ChungSPK05