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Link to original content: https://dblp.uni-trier.de/rec/conf/vlsid/VermaS20.ris
Provider: Schloss Dagstuhl - Leibniz Center for Informatics Database: dblp computer science bibliography Content:text/plain; charset="utf-8" TY - CPAPER ID - DBLP:conf/vlsid/VermaS20 AU - Verma, Anuj AU - Shrestha, Rahul TI - A New Partially-Parallel VLSI-Architecture of Quasi-Cyclic LDPC Decoder for 5G New-Radio. BT - 33rd International Conference on VLSI Design and 19th International Conference on Embedded Systems, VLSID 2020, Bangalore, India, January 4-8, 2020 SP - 1 EP - 6 PY - 2020// DO - 10.1109/VLSID49098.2020.00018 UR - https://doi.org/10.1109/VLSID49098.2020.00018 ER -