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Link to original content: https://dblp.uni-trier.de/rec/conf/vlsid/SivanesanCB18.ris
Provider: Schloss Dagstuhl - Leibniz Center for Informatics Database: dblp computer science bibliography Content:text/plain; charset="utf-8" TY - CPAPER ID - DBLP:conf/vlsid/SivanesanCB18 AU - Sivanesan, Mayuran AU - Chattopadhyay, Anupam AU - Ronak, Bajaj TI - Accelerating Hash Computations Through Efficient Instruction-Set Customisation. BT - 31st International Conference on VLSI Design and 17th International Conference on Embedded Systems, VLSID 2018, Pune, India, January 6-10, 2018 SP - 362 EP - 367 PY - 2018// DO - 10.1109/VLSID.2018.91 UR - https://doi.org/10.1109/VLSID.2018.91 UR - https://doi.ieeecomputersociety.org/10.1109/VLSID.2018.91 ER -