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https://dblp.uni-trier.de/rec/conf/vlsid/SinghD93.nt
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"Vinaya Kumar Singh and Ajit Arvind Diwan: A Heuristic for Decomposition in Multi-Level Logic Optimization. (1993)" .
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_:ID_1eb9f4981d1fb1e6feaf30ae62cc06a5 . _:ID_1eb9f4981d1fb1e6feaf30ae62cc06a5
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"conf/vlsid/SinghD93" .
_:ID_e220fa40eb66852902ca60f2aca9542d . _:ID_e220fa40eb66852902ca60f2aca9542d
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"10.1109/ICVD.1993.669622" .
"A Heuristic for Decomposition in Multi-Level Logic Optimization." .
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"2"^^
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_:Sig_bd091be8410b7da29cfe57fe86b7d261_1 . _:Sig_bd091be8410b7da29cfe57fe86b7d261_1
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"Vinaya Kumar Singh" . _:Sig_bd091be8410b7da29cfe57fe86b7d261_1
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"1"^^
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_:Sig_bd091be8410b7da29cfe57fe86b7d261_2 . _:Sig_bd091be8410b7da29cfe57fe86b7d261_2
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"Ajit Arvind Diwan" . _:Sig_bd091be8410b7da29cfe57fe86b7d261_2
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"2"^^
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"5-8" .
"VLSI Design" .
"VLSI Design" .
"1993"^^
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"1993"^^
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"provenance information for RDF data of dblp record 'conf/vlsid/SinghD93'" .
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"2023-03-24T00:04:00+0100" .
