Sai Aparna Aketi et al.: Single-Error Hardened and Multiple-Error Tolerant Guarded Dual Modular Redundancy Technique. (2018)conf/vlsid/AketiMS1810.1109/VLSID.2018.71Single-Error Hardened and Multiple-Error Tolerant Guarded Dual Modular Redundancy Technique.3Sai Aparna Aketi1Joycee Mekie2Hemal Shah3250-255VLSIDVLSID20182018provenance information for RDF data of dblp record 'conf/vlsid/AketiMS18'2023-03-24T00:03:59+0100