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Link to original content: https://dblp.uni-trier.de/rec/conf/vlsic/XuOI21.ris
Provider: Schloss Dagstuhl - Leibniz Center for Informatics Database: dblp computer science bibliography Content:text/plain; charset="utf-8" TY - CPAPER ID - DBLP:conf/vlsic/XuOI21 AU - Xu, Zule AU - Osada, Masaru AU - Iizuka, Tetsuya TI - A 3.3-GHz 4.6-mW Fractional-N Type-II Hybrid Switched-Capacitor Sampling PLL Using CDAC-Embedded Digital Integral Path with -80-dBc Reference Spur. BT - 2021 Symposium on VLSI Circuits, Kyoto, Japan, June 13-19, 2021 SP - 1 EP - 2 PY - 2021// DO - 10.23919/VLSICIRCUITS52068.2021.9492381 UR - https://doi.org/10.23919/VLSICircuits52068.2021.9492381 ER -