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Link to original content: https://dblp.uni-trier.de/rec/conf/vlsi/ShresthaS18.rdf
Rahul Shrestha and Ashutosh Sharma: VLSI-Architecture of Radix-2/4/8 SISO Decoder for Turbo Decoding at Multiple Data-rates. (2018) conf/vlsi/ShresthaS18 10.1109/VLSI-SOC.2018.8644753 VLSI-Architecture of Radix-2/4/8 SISO Decoder for Turbo Decoding at Multiple Data-rates. 2 Rahul Shrestha 1 Ashutosh Sharma 2 131-136 VLSI-SoC VLSI-SoC 2018 2018 provenance information for RDF data of dblp record 'conf/vlsi/ShresthaS18' 2019-02-26T11:02:49+0100