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Link to original content: https://dblp.uni-trier.de/rec/conf/podc/DielacherFS09.rdf
Andreas Dielacher et al.: Brief announcement: how to speed-up fault-tolerant clock generation in VLSI systems-on-chip via pipelining. (2009) conf/podc/DielacherFS09 10.1145/1582716.1582762 Brief announcement: how to speed-up fault-tolerant clock generation in VLSI systems-on-chip via pipelining. 3 Andreas Dielacher 1 Matthias Függer 2 Ulrich Schmid 0001 3 276-277 PODC PODC 2009 2009 provenance information for RDF data of dblp record 'conf/podc/DielacherFS09' 2018-11-06T11:07:18+0100