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Link to original content: https://dblp.uni-trier.de/rec/conf/isvlsi/XydisPSE10.rdf
Sotirios Xydis et al.: High-Level Synthesis Methodologies for Delay-Area Optimized Coarse-Grained Reconfigurable Coprocessor Architectures. (2010) conf/isvlsi/XydisPSE10 10.1109/ISVLSI.2010.8 High-Level Synthesis Methodologies for Delay-Area Optimized Coarse-Grained Reconfigurable Coprocessor Architectures. 4 Sotirios Xydis 1 Kiamal Z. Pekmestzi 2 Dimitrios Soudris 3 George Economakos 4 486-487 ISVLSI ISVLSI 2010 2010 provenance information for RDF data of dblp record 'conf/isvlsi/XydisPSE10' 2023-03-24T00:02:41+0100