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https://dblp.uni-trier.de/rec/conf/dsd/VeeravalliPSS12.nt
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"Varadan Savulimedu Veeravalli et al.: Architecture and Design Analysis of a Digital Single-Event Transient/Upset Measurement Chip. (2012)" .
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_:ID_d6fbe8ae488470342838fd4eb4ddaa35 . _:ID_d6fbe8ae488470342838fd4eb4ddaa35
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"conf/dsd/VeeravalliPSS12" .
_:ID_0629542df382d0b16de9ce7cc9701316 . _:ID_0629542df382d0b16de9ce7cc9701316
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"10.1109/DSD.2012.26" .
"Architecture and Design Analysis of a Digital Single-Event Transient/Upset Measurement Chip." .
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"4"^^
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_:Sig_9a54886ca40dcf78eb919d0d10670979_1 . _:Sig_9a54886ca40dcf78eb919d0d10670979_1
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"Varadan Savulimedu Veeravalli" . _:Sig_9a54886ca40dcf78eb919d0d10670979_1
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"1"^^
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_:Sig_9a54886ca40dcf78eb919d0d10670979_2 . _:Sig_9a54886ca40dcf78eb919d0d10670979_2
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"Thomas Polzer" . _:Sig_9a54886ca40dcf78eb919d0d10670979_2
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"2"^^
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_:Sig_9a54886ca40dcf78eb919d0d10670979_3 . _:Sig_9a54886ca40dcf78eb919d0d10670979_3
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"Andreas Steininger" . _:Sig_9a54886ca40dcf78eb919d0d10670979_3
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"3"^^
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_:Sig_9a54886ca40dcf78eb919d0d10670979_4 . _:Sig_9a54886ca40dcf78eb919d0d10670979_4
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"Ulrich Schmid 0001" . _:Sig_9a54886ca40dcf78eb919d0d10670979_4
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"4"^^
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"8-17" .
"DSD" .
"DSD" .
"2012"^^
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"2012"^^
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"provenance information for RDF data of dblp record 'conf/dsd/VeeravalliPSS12'" .
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"2023-06-26T20:45:51+0200" .