Chetan Kumar V.P. Sai PhaneendraSyed Ershad AhmedSreehari VeeramachaneniN. Moorthy MuthukrishnanM. B. SrinivasA Unified Architecture for BCD and Binary Adder/Subtractor.426-4292011DSDhttps://doi.org/10.1109/DSD.2011.58https://doi.ieeecomputersociety.org/10.1109/DSD.2011.58conf/dsd/2011db/conf/dsd/dsd2011.html#VPAVMS11