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ORCIDJonathan Rose
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- affiliation: University of Toronto, Canada
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2020 – today
- 2024
[c94]Andrew Brown, Jiading Zhu, Mohamed Abdelwahab, Alec Dong, Cindy Wang, Jonathan Rose:
Generation, Distillation and Evaluation of Motivational Interviewing-Style Reflections with a Foundational Language Model. EACL (1) 2024: 1241-1252- [i2]Andrew Brown, Jiading Zhu, Mohamed Abdelwahab, Alec Dong, Cindy Wang, Jonathan Rose:
Generation, Distillation and Evaluation of Motivational Interviewing-Style Reflections with a Foundational Language Model. CoRR abs/2402.01051 (2024) - [i1]Rohan Deepak Ajwani, Zining Zhu, Jonathan Rose, Frank Rudzicz:
Plug and Play with Prompts: A Prompt Tuning Approach for Controlling Text Generation. CoRR abs/2404.05143 (2024) - 2020
- [j40]Braiden Brousseau
, Jonathan Rose, Moshe Eizenman:
Hybrid Eye-Tracking on a Smartphone with CNN Feature Extraction and an Infrared 3D Model. Sensors 20(2): 543 (2020) - [j39]Kevin E. Murray, Jason Luu, Matthew J. P. Walker, Conor McCullough, Sen Wang, Safeen Huda, Bo Yan, Charles Chiasson, Kenneth B. Kent, Jason Helge Anderson, Jonathan Rose, Vaughn Betz:
Optimizing FPGA Logic Block Architectures for Arithmetic. IEEE Trans. Very Large Scale Integr. Syst. 28(6): 1378-1391 (2020) - [c93]Soumil Chugh, Braiden Brousseau, Jonathan Rose, Moshe Eizenman:
Detection and Correspondence Matching of Corneal Reflections for Eye Tracking Using Deep Learning. ICPR 2020: 2210-2217
2010 – 2019
- 2018
- [j38]Henry Wong, Vaughn Betz, Jonathan Rose:
High-Performance Instruction Scheduling Circuits for Superscalar Out-of-Order Soft Processors. ACM Trans. Reconfigurable Technol. Syst. 11(1): 1:1-1:22 (2018) - [c92]Alex Rodionov, Jonathan Rose:
Automatic Topology Optimization for FPGA Interconnect Synthesis. FPL 2018: 30-34 - [c91]Braiden Brousseau, Jonathan Rose, Moshe Eizenman:
SmartEye: An Accurate Infrared Eye Tracking System for Smartphones. UEMCON 2018: 951-959 - 2017
- [c90]Fitsum Assamnew Andargie, Jonathan Rose, Todd M. Austin, Valeria Bertacco:
Energy efficient object detection on the mobile GP-GPU. AFRICON 2017: 945-950 - [c89]Alex Rodionov, Jonathan Rose:
Synchronization Constraints for Interconnect Synthesis. FPGA 2017: 95-104 - 2016
- [j37]Alex Rodionov, David Biancolin, Jonathan Rose:
Fine-Grained Interconnect Synthesis. ACM Trans. Reconfigurable Technol. Syst. 9(4): 31:1-31:22 (2016) - [j36]Henry Wong, Vaughn Betz, Jonathan Rose:
Microarchitecture and Circuits for a 200 MHz Out-of-Order Soft Processor Memory System. ACM Trans. Reconfigurable Technol. Syst. 10(1): 7:1-7:22 (2016) - [c88]Henry Wong, Vaughn Betz, Jonathan Rose:
High Performance Instruction Scheduling Circuits for Out-of-Order Soft Processors. FCCM 2016: 9-16 - 2015
- [c87]Fitsum Assamnew Andargie, Jonathan Rose:
Performance characterization of mobile GP-GPUs. AFRICON 2015: 1-6 - [c86]Alex Rodionov, David Biancolin, Jonathan Rose:
Fine-Grained Interconnect Synthesis. FPGA 2015: 46-55 - [c85]Alex Rodionov, Jonathan Rose:
Automatic FPGA system and interconnect construction with multicast and customizable topology. FPT 2015: 72-79 - 2014
- [j35]Jason Luu, Jeffrey Goeders, Michael Wainberg, Andrew Somerville, Thien Yu, Konstantin Nasartschuk, Miad Nasr, Sen Wang, Tim Liu, Nooruddin Ahmed, Kenneth B. Kent, Jason Helge Anderson, Jonathan Rose, Vaughn Betz:
VTR 7.0: Next Generation Architecture and CAD System for FPGAs. ACM Trans. Reconfigurable Technol. Syst. 7(2): 6:1-6:30 (2014) - [j34]Henry Wong, Vaughn Betz, Jonathan Rose:
Quantifying the Gap Between FPGA and Custom CMOS to Aid Microarchitectural Design. IEEE Trans. Very Large Scale Integr. Syst. 22(10): 2067-2080 (2014) - [c84]Jason Luu, Conor McCullough, Sen Wang, Safeen Huda, Bo Yan, Charles Chiasson, Kenneth B. Kent, Jason Helge Anderson, Jonathan Rose, Vaughn Betz:
On Hard Adders and Carry Chains in FPGAs. FCCM 2014: 52-59 - [c83]Jason Luu, Jonathan Rose, Jason Helge Anderson:
Towards interconnect-adaptive packing for FPGAs. FPGA 2014: 21-30 - 2013
- [c82]Henry Wong, Vaughn Betz, Jonathan Rose:
Efficient methods for out-of-order load/store execution for high-performance soft processors. FPT 2013: 442-445 - 2012
- [j33]Wei Zhang, Vaughn Betz, Jonathan Rose:
Portable and scalable FPGA-based acceleration of a direct linear system solver. ACM Trans. Reconfigurable Technol. Syst. 5(1): 6:1-6:26 (2012) - [j32]Peter Yiannacouras, J. Gregory Steffan, Jonathan Rose:
Portable, Flexible, and Scalable Soft Vector Processors. IEEE Trans. Very Large Scale Integr. Syst. 20(8): 1429-1442 (2012) - [c81]Jonathan Rose, Jason Luu, Chi Wai Yu, Opal Densmore, Jeffrey Goeders, Andrew Somerville, Kenneth B. Kent, Peter Jamieson, Jason Helge Anderson:
The VTR project: architecture and CAD for FPGAs from verilog to routing. FPGA 2012: 77-86 - [c80]Niyati Shah, Jonathan Rose:
On the difficulty of pin-to-wire routing in FPGAs. FPL 2012: 83-90 - [c79]Braiden Brousseau, Jonathan Rose:
An energy-efficient, fast FPGA hardware architecture for OpenCV-Compatible object detection. FPT 2012: 166-173 - 2011
- [j31]Alex Rodionov, Alexandr Bezginov, Jonathan Rose, Elisabeth R. M. Tillier:
A new, fast algorithm for detecting protein coevolution using maximum compatible cliques. Algorithms Mol. Biol. 6: 17 (2011) - [j30]Jason Luu, Ian Kuon, Peter Jamieson, Ted Campbell, Andy Gean Ye, Wei Mark Fang, Kenneth B. Kent, Jonathan Rose:
VPR 5.0: FPGA CAD and architecture exploration tools with single-driver routing, heterogeneity and process scaling. ACM Trans. Reconfigurable Technol. Syst. 4(4): 32:1-32:23 (2011) - [j29]Ian Kuon, Jonathan Rose:
Exploring Area and Delay Tradeoffs in FPGAs With Architecture and Automated Transistor Design. IEEE Trans. Very Large Scale Integr. Syst. 19(1): 71-84 (2011) - [c78]Jonathan Rose, Guy G. Lemieux:
The role of FPGAs in a converged future with heterogeneous programmable processors: pre-conference workshop. FPGA 2011: 1-2 - [c77]Henry Wong, Vaughn Betz, Jonathan Rose:
Comparing FPGA vs. custom cmos and the impact on processor microarchitecture. FPGA 2011: 5-14 - [c76]Jason Luu, Jason Helge Anderson, Jonathan Rose:
Architecture description and packing for logic blocks with hierarchy, modes and complex interconnect. FPGA 2011: 227-236 - 2010
- [j28]Peter A. Jamieson, Jonathan Rose:
Enhancing the Area Efficiency of FPGAs With Hard Circuits Using Shadow Clusters. IEEE Trans. Very Large Scale Integr. Syst. 18(12): 1696-1709 (2010) - [c75]Alex Rodionov, Alexandr Bezginov, Jonathan Rose, Elisabeth R. M. Tillier:
Faster coevolution detection of proteins using maximum similar cliques. BCB 2010: 484-486
2000 – 2009
- 2009
- [c74]Peter Yiannacouras, J. Gregory Steffan, Jonathan Rose:
Fine-grain performance scaling of soft vector processors. CASES 2009: 97-106 - [c73]Jason Luu, Keith Redmond, William Lo, Paul Chow, Lothar Lilge, Jonathan Rose:
FPGA-based Monte Carlo Computation of Light Absorption for Photodynamic Cancer Therapy. FCCM 2009: 157-164 - [c72]Jason Luu, Ian Kuon, Peter Jamieson, Ted Campbell, Andy Gean Ye, Wei Mark Fang, Jonathan Rose:
VPR 5.0: FPGA cad and architecture exploration tools with single-driver routing, heterogeneity and process scaling. FPGA 2009: 133-142 - [c71]Peter Yiannacouras, J. Gregory Steffan, Jonathan Rose:
Soft vector processors vs FPGA custom hardware: measuring and reducing the gap. FPGA 2009: 277 - [c70]Jonathan Rose:
The evolution of architecture exploration of programmable devices. FPL 2009: 3 - [c69]Peter Yiannacouras, J. Gregory Steffan, Jonathan Rose:
Data parallel FPGA workloads: Software versus hardware. FPL 2009: 51-58 - 2008
- [c68]Peter Yiannacouras, J. Gregory Steffan, Jonathan Rose:
VESPA: portable, scalable, and flexible FPGA-based vector processors. CASES 2008: 61-70 - [c67]Ian Kuon, Jonathan Rose:
Automated transistor sizing for FPGA architecture exploration. DAC 2008: 792-795 - [c66]Wei Mark Fang, Jonathan Rose:
Modeling routing demand for early-stage FPGA architecture development. FPGA 2008: 139-148 - [c65]Ian Kuon, Jonathan Rose:
Area and delay trade-offs in the circuit and architecture design of FPGAs. FPGA 2008: 149-158 - [c64]Wei Zhang, Vaughn Betz, Jonathan Rose:
Portable and scalable FPGA-based acceleration of a direct linear system solver. FPT 2008: 17-24 - 2007
- [j27]Ian Kuon, Russell Tessier, Jonathan Rose:
FPGA Architecture: Survey and Challenges. Found. Trends Electron. Des. Autom. 2(2): 135-253 (2007) - [j26]Ian Kuon, Jonathan Rose:
Measuring the Gap Between FPGAs and ASICs. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 26(2): 203-215 (2007) - [j25]Peter Yiannacouras, J. Gregory Steffan, Jonathan Rose:
Exploration and Customization of FPGA-Based Soft Processors. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 26(2): 266-277 (2007) - [c63]Peter Jamieson, Jonathan Rose:
Architecting Hard Crossbars on FPGAs and Increasing their Area Efficiency with Shadow Clusters. FPT 2007: 57-64 - 2006
- [j24]Ahmad Darabiha, W. James MacLean, Jonathan Rose:
Reconfigurable hardware implementation of a phase-correlation stereoalgorithm. Mach. Vis. Appl. 17(2): 116-132 (2006) - [j23]Andy Gean Ye, Jonathan Rose:
Using Bus-Based Connections to Improve Field-Programmable Gate-Array Density for Implementing Datapath Circuits. IEEE Trans. Very Large Scale Integr. Syst. 14(5): 462-473 (2006) - [c62]Ian Kuon, Jonathan Rose:
Measuring the gap between FPGAs and ASICs. FPGA 2006: 21-30 - [c61]Peter Yiannacouras, J. Gregory Steffan, Jonathan Rose:
Application-specific customization of soft processor microarchitecture. FPGA 2006: 201-210 - [c60]Peter Jamieson, Jonathan Rose:
Enhancing the area-efficiency of FPGAs with hard circuits using shadow clusters. FPT 2006: 1-8 - [c59]Jonathan Rose:
Invited Keynote 1: Closing the gap between FPGAs and ASICs. FPT 2006 - 2005
- [c58]Peter Yiannacouras, Jonathan Rose, J. Gregory Steffan:
The microarchitecture of FPGA-based soft processors. CASES 2005: 202-212 - [c57]Andy Gean Ye, Jonathan Rose:
Using bus-based connections to improve field-programmable gate array density for implementing datapath circuits. FPGA 2005: 3-13 - [c56]David M. Lewis, Elias Ahmed, Gregg Baeckler, Vaughn Betz, Mark Bourgeault, David Cashman, David R. Galloway, Mike Hutton, Christopher Lane, Andy Lee, Paul Leventis, Sandy Marquardt, Cameron McClintock, Ketan Padalia, Bruce Pedersen, Giles Powell, Boris Ratchev, Srinivas Reddy, Jay Schleicher, Kevin Stevens, Richard Yuan, Richard Cliff, Jonathan Rose:
The Stratix II logic and routing architecture. FPGA 2005: 14-20 - [c55]Ian Kuon, Aaron Egier, Jonathan Rose:
Design, layout and verification of an FPGA using automated tools. FPGA 2005: 215-226 - [c54]Andy Gean Ye, Jonathan Rose:
Measuring and Utilizing the Correlation Between Signal Connectivity and Signal Positioning for FPGAs Containing Multi-Bit Building Blocks. FPL 2005: 159-166 - [c53]Peter Jamieson, Jonathan Rose:
A Verilog RTL Synthesis Tool for Heterogeneous FPGAs. FPL 2005: 305-310 - [c52]Joshua Fender, Jonathan Rose, David R. Galloway:
The Transmogrifier-4: An FPGA-Based Hardware Development System with Multi-Gigabyte Memory Capacity and High Host and Memory Bandwidth. FPT 2005: 301-302 - 2004
- [j22]Paul D. Kundarewich, Jonathan Rose:
Synthetic circuit generation using clustering and iteration. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 23(6): 869-887 (2004) - [j21]Elias Ahmed, Jonathan Rose:
The effect of LUT and cluster size on deep-submicron FPGA performance and density. IEEE Trans. Very Large Scale Integr. Syst. 12(3): 288-298 (2004) - [c51]Tomasz S. Czajkowski, Jonathan Rose:
A synthesis oriented omniscient manual editor. FPGA 2004: 89-98 - [c50]Ian Kuon, Aaron Egier, Jonathan Rose:
Transistor grouping and metal layer trade-offs in automatic tile layout of FPGAs. FPGA 2004: 249 - [c49]Anish Alex, Jonathan Rose, Ruth Isserlin-Weinberger, Christopher W. V. Hogue:
Hardware Accelerated Novel Protein Identification. FPL 2004: 13-22 - [c48]Andy Gean Ye, Jonathan Rose:
Using multi-bit logic blocks and automated packing to improve field-programmable gate array density for implementing datapath circuits. FPT 2004: 129-136 - [c47]Jonathan Rose:
Hard vs. Soft: The Central Question of Pre-Fabricated Silicon. ISMVL 2004: 2-5 - 2003
- [c46]Andy Gean Ye, Jonathan Rose, David M. Lewis:
Architecture of datapath-oriented coarse-grain logic and routing for FPGAs. CICC 2003: 61-64 - [c45]Ahmad Darabiha, Jonathan Rose, W. James MacLean:
Video-Rate Stereo Depth Measurement on Programmable Hardware. CVPR (1) 2003: 203-210 - [c44]David M. Lewis, Vaughn Betz, David Jefferson, Andy Lee, Christopher Lane, Paul Leventis, Sandy Marquardt, Cameron McClintock, Bruce Pedersen, Giles Powell, Srinivas Reddy, Chris Wysocki, Richard Cliff, Jonathan Rose:
The StratixTM routing and logic architecture. FPGA 2003: 12-20 - [c43]Ketan Padalia, Ryan Fung, Mark Bourgeault, Aaron Egier, Jonathan Rose:
Automatic transistor and physical design of FPGA tiles from an architectural specification. FPGA 2003: 164-172 - [c42]Paul D. Kundarewich, Jonathan Rose:
Synthetic circuit generation using clustering and iteration. FPGA 2003: 245 - [c41]Joshua Fender, Jonathan Rose:
A high-speed ray tracing engine built on a field-programmable system. FPT 2003: 188-195 - [c40]Peter Yiannacouras, Jonathan Rose:
A parameterized automatic cache generator for FPGAs. FPT 2003: 324-327 - 2002
- [j20]Michael D. Hutton, Jonathan Rose, Derek G. Corneil:
Automatic generation of synthetic sequential benchmark circuits. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 21(8): 928-940 (2002) - [c39]Ajay Roopchansingh, Jonathan Rose:
Nearest neighbour interconnect architecture in deep submicron FPGAs. CICC 2002: 59-62 - [c38]William Chow, Jonathan Rose:
EVE: a CAD tool for manual placement and pipelining assistance of FPGA circuits. FPGA 2002: 85-94 - [c37]Andy Gean Ye, Jonathan Rose, David M. Lewis:
Synthesizing datapath circuits for FPGAs with emphasis on area minimization. FPT 2002: 219-226 - 2001
- [j19]Steven J. E. Wilton, Jonathan Rose, Zvonko G. Vranesic:
Structural analysis and generation of synthetic digital circuits with memory. IEEE Trans. Very Large Scale Integr. Syst. 9(1): 223-226 (2001) - [c36]Rob A. Rutenbar, Max Baron, Thomas Daniel, Rajeev Jayaraman, Zvi Or-Bach, Jonathan Rose, Carl Sechen:
Panel: (When) Will FPGAs Kill ASICs? DAC 2001: 321-322 - [c35]Mike Sheng, Jonathan Rose:
Mixing buffers and pass transistors in FPGA routing architectures. FPGA 2001: 75-84 - 2000
- [j18]Mohammed A. S. Khalid, Jonathan Rose:
A novel and efficient routing architecture for multi-FPGA systems. IEEE Trans. Very Large Scale Integr. Syst. 8(1): 30-39 (2000) - [j17]Alexander Marquardt, Vaughn Betz, Jonathan Rose:
Speed and area tradeoffs in cluster-based FPGA architectures. IEEE Trans. Very Large Scale Integr. Syst. 8(1): 84-93 (2000) - [c34]Elias Ahmed, Jonathan Rose:
The effect of LUT and cluster size on deep-submicron FPGA performance and density. FPGA 2000: 3-12 - [c33]Vaughn Betz, Jonathan Rose:
Automatic generation of FPGA routing architectures from high-level descriptions. FPGA 2000: 175-184 - [c32]Alexander Marquardt, Vaughn Betz, Jonathan Rose:
Timing-driven placement for FPGAs. FPGA 2000: 203-213 - [c31]Rob McCready, Jonathan Rose:
Real-time, frame-rate face detection on a configurable hardware system (poster abstract). FPGA 2000: 221
1990 – 1999
- 1999
- [b1]Vaughn Betz, Jonathan Rose, Alexander Marquardt:
Architecture and CAD for Deep-Submicron FPGAS. The Springer International Series in Engineering and Computer Science 497, Kluwer 1999, ISBN 978-1-4613-7342-1, pp. 1-247 - [j16]Steven J. E. Wilton, Jonathan Rose, Zvonko G. Vranesic:
The memory/logic interface in FPGAs with large embedded memory arrays. IEEE Trans. Very Large Scale Integr. Syst. 7(1): 80-91 (1999) - [j15]Paul Chow, Soon Ong Seo, Jonathan Rose, Kevin Chung, Gerard Páez-Monzón, Immanuel Rahardja:
The design of an SRAM-based field-programmable gate array. I. Architecture. IEEE Trans. Very Large Scale Integr. Syst. 7(2): 191-197 (1999) - [j14]Paul Chow, Soon Ong Seo, Jonathan Rose, Kevin Chung, Gerard Páez-Monzón, Immanuel Rahardja:
The design of a SRAM-based field-programmable gate array-Part II: Circuit design and layout. IEEE Trans. Very Large Scale Integr. Syst. 7(3): 321-330 (1999) - [c30]Alexander Marquardt, Vaughn Betz, Jonathan Rose:
Using Cluster-Based Logic Blocks and Timing-Driven Packing to Improve FPGA Speed and Density. FPGA 1999: 37-46 - [c29]Vaughn Betz, Jonathan Rose:
FPGA Routing Architecture: Segmentation and Buffering to Optimize Speed and Density. FPGA 1999: 59-68 - [c28]Yaska Sankar, Jonathan Rose:
Trading Quality for Compile Time: Ultra-Fast Placement for FPGAs. FPGA 1999: 157-166 - [c27]Mohammed A. S. Khalid, Jonathan Rose:
Hardwired-Clusters Partial-Crossbar: A Hierarchical Routing Architecture for Multi-FPGA Systems. IPPS/SPDP Workshops 1999: 597-605 - [c26]Michael D. Hutton, Jonathan Rose:
Equivalence classes of clone circuits for physical-design benchmarking. ISCAS (6) 1999: 428-431 - [c25]Michael D. Hutton, Jonathan Rose:
Applications of clone circuits to issues in physical-design. ISCAS (6) 1999: 448-451 - 1998
- [j13]Vaughn Betz, Jonathan Rose:
How Much Logic Should Go in an FPGA Logic Block? IEEE Des. Test Comput. 15(1): 10-15 (1998) - [j12]Michael D. Hutton, Jonathan Rose, Jerry P. Grossman, Derek G. Corneil:
Characterization and parameterized generation of synthetic combinational benchmark circuits. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 17(10): 985-996 (1998) - [j11]David M. Lewis, David R. Galloway, Marcus van Ierssel, Jonathan Rose, Paul Chow:
The Transmogrifier-2: a 1 million gate rapid-prototyping system. IEEE Trans. Very Large Scale Integr. Syst. 6(2): 188-198 (1998) - [j10]Vaughn Betz, Jonathan Rose:
Effect of the prefabricated routing track distribution on FPGA area-efficiency. IEEE Trans. Very Large Scale Integr. Syst. 6(3): 445-456 (1998) - [c24]Mohammed A. S. Khalid, Jonathan Rose:
A Hybrid Complete-Graph Partial-Crossbar Routing Architecture for Multi-FPGA Systems. FPGA 1998: 45-54 - [c23]Jonathan Rose, Sinan Kaptanoglu, Clive McCarthy, Rob Smith, Sandip Vij, Steve Taylor:
Constraints from Hell: How to Tell Makes a Good FPGA (Panel). FPGA 1998: 117-119 - [c22]Jordan S. Swartz, Vaughn Betz, Jonathan Rose:
A Fast Routability-Driven Router for FPGAs. FPGA 1998: 140-149 - 1997
- [c21]Steven J. E. Wilton, Jonathan Rose, Zvonko G. Vranesic:
Memory-to-Memory Connection Structures in FPGAs with Embedded Memory Arrays. FPGA 1997: 10-16 - [c20]David M. Lewis, David R. Galloway, Marcus van Ierssel, Jonathan Rose, Paul Chow:
The Transmogrifier-2: A 1 Million Gate Rapid Prototyping System. FPGA 1997: 53-61 - [c19]Jonathan Rose, Dwight D. Hill:
Architectural and Physical Design Challenges for One-Million Gate FPGAs and Beyond. FPGA 1997: 129-132 - [c18]Michael D. Hutton, Jonathan Rose, Derek G. Corneil:
Generation of Synthetic Sequential Benchmark Circuits. FPGA 1997: 149-155 - [c17]Vaughn Betz, Jonathan Rose:
VPR: A new packing, placement and routing tool for FPGA research. FPL 1997: 213-222 - 1996
- [j9]Stephen Dean Brown, Jonathan Rose:
FPGA and CPLD Architectures: A Tutorial. IEEE Des. Test Comput. 13(2): 42-57 (1996) - [c16]Michael D. Hutton, Jerry P. Grossman, Jonathan Rose, Derek G. Corneil:
Characterization and Parameterized Random Generation of Digital Circuits. DAC 1996: 94-99 - [c15]Vaughn Betz, Jonathan Rose:
Directional bias and non-uniformity in FPGA global routing architectures. ICCAD 1996: 652-659 - [e2]Jonathan Rose, Carl Ebeling:
Proceedings of the 1996 Fourth International Symposium on Field Programmable Gate Arrays, FPGA 1996, Monterey, CA, USA, February 11-13, 1996. ACM 1996, ISBN 0-89791-773-1 [contents] - 1995
- [c14]Vaughn Betz, Jonathan Rose:
Using Architectural "Families" to Increase FPGA Speed and Density. FPGA 1995: 10-16 - [c13]Steven J. E. Wilton, Jonathan Rose, Zvonko G. Vranesic:
Architecture of Centralized Field-Configurable Memory. FPGA 1995: 97-103 - [e1]Pak K. Chan, Jonathan Rose:
Proceedings of the Third International ACM Symposium on Field-Programmable Gate Arrays,FPGA 1995, Monterey, California, USA, February 12-14, 1995. ACM 1995, ISBN 0-89791-743-X [contents] - 1994
- [c12]David Karchmer, Jonathan Rose:
Definition and solution of the memory packing problem for field-programmable systems. ICCAD 1994: 20-26 - 1993
- [j8]Jonathan Rose, Abbas El Gamal, Alberto L. Sangiovanni-Vincentelli:
Architecture of field-programmable gate arrays. Proc. IEEE 81(7): 1013-1029 (1993) - [j7]Alberto L. Sangiovanni-Vincentelli, Abbas El Gamal, Jonathan Rose:
Synthesis method for field programmable gate arrays. Proc. IEEE 81(7): 1057-1083 (1993) - [j6]Stephen Dean Brown, Jonathan Rose, Zvonko G. Vranesic:
A stochastic model to predict the routability of field-programmable gate arrays. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 12(12): 1827-1838 (1993) - [c11]Jonathan Rose:
Logic Emulation: A Niche or a Future Standard for Design Verification? (Panel Abstract). DAC 1993: 164 - 1992
- [j5]Stephen Dean Brown, Jonathan Rose, Zvonko G. Vranesic:
A detailed router for field-programmable gate arrays. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 11(5): 620-628 (1992) - [c10]Kevin Chung, Jonathan Rose:
TEMPT: Technology Mapping for the Exploration of FPGA Architectures with Hard-Wired Connections. DAC 1992: 361-367 - [c9]Benjamin Tseng, Jonathan Rose, Stephen Dean Brown:
Improving FPGA Routing Architectures Using Architecture and CAD Interactions. ICCD 1992: 99-104 - 1991
- [c8]Robert J. Francis, Jonathan Rose, Zvonko G. Vranesic:
Chortle-crf: Fast Technology Mapping for Lookup Table-Based FPGAs. DAC 1991: 227-233 - [c7]Jonathan Rose:
Will the Field-Programmable Gata Array Replace the Mask-Programmable Gate Array? (Panel Abstract). DAC 1991: 779 - [c6]Robert J. Francis, Jonathan Rose, Zvonko G. Vranesic:
Technology Mapping on Lookup Table-Based FPGAs for Performance. ICCAD 1991: 568-571 - 1990
- [j4]Jonathan Rose, Wolfgang Klebsch, Jürgen Wolf:
Temperature measurement and equilibrium dynamics of simulated annealing placements. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 9(3): 253-259 (1990) - [j3]Jonathan Rose:
Parallel global routing for standard cells. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 9(10): 1085-1095 (1990) - [c5]Robert J. Francis, Jonathan Rose, Kevin Chung:
Chortle: A Technology Mapping Program for Lookup Table-Based Field Programmable Gate Arrays. DAC 1990: 613-619 - [c4]Stephen Dean Brown, Jonathan Rose, Zvonko G. Vranesic:
A Detailed Router for Field-Programmable Gate Arrays. ICCAD 1990: 382-385
1980 – 1989
- 1988
- [j2]Jonathan Rose, W. Martin Snelgrove, Zvonko G. Vranesic:
Parallel standard cell placement algorithms with quality equivalent to simulated annealing. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 7(3): 387-396 (1988) - [c3]Jonathan Rose:
LocusRoute: A Parallel Global Router for Standard Cells. DAC 1988: 189-195 - [c2]Jonathan Rose, Wolfgang Klebsch, Jürgen Wolf:
Temperature measurement of simulated annealing placements. ICCAD 1988: 514-517 - [c1]Jonathan Rose:
The Parallel Decomposition and Implementation of an Integrated Circuit Global Router. PPOPP/PPEALS 1988: 138-145 - 1985
- [j1]Jonathan Rose, Wayne M. Loucks, Zvonko G. Vranesic:
FERMTOR: A Tunable Multiprocessor Architecture. IEEE Micro 5(4): 5-17 (1985)
Coauthor Index
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