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2010 – 2019
- 2010
[j2]Uksong Kang, Hoeju Chung, Seongmoo Heo, Dukha Park, Hoon Lee, Jin Ho Kim, Soon-Hong Ahn, Sooho Cha, Jaesung Ahn, Dukmin Kwon, Jaewook Lee, Han-Sung Joo, Woo-Seop Kim, Dong Hyeon Jang, Nam-Seog Kim, Jung-Hwan Choi, Tae-Gyeong Chung, Jei-Hwan Yoo, Joo-Sun Choi, Changhyun Kim, Young-Hyun Jun:
8 Gb 3-D DDR3 DRAM Using Through-Silicon-Via Technology. IEEE J. Solid State Circuits 45(1): 111-119 (2010)
2000 – 2009
- 2009
- [c6]Uksong Kang, Hoeju Chung, Seongmoo Heo, Soon-Hong Ahn, Hoon Lee, Sooho Cha, Jaesung Ahn, Dukmin Kwon, Jin Ho Kim, Jaewook Lee, Han-Sung Joo, Woo-Seop Kim, Hyun-Kyung Kim, Eun-Mi Lee, So-Ra Kim, Keum-Hee Ma, Dong-Hyun Jang, Nam-Seog Kim, Man-Sik Choi, Sae-Jang Oh, Jung-Bae Lee, Tae-Kyung Jung, Jei-Hwan Yoo, Changhyun Kim:
8Gb 3D DDR3 DRAM using through-silicon-via technology. ISSCC 2009: 130-131 - 2007
- [j1]Seongmoo Heo, Ronny Krashinsky, Krste Asanovic:
Activity-Sensitive Flip-Flop and Latch Selection for Reduced Energy. IEEE Trans. Very Large Scale Integr. Syst. 15(9): 1060-1064 (2007) - 2006
- [b1]Seongmoo Heo:
Optimal digital system design in deep submicron technology. Massachusetts Institute of Technology, Cambridge, MA, USA, 2006 - 2005
- [c5]Seongmoo Heo, Krste Asanovic:
Replacing global wires with an on-chip network: a power analysis. ISLPED 2005: 369-374 - 2004
- [c4]Seongmoo Heo, Krste Asanovic:
Power-optimal pipelining in deep submicron technology. ISLPED 2004: 218-223 - 2003
- [c3]Seongmoo Heo, Kenneth C. Barr
, Krste Asanovic:
Reducing power density through activity migration. ISLPED 2003: 217-222 - 2002
- [c2]Seongmoo Heo, Kenneth C. Barr, Mark Hampton, Krste Asanovic:
Dynamic Fine-Grain Leakage Reduction Using Leakage-Biased Bitlines. ISCA 2002: 137-147 - 2001
- [c1]Seongmoo Heo, Ronny Krashinsky, Krste Asanovic:
Activity-Sensitive Flip-Flop and Latch Selection for Reduced Energy. ARVLSI 2001: 59-74
Coauthor Index
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