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2020 – today
- 2024
[j31]Boon Chiat Terence Teo
, Wu Cong Lim, Xian Yang Lim, Venkadasamy Navaneethan, Liter Siek:
Recent Development of High-PCE CMOS RF-DC Rectifier With Wide PIN Dynamic Range: Strategies and Trends - Review. IEEE Access 12: 79104-79117 (2024)- [c56]Wu Cong Lim, Boon Chiat Terence Teo, Xian Yang Lim, Liter Siek, Eng Leong Tan:
Comparative Analysis of Passive, Active, and Hybrid Cell Balancing for Optimal Battery Performance. ICEIC 2024: 1-4 - 2023
- [j30]Nardi Utomo, Boon Chiat Terence Teo, Xian Yang Lim, Venkadasamy Navaneethan, Ziming Liu, Chong Boon Tan, Liter Siek:
An 85.1% Peak Efficiency, Low Power Class H Audio Amplifier With Full Class H Operation. IEEE Trans. Circuits Syst. I Regul. Pap. 70(12): 4692-4704 (2023) - [c55]Ziming Liu, Wang Ling Goh, Liter Siek, Yuan Gao:
A Battery-input Hysteretic Buck Converter with 430nA Quiescent Current and 5×104 Load Current Dynamic Range for Wearable Biomedical Devices. BioCAS 2023: 1-5 - [c54]Xian Yang Lim, Wu Cong Lim, Boon Chiat Terence Teo, Venkadasamy Navaneethan, Chong Boon Tan, Nardi Utomo, Liter Siek, Atila Alvandpour:
A Review on Current-Steering DAC Design. ICEIC 2023: 1-4 - [c53]Boon Chiat Terence Teo, Wu Cong Lim, Xian Yang Lim, Venkadasamy Navaneethan, Chong Boon Tan, Nardi Utomo, Liter Siek:
Performance Analysis of Self-biasing Technique for Differential RF-DC Rectifier in IoT Application. ICEIC 2023: 1-4 - 2022
- [j29]Gibran Limi Jaya, Chirn Chye Boon, Shoushun Chen, Liter Siek:
An Equivalent-Time Sampling Millimeter-Wave Ultra-Wideband Radar Pulse Digitizer in CMOS. IEEE Trans. Circuits Syst. I Regul. Pap. 69(10): 3901-3914 (2022) - [c52]Oscar Morales Chacon, J. Jacob Wikner, Atila Alvandpour, Liter Siek:
Comparative Analysis of CMOS Latch-Driver Circuits for Current-Steering Digital-to-Analog Converters. MIXDES 2022: 93-98 - 2021
- [j28]Ao Zhou, Xin Ding, Chirn Chye Boon, Liter Siek, Yuan Liang, Yangtao Dong:
A Low-Power Quadrature LO Generator With Mutual Power-Supply Rejection Technique. IEEE Access 9: 137241-137248 (2021) - [c51]Teo Boon Chiat Terence, Venkadasamy Navaneethan, Lim Xian Yang, Nardi Utomo, Ziming Liu, Tan Chong Boon, Seah Yun Da Bryan, Ji-Jon Sit, Liter Siek:
A RF-DC Rectifier with Dual Voltage Polarity Self-Biasing for Wireless Sensor Node Application. ISCAS 2021: 1-5 - [c50]Nardi Utomo, Boon Chiat Terence Teo, Xian Yang Lim, Venkadasamy Navaneethan, Ziming Liu, Chong Boon Tan, Yun Da Bryan Seah, Ying Hung Yvonne Lam, Liter Siek:
Low Voltage Low Power Output Programmable OCL-LDO with Embedded Voltage Reference. ISCAS 2021: 1-5 - [c49]Oscar Morales Chacon, J. Jacob Wikner, Atila Alvandpour, Liter Siek:
A digital switching scheme to reduce DAC glitches using code-dependent randomization. NorCAS 2021: 1-5 - 2020
- [j27]Wendy Wee Yee Lau, Heng Wah Ho, Liter Siek:
Deep Neural Network (DNN) Optimized Design of 2.45 GHz CMOS Rectifier With 73.6% Peak Efficiency for RF Energy Harvesting. IEEE Trans. Circuits Syst. 67-I(12): 4322-4333 (2020) - [c48]Oscar Morales Chacon, J. Jacob Wikner, Atila Alvandpour, Liter Siek:
A 10-bit 3.75-GS/s Binary-Weighted DAC with 58.6-pJ Energy Consumption in 65-nm CMOS. NorCAS 2020: 1-4
2010 – 2019
- 2019
- [j26]Arjun Ramaswami Palaniappan, Liter Siek:
A TDC-less all-digital phase locked loop for medical implant applications. Microprocess. Microsystems 69: 168-178 (2019) - [j25]Devrishi Khanna, Chirn Chye Boon, Pilsoon Choi, Liter Siek, Bei Liu, Chenyang Li:
A Low-Noise, Positive-Input, Negative-Output Voltage Generator for Low-to-Moderate Driving Capacity Applications. IEEE Trans. Circuits Syst. I Regul. Pap. 66-I(9): 3423-3436 (2019) - [j24]Qiong Wei Low, Liter Siek:
A Single-Stage Dual-Output Tri-Mode AC-DC Regulator for Inductively Powered Application. IEEE Trans. Circuits Syst. I Regul. Pap. 66-I(9): 3620-3630 (2019) - [j23]Mi Zhou, Zhuochao Sun, Qiong Wei Low, Liter Siek:
Multiloop Control for Fast Transient DC-DC Converter. IEEE Trans. Very Large Scale Integr. Syst. 27(1): 219-228 (2019) - [c47]Arjun Ramaswami Palaniappan, Liter Siek:
A 0.6 V, 1.74 ps Resolution Capacitively Boosted Time-to-Digital Converter in 180 nm CMOS. ISCAS 2019: 1-4 - 2018
- [j22]Di Zhu, Liter Siek:
A 0.058 mm2, 24µW Temperature Sensor in 40nm CMOS Process with ± 0.5, °C Inaccuracy from -55 to 175°C. Circuits Syst. Signal Process. 37(6): 2278-2298 (2018) - [j21]Lei Qiu, Kai Tang, Yuanjin Zheng, Liter Siek, Yan Zhu, Seng-Pan U:
A 16-mW 1-GS/s With 49.6-dB SNDR TI-SAR ADC for Software-Defined Radio in 65-nm CMOS. IEEE Trans. Very Large Scale Integr. Syst. 26(3): 572-583 (2018) - [j20]Qiong Wei Low, Mi Zhou, Liter Siek:
A Single-Stage Direct-Conversion AC-DC Converter for Inductively Powered Application. IEEE Trans. Very Large Scale Integr. Syst. 26(5): 892-902 (2018) - [c46]Jian Sen Teh, Liter Siek:
Novel Edge Comparator with Input Time Hysteresis for Improved Edges Arbitration. ISCAS 2018: 1-5 - [c45]Jian Sen Teh, Liter Siek, Abdel Martinez Alonso, Anugerah Firdauzi, Akira Matsuzawa:
A 14-b, 850fs Fully Synthesizable Stochastic-Based Branching Time-to-Digital Converter in 65nm CMOS. ISCAS 2018: 1-5 - [c44]Mi Zhou, Zhuochao Sun, Zhekai Xiao, Qiong Wei Low, Liter Siek:
A Fast Transient Response DC-DC Converter with an Active Compensation Capacitor Module. ISCAS 2018: 1-5 - [c43]Arjun Ramaswami Palaniappan, Liter Siek:
A 0.0186 mm2, 0.65 V Supply, 9.53 ps RMS Jitter All-Digital PLL for Medical Implants. NORCAS 2018: 1-4 - [c42]Nardi Utomo, Liter Siek, Heng Goh Yap, Don Disney, Lawrence Selvaraj, Lulu Peng:
An 87% Peak Efficiency, 37W, Class H Audio Amplifier with GaN Output Stage. NORCAS 2018: 1-6 - 2017
- [j19]Kan Li, Yuanjin Zheng, Liter Siek:
A transient-enhanced low dropout regulator with rail to rail dynamic impedance attenuation buffer suitable for commercial design. Microelectron. J. 63: 27-34 (2017) - [j18]Xiaoyin Bai, Zhi-Hui Kong, Liter Siek:
A High-Efficiency 6.78-MHz Full Active Rectifier With Adaptive Time Delay Control for Wireless Power Transmission. IEEE Trans. Very Large Scale Integr. Syst. 25(4): 1297-1306 (2017) - [j17]Xiang Zhang, Liter Siek:
An 80.4% Peak Power Efficiency Adaptive Supply Class H Power Amplifier for Audio Applications. IEEE Trans. Very Large Scale Integr. Syst. 25(6): 1954-1965 (2017) - [j16]Zhekai Xiao, Anh Khoa Bui, Liter Siek:
A Hysteretic Switched-Capacitor DC-DC Converter With Optimal Output Ripple and Fast Transient Response. IEEE Trans. Very Large Scale Integr. Syst. 25(11): 2995-3005 (2017) - [c41]Hao Luo, Liter Siek:
A 0.9-V input PWM DCM boost converter with low output ripples and fast load transient response based on a novel square-root voltage mode (SRVM) control approach. ISCAS 2017: 1-4 - 2016
- [j15]Di Zhu, Liter Siek, Yuanjin Zheng:
High-Accuracy Time-Mode Duty-Cycle-Modulation-Based Temperature Sensor for Energy-Efficient System Applications. Circuits Syst. Signal Process. 35(7): 2317-2330 (2016) - [j14]Lei Qiu, Yuanjin Zheng, Liter Siek:
Multichannel Time Skew Calibration for Time-Interleaved ADCs Using Clock Signal. Circuits Syst. Signal Process. 35(8): 2669-2682 (2016) - [j13]Lei Qiu, Yuanjin Zheng, Liter Siek:
A Filter Bank Mismatch Calibration Technique for Frequency-Interleaved ADCs. Circuits Syst. Signal Process. 35(11): 3847-3862 (2016) - [j12]Yoon Hwee Leow, Howard Tang, Zhuochao Sun, Liter Siek:
A 1 V 103 dB 3rd-Order Audio Continuous-Time ΔΣ ADC With Enhanced Noise Shaping in 65 nm CMOS. IEEE J. Solid State Circuits 51(11): 2625-2638 (2016) - [j11]Lei Qiu, Kai Tang, Yuanjin Zheng, Liter Siek:
A Flexible-Weighted Nonbinary Searching Technique for High-Speed SAR-ADCs. IEEE Trans. Very Large Scale Integr. Syst. 24(8): 2808-2812 (2016) - [j10]Chundong Wu, Wang Ling Goh, Chiang Liang Kok, Liter Siek, Yat-Hei Lam, Xi Zhu, Ravinder Pal Singh:
Asymmetrical Dead-Time Control Driver for Buck Regulator. IEEE Trans. Very Large Scale Integr. Syst. 24(12): 3543-3547 (2016) - [c40]Junjie Kong, Stephan Henzler, Doris Schmitt-Landsiedel, Liter Siek:
A 9-bit, 1.08ps resolution two-step time-to-digital converter in 65 nm CMOS for time-mode ADC. APCCAS 2016: 348-351 - [c39]Lei Qiu, Kai Tang, Yan Zhu, Liter Siek, Yuanjin Zheng, Seng-Pan U:
A 10-bit 1GS/s 4-way TI SAR ADC with tap-interpolated FIR filter based time skew calibration. A-SSCC 2016: 77-80 - [c38]Di Zhu, Jiacheng Wang, Liter Siek:
A close-loop time-mode temperature sensor with inaccuracy of -0.6°C/0.5°C from -40°C to 120°C. ISCAS 2016: 942-945 - [c37]Anh Khoa Bui, Zhekai Xiao, Liter Siek:
Digitally-controlled H-bridge DC-DC converter for micropower PV energy harvesting system. ISIC 2016: 1-4 - [c36]Gibran Limi Jaya, Shoushun Chen, Liter Siek:
A dual redundancy radiation-hardened Flip-Flop based on C-element in 65nm process. ISIC 2016: 1-4 - [c35]Qiong Wei Low, Mi Zhou, Liter Siek:
Performance analysis on active rectifier structures for inductively powered application. ISIC 2016: 1-4 - [c34]W. L. Tan, C. H. Chang, Liter Siek:
Electronically tunable MOSFET-based resistor used in a variable gain amplifier or filter. ISIC 2016: 1-4 - [c33]Jian Sen Teh, Arjun Ramaswami Palaniappan, Liter Siek, Yuanjin Zheng:
Review of pulse generators for gated ring oscillator based Time-to-Digital converters. ISIC 2016: 1-4 - [c32]Zhekai Xiao, Anh Khoa Bui, Liter Siek:
A switched-capacitor DC-DC converter with embedded fast NMOS-LDOs achieving low noise, low output voltage ripple and fast response. ISIC 2016: 1-4 - [c31]Chengyue Yu, Xiang Zhang, Liter Siek:
A continuous switching mode step-down switched-capacitor regulator with inrush current control scheme. ISIC 2016: 1-4 - [c30]Mi Zhou, Qiong Wei Low, Liter Siek:
A high efficiency synchronous buck converter with adaptive dead-time control. ISIC 2016: 1-4 - 2015
- [j9]Di Zhu, Liter Siek:
A New Time-Mode On-Chip Oscillator-Based High Linearity and Low Power Temperature Sensor. J. Circuits Syst. Comput. 24(10): 1550155:1-1550155:12 (2015) - [j8]Guolei Yu, Kin Wai Roy Chew, Zhuochao Sun, Howard Tang, Liter Siek:
A 400 nW Single-Inductor Dual-Input-Tri-Output DC-DC Buck-Boost Converter With Maximum Power Point Tracking for Indoor Photovoltaic Energy Harvesting. IEEE J. Solid State Circuits 50(11): 2758-2772 (2015) - [j7]Chengyue Yu, Liter Siek:
An Area-Efficient Current-Mode Bandgap Reference With Intrinsic Robust Start-Up Behavior. IEEE Trans. Circuits Syst. II Express Briefs 62-II(10): 937-941 (2015) - [c29]Chundong Wu, Wang Ling Goh, Chiang Liang Kok, Wanlan Yang, Liter Siek:
A low TC, supply independent and process compensated current reference. CICC 2015: 1-4 - [c28]Robin Tanzania, Fook Hoong Choo, Liter Siek:
Design of WPT coils to minimize AC resistance and capacitor stress applied to SS-topology. IECON 2015: 118-122 - [c27]Chiang Liang Kok, Xin Li, Liter Siek, Di Zhu, Junjie Kong:
A switched capacitor deadtime controller for DC-DC buck converter. ISCAS 2015: 217-220 - [c26]Arjun Ramaswami Palaniappan, Dominic Maurath, Felix Kalathiparambil, Liter Siek:
A higher order curvature corrected 2 ppm/°C CMOS voltage reference circuit. ISCAS 2015: 505-508 - [c25]Junjie Kong, Liter Siek, Chiang Liang Kok:
A 9-bit body-biased vernier ring time-to-digital converter in 65 nm CMOS technology. ISCAS 2015: 1650-1653 - [c24]Lei Qiu, Kai Tang, Yuanjin Zheng, Liter Siek:
A digital time skew calibration technique for time-interleaved ADCs. ISCAS 2015: 2297-2300 - [c23]Qiong Wei Low, Liter Siek, Mi Zhou:
A high efficiency rectifier for inductively power transfer application. VLSI-SoC 2015: 270-273 - 2014
- [j6]Fei Li, Chip-Hong Chang, Arindam Basu, Liter Siek:
A 0.7 V low-power fully programmable Gaussian function generator for brain-inspired Gaussian correlation associative memory. Neurocomputing 138: 69-77 (2014) - [j5]Howard Tang, Zhuochao Sun, Kin Wai Roy Chew, Liter Siek:
A 1.33 µW 8.02-ENOB 100 kS/s Successive Approximation ADC With Supply Reduction Technique for Implantable Retinal Prosthesis. IEEE Trans. Biomed. Circuits Syst. 8(6): 844-856 (2014) - [j4]Zhuochao Sun, Kin Wai Roy Chew, Howard Tang, Guolei Yu, Liter Siek:
A 0.42-V Input Boost dc-dc Converter With Pseudo-Digital Pulsewidth Modulation. IEEE Trans. Circuits Syst. II Express Briefs 61-II(8): 634-638 (2014) - [j3]Howard Tang, Zhuochao Sun, Kin Wai Roy Chew, Liter Siek:
A 5.8 nW 9.1-ENOB 1-kS/s Local Asynchronous Successive Approximation Register ADC for Implantable Medical Device. IEEE Trans. Very Large Scale Integr. Syst. 22(10): 2220-2224 (2014) - [c22]Zhuochao Sun, Liter Siek, Ravinder Pal Singh, Minkyu Je:
A Fixed-frequency hysteretic controlled buck DC-DC converter with improved load regulation. ISCAS 2014: 954-957 - [c21]Lei Qiu, Yuanjin Zheng, Di Zhu, Liter Siek:
A statistic based time skew calibration method for time-interleaved ADCs. ISCAS 2014: 2373-2376 - [c20]Zhekai Xiao, Chiang Liang Kok, Liter Siek:
Triple boundary multiphase with predictive interleaving technique for switched capacitor DC-DC converter regulation. ISIC 2014: 17-20 - [c19]Di Zhu, Jiacheng Wang, Liter Siek, Chiang Liang Kok, Lei Qiu, Yuanjin Zheng:
High accuracy time-mode duty-cycle-modulation-based temperature sensor for energy efficient system applications. ISIC 2014: 400-403 - 2013
- [c18]Lei Qiu, Yuanjin Zheng, Liter Siek:
Analysis and design of high performance frequency-interleaved ADC. ISCAS 2013: 2022-2025 - [c17]Kin Wai Roy Chew, Zhuochao Sun, Howard Tang, Liter Siek:
A 400nW single-inductor dual-input-tri-output DC-DC buck-boost converter with maximum power point tracking for indoor photovoltaic energy harvesting. ISSCC 2013: 68-69 - 2012
- [j2]Chiang Liang Kok, Liter Siek, Wei Meng Lim:
A Novel Ultra-Low Power Two-Terminal Zener voltage Reference. J. Circuits Syst. Comput. 21(6) (2012) - [c16]Chiang Liang Kok, Qi Huang, Di Zhu, Liter Siek, Wei Meng Lim:
A fully digital green LDO regulator dedicated for biomedical implant using a power-aware binary switching technique. APCCAS 2012: 5-8 - [c15]Howard Tang, Joshua Yung Lih Low, Jeremy Yung Shern Low, Liter Siek, Ching-Chuen Jong, Chip-Hong Chang:
A compact 16-bit dual-slope integrating circuit for direct analog-to-residue conversion. APCCAS 2012: 272-275 - [c14]Chiang Liang Kok, Liter Siek, Fei Gao, Yuanjin Zheng, Wei Meng Lim:
An ultra-compact green bio-regulator dedicated for brain cortical implant using a dynamic PSR enhancement technique. EMBC 2012: 1647-1650 - [c13]Qi Huang, Di Zhu, Liter Siek:
A novel analog-to-residue conversion scheme based on clock overlapping technique. ISCAS 2012: 3206-3209 - [c12]Di Zhu, Qi Huang, Zhao Chuan Lee, Yuanjin Zheng, Liter Siek:
A novel analog-to-residue converter for biomedical DSP application. ISOCC 2012: 371-374 - 2010
- [c11]Yoon Hwee Leow, Liter Siek:
A high speed tracking quantizer for Continuous-Time multi-bit sigma delta modulators. APCCAS 2010: 776-779 - [c10]Howard Tang, Liter Siek:
Analog-to-Digital Converter with energy recovery capability using adiabatic technique. APCCAS 2010: 780-783 - [c9]Richard Wee Tar Ng, Liter Siek:
A simplified approach for baseband recovery in SDR architectures. APCCAS 2010: 1059-1062
2000 – 2009
- 2009
- [j1]Hai Qi Liu, Wang Ling Goh, Liter Siek, Wei Meng Lim, Yue Ping Zhang:
A Low-Noise Multi-GHz CMOS Multiloop Ring Oscillator With Coarse and Fine Frequency Tuning. IEEE Trans. Very Large Scale Integr. Syst. 17(4): 571-577 (2009) - [c8]Fei Li, Chip-Hong Chang, Liter Siek:
A Compact Current Mode Neuron Circuit with Gaussian Taper Learning Capability. ISCAS 2009: 2129-2132 - 2007
- [c7]Danping Li, Liter Siek:
A two-step dynamic reference A/D converter. ECCTD 2007: 232-235 - [c6]Yuan Sun, Liter Siek:
A spur-reduction technique in a fully integrated CMOS frequency synthesizer for 5-GHz WLAN SOC. SoCC 2007: 113-116 - 2005
- [c5]Hai Qi Liu, Wang Ling Goh, Liter Siek:
A 0.18-µm 10-GHz CMOS ring oscillator for optical transceivers. ISCAS (2) 2005: 1525-1528 - [c4]Q. X. Zhang, Liter Siek:
A new 4.3 ppm/°C voltage reference using standard CMOS process with 1V supply voltage. ISCAS (5) 2005: 4249-4252 - [c3]Hai Qi Liu, Wang Ling Goh, Liter Siek:
1.8-V 10-GHZ ring VCO design using 0.18-μm CMOS technology. SoCC 2005: 77-78 - 2000
- [c2]Pak K. Chan, Liter Siek, Hwee C. Tay, Jing H. Su:
A low-offset class-AB CMOS operational amplifier. ISCAS 2000: 455-458
1990 – 1999
- 1999
- [c1]Pak Kwong Chan, L. S. Ng, Liter Siek, M. S. Tse, J. Y. Ong, K. S. Lok:
Bulk compensated CMOS squaring circuits. ISCAS (2) 1999: 248-251
Coauthor Index
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last updated on 2024-10-08 21:28 CEST by the dblp team
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