iBet uBet web content aggregator. Adding the entire web to your favor.

Link to original content: https://dblp.uni-trier.de/pid/80/887-2.xml

Zhengyu Chen 0002 Northwestern University, Evanston, IL, USA https://orcid.org/0000-0001-5811-456X https://ieeexplore.ieee.org/author/37086464862 Zhengyu Chen Zhengyu Chen 0001 Westlake University, Hangzhou, China Zhejiang University, Hangzhou, China https://orcid.org/0000-0002-9863-556X Zhengyu Chen 0003 Meta Iowa State University, Ames, IA, USA https://scholar.google.com/citations?user=kyvCRoIAAAAJ https://orcid.org/0000-0003-1298-883X Zhengyu Chen 0004 Tsinghua University, Sichuan Energy Internet Research Institute, Chengdu, China https://orcid.org/0000-0002-0487-5037 https://ieeexplore.ieee.org/author/37086279892 Zhengyu Chen 0005 Shanghai University, China Zhengyu Chen 0006 Jinling Institute of Technology, Nanjing, China Nanjing University of Posts & Telecommunications, Nanjing, China https://orcid.org/0000-0003-1132-023X https://ieeexplore.ieee.org/author/38024354400

Zhengyu Chen 0002 Jie Gu 0001 High-Throughput Dynamic Time Warping Accelerator for Time-Series Classification With Pipelined Mixed-Signal Time-Domain Computing. 624-635 2021 56 IEEE J. Solid State Circuits 2 https://doi.org/10.1109/JSSC.2020.3021066 db/journals/jssc/jssc56.html#ChenG21

Zhengyu Chen 0002 Xi Chen Jie Gu 0001 15.3 A 65nm 3T Dynamic Analog RAM-Based Computing-in-Memory Macro and CNN Accelerator with Retention Enhancement, Adaptive Analog Sparsity and 44TOPS/W System Energy Efficiency. 240-242 2021 ISSCC https://doi.org/10.1109/ISSCC42613.2021.9366045 conf/isscc/2021 db/conf/isscc/isscc2021.html#ChenCG21 Zhengyu Chen 0002 Sihua Fu Qiankai Cao Jie Gu 0001 A Mixed-Signal Time-Domain Generative Adversarial Network Accelerator with Efficient Subthreshold Time Multiplier and Mixed-Signal On-Chip Training for Low Power Edge Devices. 1-2 2020 VLSI Circuits https://doi.org/10.1109/VLSICircuits18222.2020.9162829 conf/vlsic/2020 db/conf/vlsic/vlsic2020.html#ChenFCG20

Zhengyu Chen 0002 Jie Gu 0001 A Time-Domain Computing Accelerated Image Recognition Processor With Efficient Time Encoding and Non-Linear Logic Operation. 3226-3237 2019 54 IEEE J. Solid State Circuits 11 https://doi.org/10.1109/JSSC.2018.2883394 db/journals/jssc/jssc54.html#ChenG19

Zhengyu Chen 0002 Hai Zhou 0001 Jie Gu 0001 R-Accelerator: An RRAM-Based CGRA Accelerator With Logic Contraction. 2655-2667 2019 27 IEEE Trans. Very Large Scale Integr. Syst. 11 https://doi.org/10.1109/TVLSI.2019.2925937 db/journals/tvlsi/tvlsi27.html#ChenZG19

Zhengyu Chen 0002 Hai Zhou 0001 Jie Gu 0001 Digital Compatible Synthesis, Placement and Implementation of Mixed-Signal Time-Domain Computing. 67 2019 DAC https://doi.org/10.1145/3316781.3317800 https://ieeexplore.ieee.org/document/8806926 conf/dac/2019 db/conf/dac/dac2019.html#ChenZG19 Zhengyu Chen 0002 Jie Gu 0001 A Scalable Pipelined Time-Domain DTW Engine for Time-Series Classification Using Multibit Time Flip-Flops With 140Giga-Cell-Updates/s Throughput. 324-326 2019 ISSCC https://doi.org/10.1109/ISSCC.2019.8662340 conf/isscc/2019 db/conf/isscc/isscc2019.html#ChenG19

Zhengyu Chen 0002 Huanyu Wang Geng Xie Jie Gu 0001 A Comprehensive Stochastic Design Methodology for Hold-Timing Resiliency in Voltage-Scalable Design. 2118-2131 2018 26 IEEE Trans. Very Large Scale Integr. Syst. 10 http://doi.ieeecomputersociety.org/10.1109/TVLSI.2018.2847622 db/journals/tvlsi/tvlsi26.html#ChenWXG18

Zhengyu Chen 0002 Jie Gu 0001 An Image Recognition Processor with Time-domain Accelerators using Efficient Time Encoding and Non-linear Logic Operation. 257-260 2018 A-SSCC https://doi.org/10.1109/ASSCC.2018.8579259 conf/asscc/2018 db/conf/asscc/asscc2018.html#ChenG18 Zhengyu Chen 0002 Hai Zhou 0001 Jie Gu 0001 R-Accelerator: A Reconfigurable Accelerator with RRAM Based Logic Contraction and Resource Optimization for Application Specific Computing. 163-170 2018 ICCD https://doi.org/10.1109/ICCD.2018.00034 https://doi.ieeecomputersociety.org/10.1109/ICCD.2018.00034 conf/iccd/2018 db/conf/iccd/iccd2018.html#ChenZG18 Zhengyu Chen 0002 Jie Gu 0001 Analysis and Design of Energy Efficient Time Domain Signal Processing. 100-105 2016 ISLPED https://doi.org/10.1145/2934583.2934585 conf/islped/2016 db/conf/islped/islped2016.html#ChenG16 Qiankai Cao Xi Chen Sihua Fu Jie Gu 0001 Huanyu Wang Geng Xie Hai Zhou 0001