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ORCIDZhengyu Chen 0002
Person information
- affiliation: Northwestern University, Evanston, IL, USA
Other persons with the same name
- Zhengyu Chen — disambiguation page
- Zhengyu Chen 0001
![[0000-0002-9863-556X]](https://dblp.uni-trier.de/img/orcid-mark.12x12.png "0000-0002-9863-556X")
— Westlake University, Hangzhou, China (and 1 more) - Zhengyu Chen 0003 — Meta (and 1 more)
- Zhengyu Chen 0004 — Tsinghua University, Sichuan Energy Internet Research Institute, Chengdu, China
- Zhengyu Chen 0005 — Shanghai University, China
- Zhengyu Chen 0006 — Jinling Institute of Technology, Nanjing, China (and 1 more)
Other persons with a similar name
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2020 – today
- 2021
[j4]Zhengyu Chen, Jie Gu:
High-Throughput Dynamic Time Warping Accelerator for Time-Series Classification With Pipelined Mixed-Signal Time-Domain Computing. IEEE J. Solid State Circuits 56(2): 624-635 (2021)- [c7]Zhengyu Chen, Xi Chen, Jie Gu:
15.3 A 65nm 3T Dynamic Analog RAM-Based Computing-in-Memory Macro and CNN Accelerator with Retention Enhancement, Adaptive Analog Sparsity and 44TOPS/W System Energy Efficiency. ISSCC 2021: 240-242 - 2020
- [c6]Zhengyu Chen, Sihua Fu, Qiankai Cao, Jie Gu:
A Mixed-Signal Time-Domain Generative Adversarial Network Accelerator with Efficient Subthreshold Time Multiplier and Mixed-Signal On-Chip Training for Low Power Edge Devices. VLSI Circuits 2020: 1-2
2010 – 2019
- 2019
- [j3]Zhengyu Chen, Jie Gu:
A Time-Domain Computing Accelerated Image Recognition Processor With Efficient Time Encoding and Non-Linear Logic Operation. IEEE J. Solid State Circuits 54(11): 3226-3237 (2019) - [j2]Zhengyu Chen, Hai Zhou, Jie Gu:
R-Accelerator: An RRAM-Based CGRA Accelerator With Logic Contraction. IEEE Trans. Very Large Scale Integr. Syst. 27(11): 2655-2667 (2019) - [c5]Zhengyu Chen, Hai Zhou, Jie Gu:
Digital Compatible Synthesis, Placement and Implementation of Mixed-Signal Time-Domain Computing. DAC 2019: 67 - [c4]Zhengyu Chen, Jie Gu:
A Scalable Pipelined Time-Domain DTW Engine for Time-Series Classification Using Multibit Time Flip-Flops With 140Giga-Cell-Updates/s Throughput. ISSCC 2019: 324-326 - 2018
- [j1]Zhengyu Chen, Huanyu Wang, Geng Xie, Jie Gu:
A Comprehensive Stochastic Design Methodology for Hold-Timing Resiliency in Voltage-Scalable Design. IEEE Trans. Very Large Scale Integr. Syst. 26(10): 2118-2131 (2018) - [c3]Zhengyu Chen, Jie Gu:
An Image Recognition Processor with Time-domain Accelerators using Efficient Time Encoding and Non-linear Logic Operation. A-SSCC 2018: 257-260 - [c2]Zhengyu Chen, Hai Zhou, Jie Gu:
R-Accelerator: A Reconfigurable Accelerator with RRAM Based Logic Contraction and Resource Optimization for Application Specific Computing. ICCD 2018: 163-170 - 2016
- [c1]Zhengyu Chen, Jie Gu:
Analysis and Design of Energy Efficient Time Domain Signal Processing. ISLPED 2016: 100-105
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