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ORCIDSreehari Veeramachaneni
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2020 – today
- 2024
[j13]Aditya Anirudh Jonnalagadda
, Uppugunduru Anil Kumar, Rishi Thotli, Satvik Sardesai, Sreehari Veeramachaneni, Syed Ershad Ahmed:
ADEPNET: A Dynamic-Precision Efficient Posit Multiplier for Neural Networks. IEEE Access 12: 31036-31046 (2024)- [j12]L. Hemanth Krishna, Ayesha Sk, J. Bhaskara Rao, Sreehari Veeramachaneni, Sk. Noor Mahammad:
Energy-Efficient Approximate Multiplier Design With Lesser Error Rate Using the Probability-Based Approximate 4:2 Compressor. IEEE Embed. Syst. Lett. 16(2): 134-137 (2024) - [c36]Rishi Agrawal, Narayanabhatla Savyasachi Abhijith, Uppugunduru Anil Kumar, Sreehari Veeramachaneni, Syed Ershad Ahmed:
Energy-Efficient Ternary Multiplier. AICAS 2024: 382-387 - [c35]Sesibhushana Rao Bommana, Sreehari Veeramachaneni, M. B. Srinivas:
Bistable Physically Unclonable Function with Dynamic Threshold Voltage. MWSCAS 2024: 167-172 - [c34]Raghavendra Kumar Sakali, Sreehari Veeramachaneni, Sk. Noor Mahammad:
Fault-Tolerant Floating-Point Multiplier Design for Mission Critical Systems. VLSID 2024: 678-683 - 2023
- [j11]Raghavendra Kumar Sakali, Sreehari Veeramachaneni, Sk. Noor Mahammad:
Preferential fault-tolerance multiplier design to mitigate soft errors in FPGAs. Integr. 93: 102068 (2023) - [j10]Raghavendra Kumar Sakali, P. Balasubramanian, Ramesh Reddy, Sreehari Veeramachaneni, Sk. Noor Mahammad:
Optimized Fault-Tolerant Adder Design Using Error Analysis. J. Circuits Syst. Comput. 32(6): 2350091:1-2350091:32 (2023) - [c33]Aditya Anirudh Jonnalagadda, Anil Kumar Uppugunduru, Sreehari Veeramachaneni, Syed Ershad Ahmed:
Design of Energy Efficient Posit Multiplier. ACM Great Lakes Symposium on VLSI 2023: 645-651 - [c32]Shalini Burri, Gowtham Sri Harsha Kudulla, Pavan Kumar Jogi, Anantha Sai Satwik Vysyaraju, Uppugunduru Anil Kumar, Syed Ershad Ahmed, Sreehari Veeramachaneni:
Highly Accurate Approximate Ternary Multipliers for Error Resilient Applications. ISED 2023: 1-6 - [c31]Sangireddy Tharuni, Basani Harshavardhan Reddy, Bhukya Mamatha, Uppugunduru Anil Kumar, Syed Ershad Ahmed, Sreehari Veeramachaneni:
Power Efficient Approximate Ternary Subtractor for Image Processing Applications. iSES 2023: 127-130 - 2022
- [j9]L. Guna Sekhar Sai Harsha, Bhaskara Rao Jammu, Nalini Bodasingi, Sreehari Veeramachaneni, Noor Mohammad S.:
A Low Error, Hardware Efficient Logarithmic Multiplier. Circuits Syst. Signal Process. 41(1): 485-513 (2022) - [j8]Chinthalgiri Jyothi, Saranya Karunamurthi, Bhaskara Rao Jammu, Sreehari Veeramachaneni, Sk. Noor Mahammad:
A New Approximate 4-2 Compressor using Merged Sum and Carry. J. Electron. Test. 38(4): 381-394 (2022) - [j7]Bhaskara Rao Jammu, L. Guna Sekhar Sai Harsha, Nalini Bodasingi, Sreehari Veeramachaneni, Noor Mohammad S.:
Hardware efficient circuit for low error logarithmic converter. J. Comput. Methods Sci. Eng. 22(2): 511-527 (2022) - [c30]Sandeep Kolla, Ayesha Sk, Sreehari Veeramachaneni, Sk. Noor Mahammad:
Logic Locking Designs at Transistor Level for Full Adders. iSES 2022: 289-292 - 2021
- [j6]Y. Mounica, K. Naresh Kumar, Sreehari Veeramachaneni, S. K. Noor Mahammad:
Energy efficient signed and unsigned radix 16 booth multiplier design. Comput. Electr. Eng. 90: 106892 (2021) - [j5]L. Hemanth Krishna, Neeharika M., Vishvanath Janjirala, Sreehari Veeramachaneni, S. K. Noor Mahammad:
Efficient design of 15: 4 counter using a novel 5: 3 counter for high-speed multiplication. IET Comput. Digit. Tech. 15(1): 12-19 (2021) - [j4]L. Guna Sekhar Sai Harsha, Bhaskara Rao Jammu, Visweswara Rao Samoju, Sreehari Veeramachaneni, Noor Mohammad S.:
A low-error, memory-based fast binary antilogarithmic converter. Int. J. Circuit Theory Appl. 49(7): 2214-2226 (2021) - [c29]L. Hemanth Krishna, J. Bhaskara Rao, Ayesha Sk, Sreehari Veeramachaneni, S. K. Noor Mahammad:
Energy Efficient Approximate 4: 2 Compressors for Error Tolerant Applications. ICECS 2021: 1-6 - [c28]Sandeep Kolla, Ayesha Sk, Sreehari Veeramachaneni, Sk. Noor Mahammad:
Design and Analysis of Obfuscated Full Adders. ICM 2021: 49-52 - [c27]L. Hemanth Krishna, J. Bhaskara Rao, Ayesha Sk, Sreehari Veeramachaneni, Sk. Noor Mahammad:
Energy Efficient Approximate Multiplier Design for Image/Video Processing Applications. iSES 2021: 210-215 - 2020
- [j3]Chandana Mounica, Sagar Krishna, Sreehari Veeramachaneni, Sk. Noor Mahammad:
Efficient implementation of mixed-precision multiply-accumulator unit for AI algorithms. Int. J. Circuit Theory Appl. 48(8): 1386-1394 (2020)
2010 – 2019
- 2018
- [c26]Mahesh Kumar Adimulam, Amit Kapoor, Sreehari Veeramachaneni, M. B. Srinivas:
An Ultra Low Power, 10-Bit Two-Step Flash ADC for Signal Processing Applications. VLSID 2018: 19-24 - 2014
- [c25]Subhankar Pal, Chetan Vudadha, P. Sai Phaneendra, Sreehari Veeramachaneni, Srinivas B. Mandalika:
A New Design of an N-Bit Reversible Arithmetic Logic Unit. ISED 2014: 224-225 - [c24]B. Naveen Kumar Reddy, M. Chandra Sekhar, Sreehari Veeramachaneni, M. B. Srinivas:
A Novel Low Power Error Detection Logic for Inexact Leading Zero Anticipator in Floating Point Units. VLSID 2014: 128-132 - [c23]P. Sai Phaneendra, Chetan Vudadha, Sreehari Veeramachaneni, M. B. Srinivas:
An Optimized Design of Reversible Quantum Comparator. VLSID 2014: 557-562 - 2012
- [c22]Chetan Vudadha, Phaneendra P. Sai, Sreehari Veeramachaneni, M. B. Srinivas:
CNFET based ternary magnitude comparator. ISCIT 2012: 942-946 - [c21]Syed Ershad Ahmed, Sibi Abraham, Sreehari Veeramachaneni, N. Moorthy Muthukrishnan, M. B. Srinivas:
A Modified Twin Precision Multiplier with 2D Bypassing Technique. ISED 2012: 102-106 - [c20]Chetan Vudadha, P. Sai Phaneendra, Sreehari Veeramachaneni, Syed Ershad Ahmed, N. Moorthy Muthukrishnan, Mandalika B. Srinivas:
Design of Prefix-Based Optimal Reversible Comparator. ISVLSI 2012: 201-206 - [c19]Chetan Vudadha, P. Sai Phaneendra, Syed Ershad Ahmed, Sreehari Veeramachaneni, N. Moorthy Muthukrishnan, Mandalika B. Srinivas:
Design and Analysis of Reversible Ripple, Prefix and Prefix-Ripple Hybrid Adders. ISVLSI 2012: 225-230 - [c18]Chetan Vudadha, Goutham Makkena, M. Venkata Swamy Nayudu, P. Sai Phaneendra, Syed Ershad Ahmed, Sreehari Veeramachaneni, N. Moorthy Muthukrishnan, M. B. Srinivas:
Low-Power Self Reconfigurable Multiplexer Based Decoder for Adaptive Resolution Flash ADCs. VLSI Design 2012: 280-285 - 2011
- [c17]Chetan Kumar V., P. Sai Phaneendra, Syed Ershad Ahmed, Sreehari Veeramachaneni, N. Moorthy Muthukrishnan, M. B. Srinivas:
A Unified Architecture for BCD and Binary Adder/Subtractor. DSD 2011: 426-429 - [c16]P. Sai Phaneendra, Chetan Vudadha, Syed Ershad Ahmed, Sreehari Veeramachaneni, N. Moorthy Muthukrishnan, M. B. Srinivas:
Increment/decrement/2's complement/priority encoder circuit for varying operand lengths. ISCIT 2011: 472-477 - [c15]Mahesh Kumar Adimulam, Krishna Kumar Movva, Sreehari Veeramachaneni, N. Moorthy Muthukrishnan, M. B. Srinivas:
A Multiple-Bandwidth 10-bit SAR Analog to Digital Converter. ISED 2011: 24-29 - [c14]Chetan Kumar V., P. Sai Phaneendra, Syed Ershad Ahmed, Sreehari Veeramachaneni, N. Moorthy Muthukrishnan, M. B. Srinivas:
A Reconfigurable INC/DEC/2's Complement/Priority Encoder Circuit with Improved Decision Block. ISED 2011: 100-105 - [c13]Chetan Kumar V., Sai Phaneendra P., Syed Ershad Ahmed, Sreehari Veeramachaneni, N. Moorthy Muthukrishnan, M. B. Srinivas:
A Prefix Based Reconfigurable Adder. ISVLSI 2011: 349-350 - 2010
- [j2]Sandeep Saini, A. Mahesh Kumar, Sreehari Veeramachaneni, M. B. Srinivas:
An Alternate Approach to Buffer Insertion for Delay and Power Reduction in VLSI Interconnects. J. Low Power Electron. 6(3): 429-435 (2010) - [c12]Mahesh Kumar Adimulam, Krishna Kumar Movva, Sreehari Veeramachaneni, N. Moorthy Muthukrishnan, Mandalika B. Srinivas:
Low power, variable resolution pipelined analog to Digital converter with sub flash architecture. APCCAS 2010: 204-207 - [c11]Mahesh Kumar Adimulam, Krishna Kumar Movva, Sreehari Veeramachaneni, N. Moorthy Muthukrishnan, M. B. Srinivas:
A low power, variable resolution two-step flash ADC. ACM Great Lakes Symposium on VLSI 2010: 39-44 - [c10]Mahesh Kumar Adimulam, Sreehari Veeramachaneni, N. Moorthy Muthukrishnan, M. B. Srinivas:
A Novel, Variable Resolution Flash ADC with Sub Flash Architecture. ISVLSI 2010: 434-435 - [c9]Sandeep Saini, Mahesh Kumar Adimulam, Sreehari Veeramachaneni, M. B. Srinivas:
An Alternative approach to Buffer Insertion for Delay and Power Reduction in VLSI Interconnects. VLSI Design 2010: 411-416
2000 – 2009
- 2009
- [j1]Mahesh Kumar Adimulam, Sreehari Veeramachaneni, M. B. Srinivas:
A Novel Low Power, Variable Resolution Flash Analog-to-Digital Converter. J. Low Power Electron. 5(3): 279-290 (2009) - [c8]Anshul Singh, Aman Gupta, Sreehari Veeramachaneni, M. B. Srinivas:
A High Performance Unified BCD and Binary Adder/Subtractor. ISVLSI 2009: 211-216 - [c7]Mahesh Kumar Adimulam, Sreehari Veeramachaneni, M. B. Srinivas:
A novel low power, variable resolution pipelined ADC. SoCC 2009: 183-186 - [c6]Sreehari Veeramachaneni, Mahesh Kumar Adimulam, Venkat Tummala, M. B. Srinivas:
Design of a Low Power, Variable-Resolution Flash ADC. VLSI Design 2009: 117-122 - 2008
- [c5]Sreehari Veeramachaneni, Kirthi M. Krishna, Prateek G. V., Subroto S., Bharat S., M. B. Srinivas:
A Novel Carry-Look Ahead Approach to a Unified BCD and Binary Adder/Subtractor. VLSI Design 2008: 547-552 - 2007
- [c4]Sreehari Veeramachaneni, Lingamneni Avinash, Kirthi M. Krishna, M. B. Srinivas:
Novel architectures for efficient (m, n) parallel counters. ACM Great Lakes Symposium on VLSI 2007: 188-191 - [c3]Sreehari Veeramachaneni, Kirthi M. Krishna, Lingamneni Avinash, Reddy Puppala Sreekanth, M. B. Srinivas:
Novel High-Speed Redundant Binary to Binary converter using Prefix Networks. ISCAS 2007: 3271-3274 - [c2]Sreehari Veeramachaneni, Kirthi M. Krishna, Lingamneni Avinash, Reddy Puppala Sreekanth, M. B. Srinivas:
Novel, High-Speed 16-Digit BCD Adders Conforming to IEEE 754r Format. ISVLSI 2007: 343-350 - [c1]Sreehari Veeramachaneni, Kirthi M. Krishna, Lingamneni Avinash, Reddy Puppala Sreekanth, M. B. Srinivas:
Novel Architectures for High-Speed and Low-Power 3-2, 4-2 and 5-2 Compressors. VLSI Design 2007: 324-329
Coauthor Index
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last updated on 2024-11-25 23:40 CET by the dblp team
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