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2020 – today
- 2023
[j8]Zixin Cai
, Xin He, Xin Liu, Shijie Tu, Xinjie Sun, Paul Beckett, Aditya Dubey, Arnan Mitchell, Guanghui Ren, Xu Liu, Xiang Hao:
Wavelength-selective wavefront shaping by metasurface. Frontiers Inf. Technol. Electron. Eng. 24(4): 617-625 (2023)- 2022
- [c26]Nguyen Le Huy, Paul Beckett:
Optimising Power-Performance in SOI-based Null Convention Logic. ICICDT 2022: 32-35
2010 – 2019
- 2019
- [c25]Abdur Rahim Mohammad Forkan, Flora D. Salim, Russell Conduit, Paul Beckett, Stephen R. Robinson:
TIARA: technology integrated apnea respiration analyser. UbiComp 2019: 169-171 - 2018
- [j7]Nastaran Nemati, Paul Beckett, Mark C. Reed, Karl M. Fant:
Clock-Less DFT-Less Test Strategy for Null Convention Logic. IEEE Trans. Emerg. Top. Comput. 6(4): 460-473 (2018) - [j6]Jeeson Kim, Taimur Ahmed, Hussein Nili, Jiawei Yang, Doo Seok Jeong, Paul Beckett, Sharath Sriram, Damith Chinthana Ranasinghe, Omid Kavehei:
A Physical Unclonable Function With Redox-Based Nanoionic Resistive Memory. IEEE Trans. Inf. Forensics Secur. 13(2): 437-448 (2018) - [c24]Tayab Din Memon, Aneela Pathan, Paul Beckett:
FPGA Based Implementation and Area Performance Analysis of Sigma-Delta Modulated Steepest Algorithm for Channel Equalization. ICSPCS 2018: 1-6 - 2017
- [c23]Andrew Przybylski, Kashfia Haque, Paul Beckett:
The Bel array: asynchronous fine-grained reconfigurable co-processing. ACSW 2017: 45:1-45:4 - [c22]Peter J. Radcliffe, Karina Gomez Chavez, Paul Beckett, Justin Spangaro, Conrad Jakob:
Usability of LoRaWAN Technology in a Central Business District. VTC Spring 2017: 1-5 - 2016
- [c21]Leah Heiss, Paul Beckett, Amy Carr-Bottomley:
Redesigning the Trans-disciplinary: Working Across Design, Craft and Technological Boundaries to Deliver an Integrated Wearable for Cardiac Monitoring. Conference on Designing Interactive Systems 2016: 691-699 - [c20]Prashant Dabholkar, Paul Beckett:
A high throughput, low latency null convention logic 16×16-bit multiplier. ICSPCS 2016: 1-8 - [c19]Andrew Przybylski, Kashfia Haque, Paul Beckett:
The Bel array: An asynchronous fine-grained co-processor for DSP. ICSPCS 2016: 1-7 - [c18]Renuka Sovani, Prashant Dabholkar, Paul Beckett:
An asynchronous short word length Delta-Sigma FIR filter for low power DSP. ICSPCS 2016: 1-7 - [c17]Nastaran Nemati, Mark C. Reed, Karl M. Fant, Paul Beckett:
Asynchronous interleaved scan architecture for on-line built-in self-test of null convention logic. ISCAS 2016: 746-749 - [c16]Prashant Dabholkar, Renuka Sovani, Paul Beckett:
A low latency asynchronous Jenkins hash engine for IP lookup. ISCAS 2016: 2663-2666 - [i1]Jeeson Kim, Taimur Ahmed, Hussein Nili, Jiawei Yang, Doo Seok Jeong, Paul Beckett, Sharath Sriram, Damith Chinthana Ranasinghe, Omid Kavehei:
A Physical Unclonable Function with Redox-based Nanoionic Resistive Memory. CoRR abs/1611.04665 (2016) - 2015
- [c15]Kashfia Haque, Conrad Jakob, Paul Beckett:
Low Power Spatial Computing Using Null Convention Logic. DSDIS 2015: 325-329 - [c14]Matthew M. Kim, Karl M. Fant, Paul Beckett:
Design of asynchronous RISC CPU register-file Write-Back queue. VLSI-SoC 2015: 31-36 - 2014
- [j5]Kashfia Haque, Paul Beckett:
Radiation-Hard Field-Programmable Gate Arrays Configuration Technique Using Silicon on Sapphire. IEEE Trans. Very Large Scale Integr. Syst. 22(2): 232-241 (2014) - [c13]Matthew M. Kim, Paul Beckett:
Design Techniques for NCL-Based Asynchronous Circuits on Commercial FPGA. DSD 2014: 451-458 - [c12]Jing Yu, Paul Beckett:
A dual-rail LUT for reconfigurable logic using null convention logic. ACM Great Lakes Symposium on VLSI 2014: 261-266 - 2013
- [j4]Tayab Din Memon, Paul Beckett, Amin Z. Sadik:
POWER-Area-Performance Characteristics of FPGA-based Sigma-Delta FIR Filters. J. Signal Process. Syst. 70(3): 275-288 (2013) - 2012
- [j3]Paul Beckett, Tayab Din Memon:
Reconfigurable Blocks Based on Balanced Ternary. J. Signal Process. Syst. 67(1): 3-13 (2012) - 2011
- [c11]Kashfia Haque, Paul Beckett:
A Radiation Hard Lut Block with Auto-Scrubbing. FPL 2011: 441-446 - [c10]Kashfia Haque, Paul Beckett:
A SOI EEPROM Based Configuration Cell with Simple Scrubbing Detection. VLSI Design 2011: 24-29 - 2010
- [c9]Paul Beckett, Heiko Rudolph:
Run. DELTA 2010: 245-249
2000 – 2009
- 2009
- [j2]Paul Beckett:
Power scalability in a mesh-connected reconfigurable architecture. ACM Trans. Embed. Comput. Syst. 9(2): 13:1-13:28 (2009) - [c8]Paul Beckett:
Towards a balanced ternary FPGA. FPT 2009: 46-53 - 2008
- [j1]Paul Beckett:
A Low-Power Reconfigurable Logic Array Based on Double-Gate Transistors. IEEE Trans. Very Large Scale Integr. Syst. 16(2): 115-123 (2008) - 2007
- [c7]Lianlian Zeng, Paul Beckett:
Soft Error Rate Estimation in Deep Sub-micron CMOS. PRDC 2007: 210-216 - 2005
- [c6]Paul Beckett:
Low-power circuits using dynamic threshold devices. ACM Great Lakes Symposium on VLSI 2005: 213-216 - [c5]Paul Beckett, Seth Copen Goldstein:
Why area might reduce power in nanoscale CMOS. ISCAS (3) 2005: 2329-2332 - [c4]Paul Beckett:
Low-power spatial computing using dynamic threshold devices. ISCAS (3) 2005: 2345-2348 - 2003
- [c3]Paul Beckett:
Exploiting multiple functionality for nano-scale reconfigurable systems. ACM Great Lakes Symposium on VLSI 2003: 50-55 - [c2]Paul Beckett:
A Polymorphic Hardware Platform. IPDPS 2003: 175 - 2002
- [c1]Paul Beckett:
A fine-grained reconfigurable logic array based on double gate transistors. FPT 2002: 260-267
Coauthor Index
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last updated on 2024-04-24 22:52 CEST by the dblp team
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