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2020 – today
- 2023
[c44]Hyun-Joon Nam, Hong-June Park:
Pitch Mark Detection from Noisy Speech Waveform Using Wave-U-Net. ICASSP 2023: 1-5- 2021
- [j80]Sooeun Lee
, Jaeyoung Seo, Changyoon Han, Jae-Yoon Sim, Hong-June Park, Byungsub Kim:
A DFE-Enhanced Phase-Difference Modulation Signaling for Multi-Drop Memory Interfaces. IEEE Trans. Circuits Syst. II Express Briefs 68(6): 1862-1866 (2021) - [j79]Min-Kyun Chae, Hye-Jung Kwon, Seung-Jun Bae, Nam-Jong Kim, Hong-June Park:
A Duo-Binary Transceiver With Time-Based Receiver and Voltage-Mode Time-Interleaved Mixing Transmitter for DRAM Interface. IEEE Trans. Circuits Syst. II Express Briefs 68(7): 2409-2413 (2021) - 2020
- [j78]Ji-Hoon Lee, Jaehyun Ko, Kwangmin Kim, Minsoo Choi, Jae-Yoon Sim, Hong-June Park, Byungsub Kim:
A Body Channel Communication Technique Utilizing Decision Feedback Equalization. IEEE Access 8: 198468-198481 (2020) - [j77]Jaehyeong Hong, Dong Hoon Baek, Hyunwoo Son, Cheolmin Ahn, Byungsub Kim, Hong-June Park, Jae-Yoon Sim:
A pattern-dependent injection-locked CDR for clock-embedded signaling. Microelectron. J. 96: 104708 (2020) - [j76]Sooeun Lee, Jaeyoung Seo, Kyunghyun Lim, Jahyun Koo, Jae-Yoon Sim, Hong-June Park, Byungsub Kim:
A 7.8 Gb/s/pin, 1.96 pJ/b Transceiver With Phase-Difference-Modulation Signaling for Highly Reflective Interconnects. IEEE Trans. Circuits Syst. I Regul. Pap. 67-I(6): 2114-2127 (2020) - [j75]Seong-Eun Cho, Byungsub Kim, Jae-Yoon Sim, Hong-June Park:
Low-Power Small-Area Inverter-Based DSM for MEMS Microphone. IEEE Trans. Circuits Syst. 67-II(11): 2392-2396 (2020) - [j74]Cheolmin Ahn, Jaehyeong Hong, Jongshin Shin, Byungsub Kim, Hong-June Park, Jae-Yoon Sim:
An 18-Gb/s NRZ Transceiver With a Channel-Included 2-UI Impulse-Response Filtering FFE and 1-Tap DFE Compensating up to 32-dB Loss. IEEE Trans. Circuits Syst. 67-II(12): 2863-2867 (2020) - [j73]Jaeyoung Seo, Jaehyun Ko, Kyunghyun Lim, Sooeun Lee, Jae-Yoon Sim, Hong-June Park, Byungsub Kim:
A 7.8-Gb/s 2.9-pJ/b Single-Ended Receiver With 20-Tap DFE for Highly Reflective Channels. IEEE Trans. Very Large Scale Integr. Syst. 28(3): 818-822 (2020) - [c43]Seungho Han, Sungyu Jeong, Chanho Kim, Hong-June Park, Byungsub Kim:
GUI-Enhanced Layout Generation of FFE SST TXs for Fast High-Speed Serial Link Design. DAC 2020: 1-6
2010 – 2019
- 2019
- [j72]Minseob Lee, Shinwoong Kim, Hong-June Park, Jae-Yoon Sim:
A 0.0043-mm2 0.3-1.2-V Frequency-Scalable Synthesized Fractional-N Digital PLL With a Speculative Dual-Referenced Interpolating TDC. IEEE J. Solid State Circuits 54(1): 99-108 (2019) - [j71]Hong-June Park, Jae-Yoon Sim, Robert Chen-Hao Chang:
Introduction to the Special Section on the 2018 Asian Solid-State Circuits Conference (A-SSCC). IEEE J. Solid State Circuits 54(10): 2635-2636 (2019) - [j70]Youngwoo Ji, Jungho Lee, Byungsub Kim, Hong-June Park, Jae-Yoon Sim:
A 192-pW Voltage Reference Generating Bandgap- $V_{\text{th}}$ With Process and Temperature Dependence Compensation. IEEE J. Solid State Circuits 54(12): 3281-3291 (2019) - [j69]Hyunwoo Son, Hwasuk Cho, Jungho Lee, Seongun Bae, Byungsub Kim, Hong-June Park, Jae-Yoon Sim:
A Multilayer-Learning Current-Mode Neuromorphic System With Analog-Error Compensation. IEEE Trans. Biomed. Circuits Syst. 13(5): 986-998 (2019) - [j68]Jahyun Koo, Byungsub Kim, Hong-June Park, Jae-Yoon Sim:
A Quadrature RC Oscillator With Noise Reduction by Voltage Swing Control. IEEE Trans. Circuits Syst. I Regul. Pap. 66-I(8): 3077-3088 (2019) - [c42]Youngwoo Ji, Jungho Lee, Byungsub Kim, Hong-June Park, Jae-Yoon Sim:
A 192pW Hybrid Bandgap-Vth Reference with Process Dependence Compensated by a Dimension-Induced Side-Effect. ISSCC 2019: 308-310 - [c41]Cheonhoo Jeon, Jahyun Koo, Kyongsu Lee, Su-Kyoung Kim, Sei Kwang Hahn, Byungsub Kim, Hong-June Park, Jae-Yoon Sim:
A 143nW Glucose-Monitoring Smart Contact Lens IC with a Dual-Mode Transmitter for Wireless-Powered Backscattering and RF-Radiated Transmission Using a Single Loop Antenna. VLSI Circuits 2019: 294- - 2018
- [j67]Il-Min Yi, Min-Kyun Chae, Seok-Hun Hyun, Seung-Jun Bae, Jung-Hwan Choi, Seong-Jin Jang, Byungsub Kim, Jae-Yoon Sim, Hong-June Park:
A Time-Based Receiver With 2-Tap Decision Feedback Equalizer for Single-Ended Mobile DRAM Interface. IEEE J. Solid State Circuits 53(1): 144-154 (2018) - [j66]Seungnam Choi, Hwan-Seok Ku, Hyunwoo Son, Byungsub Kim, Hong-June Park, Jae-Yoon Sim:
An 84.6-dB-SNDR and 98.2-dB-SFDR Residue-Integrated SAR ADC for Low-Power Sensor Applications. IEEE J. Solid State Circuits 53(2): 404-417 (2018) - [j65]Minsoo Choi, Sooeun Lee, Myungguk Lee, Ji-Hoon Lee, Jae-Yoon Sim, Hong-June Park, Byungsub Kim:
An FFE Transmitter Which Automatically and Adaptively Relaxes Impedance Matching. IEEE J. Solid State Circuits 53(6): 1780-1792 (2018) - [j64]Hwasuk Cho, Hyunwoo Son, Kihwan Seong, Byungsub Kim, Hong-June Park, Jae-Yoon Sim:
An On-Chip Learning Neuromorphic Autoencoder With Current-Mode Transposable Memory Read and Virtual Lookup Table. IEEE Trans. Biomed. Circuits Syst. 12(1): 161-170 (2018) - [j63]Youngwoo Ji, Byungsub Kim, Hong-June Park, Jae-Yoon Sim:
A Study on Bandgap Reference Circuit With Leakage-Based PTAT Generation. IEEE Trans. Very Large Scale Integr. Syst. 26(11): 2310-2321 (2018) - [j62]Kwangmin Kim, Seokjoon Kang, Jae-Yoon Sim, Hong-June Park, Byungsub Kim:
A Search Algorithm for the Worst Operation Scenario of a Cross-Point Phase-Change Memory Utilizing Particle Swarm Optimization. IEEE Trans. Very Large Scale Integr. Syst. 26(12): 2591-2598 (2018) - [c40]Youngwoo Ji, Cheonhoo Jeon, Hyunwoo Son, Byungsub Kim, Hong-June Park, Jae-Yoon Sim:
A 9.3 nW all-in-one bandgap voltage and current reference circuit using leakage-based PTAT generation and DIBL characteristic. ASP-DAC 2018: 309-310 - [c39]Ji-Hoon Lee, Kwangmin Kim, Minsoo Choi, Jae-Yoon Sim, Hong-June Park, Byungsub Kim:
A 16.6-pJ/b 150-Mb/s body-channel communication transceiver with decision feedback equalization improving >200x area efficiency. ASP-DAC 2018: 311-312 - [c38]Hyunwoo Son, Hwasuk Cho, Jahyun Koo, Youngwoo Ji, Byungsub Kim, Hong-June Park, Jae-Yoon Sim:
A low-power wide dynamic-range current readout circuit for biosensors. ASP-DAC 2018: 325-326 - [c37]Minseob Lee, Shinwoong Kim, Hwasuk Cho, Jahyun Koo, Kwang-Hee Choi, Jin-Hyeok Choi, Byungsub Kim, Hong-June Park, Jae-Yoon Sim:
A 0.3-to-1.2V frequency-scalable fractional-N ADPLL with a speculative dual-referenced interpolating TDC. ISSCC 2018: 122-124 - [c36]Sooeun Lee, Jaeyoung Seo, Kyunghyun Lim, Jaehyun Ko, Jae-Yoon Sim, Hong-June Park, Byungsub Kim:
A 7.8Gb/s/pin 1.96pJ/b compact single-ended TRX and CDR with phase-difference modulation for highly reflective memory interfaces. ISSCC 2018: 272-274 - 2017
- [j61]Yoon-Jee Kim, Sung-Eun Cho, Ji-Yong Um, Min-Kyun Chae, Jihoon Bang, Jongkeun Song, Taeho Jeon, Byungsub Kim, Jae-Yoon Sim, Hong-June Park:
A Single-Chip 64-Channel Ultrasound RX-Beamformer Including Analog Front-End and an LUT for Non-Uniform ADC-Sample-Clock Generation. IEEE Trans. Biomed. Circuits Syst. 11(1): 87-97 (2017) - [j60]Hyunwoo Son, Hwasuk Cho, Jahyun Koo, Youngwoo Ji, Byungsub Kim, Hong-June Park, Jae-Yoon Sim:
A Low-Power Wide Dynamic-Range Current Readout Circuit for Ion-Sensitive FET Sensors. IEEE Trans. Biomed. Circuits Syst. 11(3): 523-533 (2017) - [j59]Seunghwan Hong, Shinwoong Kim, Seungnam Choi, Hwasuk Cho, Jaehyeong Hong, Young Hun Seo, Byungsub Kim, Hong-June Park, Jae-Yoon Sim:
A 250-µW 2.4-GHz Fast-Lock Fractional-N Frequency Generation for Ultralow-Power Applications. IEEE Trans. Circuits Syst. II Express Briefs 64-II(2): 106-110 (2017) - [j58]Young-Ho Choi, Byungsub Kim, Jae-Yoon Sim, Hong-June Park:
A Phase-Interpolator-Based Fractional Counter for All-Digital Fractional-N Phase-Locked Loop. IEEE Trans. Circuits Syst. II Express Briefs 64-II(3): 249-253 (2017) - [j57]Seungnam Choi, Yunjae Suh, Joohyun Lee, Jinkyu Kim, Byungsub Kim, Hong-June Park, Jae-Yoon Sim:
A Self-Biased Current-Mode Amplifier With an Application to 10-bit Pipeline ADC. IEEE Trans. Circuits Syst. I Regul. Pap. 64-I(7): 1706-1717 (2017) - [j56]Jaeyoung Seo, Minsoo Choi, Sanquan Song, Jae-Yoon Sim, Hong-June Park, Byungsub Kim:
An Approximate Transfer Function Model of Two Serially Connected Heterogeneous Transmission Lines. IEEE Trans. Circuits Syst. II Express Briefs 64-II(9): 1067-1071 (2017) - [j55]Kihwan Seong, Won-Cheol Lee, Byungsub Kim, Jae-Yoon Sim, Hong-June Park:
All-Synthesizable Current-Mode Transmitter Driver for USB2.0 Interface. IEEE Trans. Very Large Scale Integr. Syst. 25(2): 788-792 (2017) - [j54]Yelim Youn, Kwangmin Kim, Jae-Yoon Sim, Hong-June Park, Byungsub Kim:
Investigation on the Worst Read Scenario of a ReRAM Crossbar Array. IEEE Trans. Very Large Scale Integr. Syst. 25(9): 2402-2410 (2017) - [c35]Myungguk Lee, Seungho Han, Jae-Yoon Sim, Hong-June Park, Byungsub Kim:
A 10-GHz multi-purpose reconfigurable built-in self-test circuit for high-speed links. A-SSCC 2017: 73-76 - [c34]Jahyun Koo, Kyoung-Sik Moon, Byungsub Kim, Hong-June Park, Jae-Yoon Sim:
5.5 A quadrature relaxation oscillator with a process-induced frequency-error compensation loop. ISSCC 2017: 94-95 - [c33]Youngwoo Ji, Cheonhoo Jeon, Hyunwoo Son, Byungsub Kim, Hong-June Park, Jae-Yoon Sim:
5.8 A 9.3nW all-in-one bandgap voltage and current reference circuit. ISSCC 2017: 100-101 - [c32]Hwasuk Cho, Kihwan Seong, Kwang-Hee Choi, Jin-Hyeok Choi, Byungsub Kim, Hong-June Park, Jae-Yoon Sim:
8.7 A 0.0047mm2 highly synthesizable TDC- and DCO-less fractional-N PLL with a seamless lock range of fREF to 1GHz. ISSCC 2017: 154-155 - [c31]Il-Min Yi, Min-Kyun Chae, Seok-Hun Hyun, Seung-Jun Bae, Jung-Hwan Choi, Seong-Jin Jang, Byungsub Kim, Jae-Yoon Sim, Hong-June Park:
23.7 A time-based receiver with 2-tap DFE for a 12Gb/s/pin single-ended transceiver of mobile DRAM interface in 0.8V 65nm CMOS. ISSCC 2017: 400-401 - 2016
- [j53]Dong-Woo Jee, Yunjae Suh, Hong-June Park, Jae-Yoon Sim:
A Digitally Controlled Op-Amp with Level-Crossing-Based Approximation and its Application to a 10-bit Pipeline ADC. J. Circuits Syst. Comput. 25(12): 1650155:1-1650155:16 (2016) - [j52]Shinwoong Kim, Seunghwan Hong, Kapseok Chang, Hyungsik Ju, Jaewook Shin, Byungsub Kim, Hong-June Park, Jae-Yoon Sim:
A 2 GHz Synthesized Fractional-N ADPLL With Dual-Referenced Interpolating TDC. IEEE J. Solid State Circuits 51(2): 391-400 (2016) - [j51]Soo-Min Lee, Ji-Hoon Lim, Il-Min Yi, Young Jae Jang, Hae-Kang Jung, Kyunghoon Kim, Dae-Han Kwon, Byungsub Kim, Jae-Yoon Sim, Hong-June Park:
A Single-Ended Parallel Transceiver With Four-Bit Four-Wire Four-Level Balanced Coding for the Point-to-Point DRAM Interface. IEEE J. Solid State Circuits 51(8): 1890-1901 (2016) - [j50]Seungho Han, Sooeun Lee, Minsoo Choi, Jae-Yoon Sim, Hong-June Park, Byungsub Kim:
A Coefficient-Error-Robust Feed-Forward Equalizing Transmitter for Eye-Variation and Power Improvement. IEEE J. Solid State Circuits 51(8): 1902-1914 (2016) - [j49]Il-Min Yi, Soo-Min Lee, Seung-Jun Bae, Young-Soo Sohn, Jung-Hwan Choi, Seong-Jin Jang, Byungsub Kim, Jae-Yoon Sim, Hong-June Park:
A 40 mV-Differential-Channel-Swing Transceiver Using a RX Current-Integrating TIA and a TX Pre-Emphasis Equalizer With a CML Driver at 9 Gb/s. IEEE Trans. Circuits Syst. I Regul. Pap. 63-I(1): 122-133 (2016) - [j48]Ji-Hoon Lim, Jun-Hyun Bae, Jaemin Jang, Hae-Kang Jung, Hyunbae Lee, Yongju Kim, Byungsub Kim, Jae-Yoon Sim, Hong-June Park:
A Delay Locked Loop With a Feedback Edge Combiner of Duty-Cycle Corrector With a 20%-80% Input Duty Cycle for SDRAMs. IEEE Trans. Circuits Syst. II Express Briefs 63-II(2): 141-145 (2016) - [j47]Seungnam Choi, Hyunwoo Son, Jongshin Shin, Sang-Hyun Lee, Byungsub Kim, Hong-June Park, Jae-Yoon Sim:
A 0.65-to-10.5 Gb/s Reference-Less CDR With Asynchronous Baud-Rate Sampling for Frequency Acquisition and Adaptive Equalization. IEEE Trans. Circuits Syst. I Regul. Pap. 63-I(2): 276-287 (2016) - [c30]Young Jae Jang, Seong-Eun Cho, Byungsub Kim, Jae-Yoon Sim, Hong-June Park:
A low-power LDO circuit with a fast load regulation. APCCAS 2016: 47-49 - [c29]Young-Ho Choi, Kihwan Seong, Byungsub Kim, Jae-Yoon Sim, Hong-June Park:
All-synthesizable 6Gbps voltage-mode transmitter for serial link. A-SSCC 2016: 245-248 - [c28]Kihwan Seong, Won-Cheol Lee, Byungsub Kim, Jae-Yoon Sim, Hong-June Park:
All-synthesizable transmitter driver and data recovery circuit for USB2.0 interface. ISOCC 2016: 63-64 - [c27]Il-Min Yi, Seung-Jun Bae, Min-Kyun Chae, Soo-Min Lee, Young Jae Jang, Young-Chul Cho, Young-Soo Sohn, Jung-Hwan Choi, Seong-Jin Jang, Byungsub Kim, Jae-Yoon Sim, Hong-June Park:
A low-EMI four-bit four-wire single-ended DRAM interface by using a three-level balanced coding scheme. VLSI Circuits 2016: 1-2 - 2015
- [j46]Ji-Yong Um, Yoon-Jee Kim, Seong-Eun Cho, Min-Kyun Chae, Byungsub Kim, Jae-Yoon Sim, Hong-June Park:
A Single-Chip 32-Channel Analog Beamformer With 4-ns Delay Resolution and 768-ns Maximum Delay Range for Ultrasound Medical Imaging With a Linear Array Transducer. IEEE Trans. Biomed. Circuits Syst. 9(1): 138-151 (2015) - [j45]Minsoo Choi, Jae-Yoon Sim, Hong-June Park, Byungsub Kim:
An Approximate Closed-Form Transfer Function Model for Diverse Differential Interconnects. IEEE Trans. Circuits Syst. I Regul. Pap. 62-I(5): 1335-1344 (2015) - [c26]Sooeun Lee, Gunbok Lee, Jae-Yoon Sim, Hong-June Park, Wee Sang Park, Byungsub Kim:
A Sample Reduction Technique by Aliasing Channel Response for Fast Equalizing Transceiver Design. ICCAD 2015: 567-574 - [c25]Jongmi Lee, Youngwoo Ji, Seungnam Choi, Young-Chul Cho, Seong-Jin Jang, Joo-Sun Choi, Byungsub Kim, Hong-June Park, Jae-Yoon Sim:
5.7 A 29nW bandgap reference circuit. ISSCC 2015: 1-3 - 2014
- [j44]Seung-Hun Lee, Seon-Kyoo Lee, Byungsub Kim, Hong-June Park, Jae-Yoon Sim:
Current-Mode Transceiver for Silicon Interposer Channel. IEEE J. Solid State Circuits 49(9): 2044-2053 (2014) - [j43]Soo-Min Lee, Il-Min Yi, Hae-Kang Jung, Hyunbae Lee, Yong-Ju Kim, Yunsaing Kim, Byungsub Kim, Jae-Yoon Sim, Hong-June Park:
An 80 mV-Swing Single-Ended Duobinary Transceiver With a TIA RX Termination for the Point-to-Point DRAM Interface. IEEE J. Solid State Circuits 49(11): 2618-2630 (2014) - [j42]Ji-Yong Um, Yoon-Jee Kim, Seong-Eun Cho, Min-Kyun Chae, Jongkeun Song, Bae-Hyung Kim, Seung-Hun Lee, Jihoon Bang, Youngil Kim, Kyungil Cho, Byungsub Kim, Jae-Yoon Sim, Hong-June Park:
An Analog-Digital Hybrid RX Beamformer Chip With Non-Uniform Sampling for Ultrasound Medical Imaging With 2D CMUT Array. IEEE Trans. Biomed. Circuits Syst. 8(6): 799-809 (2014) - [j41]Hye-Jung Kwon, Jae-Seung Lee, Byungsub Kim, Jae-Yoon Sim, Hong-June Park:
Analysis of an Open-Loop Time Amplifier With a Time Gain Determined by the Ratio of Bias Current. IEEE Trans. Circuits Syst. II Express Briefs 61-II(7): 481-485 (2014) - [j40]Minsoo Choi, Jae-Yoon Sim, Hong-June Park, Byungsub Kim:
An Approximate Closed-Form Channel Model for Diverse Interconnect Applications. IEEE Trans. Circuits Syst. I Regul. Pap. 61-I(10): 3034-3043 (2014) - [j39]Hyunsoo Ha, Seon-Kyoo Lee, Byungsub Kim, Hong-June Park, Jae-Yoon Sim:
A 0.5-V, 1.47- µW 40-kS/s 13-bit SAR ADC With Capacitor Error Compensation. IEEE Trans. Circuits Syst. II Express Briefs 61-II(11): 840-844 (2014) - [j38]Il-Min Yi, Soo-Min Lee, Seung-Jun Bae, Young-Soo Sohn, Jung-Hwan Choi, Byungsub Kim, Jae-Yoon Sim, Hong-June Park:
A 40-mV-Swing Single-Ended Transceiver for TSV with a Switched-Diode RX Termination. IEEE Trans. Circuits Syst. II Express Briefs 61-II(12): 987-991 (2014) - [c24]Yunjae Suh, Seungnam Choi, Byungsub Kim, Hong-June Park, Jae-Yoon Sim:
A voltage-scalable 10-b pipelined ADC with current-mode amplifier. CICC 2014: 1-4 - [c23]Jae-Seung Lee, Dong-Hee Yeo, Sang-Soo Lee, Hye-Jung Kwon, Jae-Yoon Sim, Byungsub Kim, Hong-June Park:
A 0.4 V driving multi-touch capacitive sensor with the driving signal frequency set to (n+0.5) times the inverse of the LCD VCOM noise period. ISCAS 2014: 682-685 - [c22]Dong Hoon Baek, Byungsub Kim, Hong-June Park, Jae-Yoon Sim:
2.6 A 5.67mW 9Gb/s DLL-based reference-less CDR with pattern-dependent clock-embedded signaling for intra-panel interface. ISSCC 2014: 48-49 - [c21]Seungho Han, Sooeun Lee, Minsoo Choi, Jae-Yoon Sim, Hong-June Park, Byungsub Kim:
2.7 A coefficient-error-robust FFE TX with 230% eye-variation improvement without calibration in 65nm CMOS technology. ISSCC 2014: 50-51 - [c20]Ji-Yong Um, Eun-Woo Song, Yoon-Jee Kim, Seong-Eun Cho, Min-Kyun Chae, Jongkeun Song, Bae-Hyung Kim, Seunghun Lee, Jihoon Bang, Youngil Kim, Kyungil Cho, Byungsub Kim, Jae-Yoon Sim, Hong-June Park:
24.8 An analog-digital-hybrid single-chip RX beamformer with non-uniform sampling for 2D-CMUT ultrasound imaging to achieve wide dynamic range of delay and small chip area. ISSCC 2014: 426-427 - 2013
- [j37]Jun-Seok Kim, Young Hun Seo, Yunjae Suh, Hong-June Park, Jae-Yoon Sim:
A 300-MS/s, 1.76-ps-Resolution, 10-b Asynchronous Pipelined Time-to-Digital Converter With on-Chip Digital Background Calibration in 0.13-µm CMOS. IEEE J. Solid State Circuits 48(2): 516-526 (2013) - [j36]Seon-Kyoo Lee, Byungsub Kim, Hong-June Park, Jae-Yoon Sim:
A 5 Gb/s Single-Ended Parallel Receiver With Adaptive Crosstalk-Induced Jitter Cancellation. IEEE J. Solid State Circuits 48(9): 2118-2127 (2013) - [j35]Dong-Woo Jee, Yunjae Suh, Byungsub Kim, Hong-June Park, Jae-Yoon Sim:
A FIR-Embedded Phase Interpolator Based Noise Filtering for Wide-Bandwidth Fractional-N PLL. IEEE J. Solid State Circuits 48(11): 2795-2804 (2013) - [j34]Seon-Kyoo Lee, Byungsub Kim, Hong-June Park, Jae-Yoon Sim:
A QDR-Based 6-GB/s Parallel Transceiver With Current-Regulated Voltage-Mode Output Driver and Byte CDR for Memory Interface. IEEE Trans. Circuits Syst. II Express Briefs 60-II(2): 91-95 (2013) - [j33]Yunjae Suh, Jongmi Lee, Byungsub Kim, Hong-June Park, Jae-Yoon Sim:
A 10-bit 25-MS/s 1.25-mW Pipelined ADC With a Semidigital Gm-Based Amplifier. IEEE Trans. Circuits Syst. II Express Briefs 60-II(3): 142-146 (2013) - [j32]Ji-Yong Um, Yoon-Jee Kim, Eun-Woo Song, Jae-Yoon Sim, Hong-June Park:
A Digital-Domain Calibration of Split-Capacitor DAC for a Differential SAR ADC Without Additional Analog Circuits. IEEE Trans. Circuits Syst. I Regul. Pap. 60-I(11): 2845-2856 (2013) - [c19]Soo-Min Lee, Jong-Hoon Kim, Jong-Sam Kim, Yunsaing Kim, Hyunbae Lee, Jae-Yoon Sim, Hong-June Park:
A 27% reduction in transceiver power for single-ended point-to-point DRAM interface with the termination resistance of 4×Z0 at both TX and RX. ISSCC 2013: 308-309 - 2012
- [j31]Young Hun Seo, Jun-Seok Kim, Hong-June Park, Jae-Yoon Sim:
A 1.25 ps Resolution 8b Cyclic TDC in 0.13 µm CMOS. IEEE J. Solid State Circuits 47(3): 736-743 (2012) - [j30]Dong-Woo Jee, Young Hun Seo, Hong-June Park, Jae-Yoon Sim:
A 2 GHz Fractional-N Digital PLL with 1b Noise Shaping ΔΣ TDC. IEEE J. Solid State Circuits 47(4): 875-883 (2012) - [j29]Hae-Kang Jung, Il-Min Yi, Soo-Min Lee, Jae-Yoon Sim, Hong-June Park:
A Transmitter to Compensate for Crosstalk-Induced Jitter by Subtracting a Rectangular Crosstalk Waveform From Data Signal During the Data Transition Time in Coupled Microstrip Lines. IEEE J. Solid State Circuits 47(9): 2068-2079 (2012) - [j28]Dong-Woo Jee, Byungsub Kim, Hong-June Park, Jae-Yoon Sim:
A 1.9-GHz Fractional-N Digital PLL With Subexponent ΔΣ TDC and IIR-Based Noise Cancellation. IEEE Trans. Circuits Syst. II Express Briefs 59-II(11): 721-725 (2012) - [c18]Hyunsoo Ha, Yunjae Suh, Seon-Kyoo Lee, Hong-June Park, Jae-Yoon Sim:
A 0.5V, 11.3-μW, 1-kS/s resistive sensor interface circuit with correlated double sampling. CICC 2012: 1-4 - [c17]Young-Ho Choi, Jae-Yoon Sim, Hong-June Park:
A fractional-N frequency divider for SSCG using a single dual-modulus integer divider and a phase interpolator. ISOCC 2012: 68-71 - [c16]Il-Min Yi, Seung-Jun Bae, Young-Soo Sohn, Jae-Yoon Sim, Hong-June Park:
An on-chip TSV emulation using metal bar surrounded by metal ring to develop interface circuits. ISOCC 2012: 192-195 - [c15]Young-Sik Kim, Seon-Kyoo Lee, Seung-Jun Bae, Young-Soo Sohn, Jung-Bae Lee, Joo-Sun Choi, Hong-June Park, Jae-Yoon Sim:
An 8GB/s quad-skew-cancelling parallel transceiver in 90nm CMOS for high-speed DRAM interface. ISSCC 2012: 136-138 - [c14]Seon-Kyoo Lee, Hyunsoo Ha, Hong-June Park, Jae-Yoon Sim:
A 5Gb/s single-ended parallel receiver with adaptive FEXT cancellation. ISSCC 2012: 140-142 - 2011
- [j27]Seon-Kyoo Lee, Young-Sang Kim, Hong-June Park, Jae-Yoon Sim:
A Wide Lock-Range Referenceless CDR with Automatic Frequency Acquisition. J. Electr. Comput. Eng. 2011: 701730:1-701730:7 (2011) - [j26]Young-Sang Kim, Seon-Kyoo Lee, Hong-June Park, Jae-Yoon Sim:
A 110 MHz to 1.4 GHz Locking 40-Phase All-Digital DLL. IEEE J. Solid State Circuits 46(2): 435-444 (2011) - [j25]Seon-Kyoo Lee, Seung-Jin Park, Hong-June Park, Jae-Yoon Sim:
A 21 fJ/Conversion-Step 100 kS/s 10-bit ADC With a Low-Noise Time-Domain Comparator for Low-Power Sensor Interface. IEEE J. Solid State Circuits 46(3): 651-659 (2011) - [j24]Hyung-Joon Chi, Jae-Seung Lee, Seong-Hwan Jeon, Seung-Jun Bae, Young-Soo Sohn, Jae-Yoon Sim, Hong-June Park:
A Single-Loop SS-LMS Algorithm With Single-Ended Integrating DFE Receiver for Multi-Drop DRAM Interface. IEEE J. Solid State Circuits 46(9): 2053-2063 (2011) - [j23]Jong-Hoon Kim, Jung-Bum Shin, Jae-Yoon Sim, Hong-June Park:
5-Gb/s Peak Detector Using a Current Comparator and a Three-State Charge Pump. IEEE Trans. Circuits Syst. II Express Briefs 58-II(5): 269-273 (2011) - [j22]Hyung-Joon Chi, Young-Ho Choi, Soo-Min Lee, Jae-Yoon Sim, Hong-June Park, Jong-Jin Lim, Pil-Sung Kang, Bu-Yeol Lee, Jin-Cheol Hong, Hee-Sub Lee:
A 2-Gb/s Intrapanel Interface for TFT-LCD With a VSYNC-Embedded Subpixel Clock and a Cascaded Deskew and Multiphase DLL. IEEE Trans. Circuits Syst. II Express Briefs 58-II(10): 687-691 (2011) - [c13]Ji-Yong Um, Jae-Hwan Kim, Jae-Yoon Sim, Hong-June Park:
Digital-domain calibration of split-capacitor DAC with no extra calibration DAC for a differential-type SAR ADC. A-SSCC 2011: 77-80 - [c12]Hye-Jung Kwon, Jae-Seung Lee, Jae-Yoon Sim, Hong-June Park:
A high-gain wide-input-range time amplifier with an open-loop architecture and a gain equal to current bias ratio. A-SSCC 2011: 325-328 - [c11]Jae-Hwan Kim, Ji-Yong Um, Jae-Yoon Sim, Hong-June Park:
Time-interleaved sample clock generator for ultrasound beamformer application. ISOCC 2011: 290-293 - [c10]Dong-Woo Jee, Yunjae Suh, Hong-June Park, Jae-Yoon Sim:
A 0.1-fref BW 1GHz fractional-N PLL with FIR-embedded phase-interpolator-based noise filtering. ISSCC 2011: 94-96 - 2010
- [j21]Jun-Hyun Bae, Sang-Hune Park, Jae-Yoon Sim, Hong-June Park:
A Digital Differential Transmitter with Pseudo-LVDS Output Driver and Digital Mismatch Calibration. IEICE Trans. Electron. 93-C(1): 132-135 (2010) - [j20]Jae-Seung Lee, Jae-Yoon Sim, Hong-June Park:
A High-Throughput On-Chip Variation Monitoring Circuit for MOSFET Threshold Voltage Using VCDL and Time-to-Digital Converter. IEICE Trans. Electron. 93-C(8): 1333-1337 (2010) - [j19]Young-Sang Kim, Yunjae Suh, Hong-June Park, Jae-Yoon Sim:
An Analysis and Design Methodology of Resistor-Based Phase Error Averaging for Multiphase Generation. IEICE Trans. Electron. 93-C(12): 1662-1669 (2010) - [j18]Seon-Kyoo Lee, Young Hun Seo, Hong-June Park, Jae-Yoon Sim:
A 1 GHz ADPLL With a 1.25 ps Minimum-Resolution Sub-Exponent TDC in 0.18 μ m CMOS. IEEE J. Solid State Circuits 45(12): 2874-2881 (2010) - [j17]Young Hun Seo, Young-Sang Kim, Hong-June Park, Jae-Yoon Sim:
A 5 Gb/s Transmitter With a TDR-Based Self-Calibration of Preemphasis Strength. IEEE Trans. Circuits Syst. II Express Briefs 57-II(5): 379-383 (2010) - [c9]Jun-Hyun Bae, Young-Soo Sohn, Seung-Jun Bae, Kwang-Il Park, Joo-Sun Choi, Young-Hyun Jun, Jae-Yoon Sim, Hong-June Park:
A crosstalk-and-ISI equalizing receiver in 2-drop single-ended SSTL memory channel. CICC 2010: 1-4 - [c8]Hae-Kang Jung, Soo-Min Lee, Jae-Yoon Sim, Hong-June Park:
A slew-rate controlled transmitter to compensate for the crosstalk-induced jitter of coupled microstrip lines. CICC 2010: 1-4 - [c7]Seon-Kyoo Lee, Young Hun Seo, Yunjae Suh, Hong-June Park, Jae-Yoon Sim:
A 1GHz ADPLL with a 1.25ps minimum-resolution sub-exponent TDC in 0.18µm CMOS. ISSCC 2010: 482-483
2000 – 2009
- 2009
- [j16]Seung-Jin Park, Young Hun Seo, Hong-June Park, Jae-Yoon Sim:
A Distortion-Free General Purpose LVDS Driver. IEICE Trans. Electron. 92-C(2): 278-280 (2009) - [j15]Hae-Kang Jung, Kyoungho Lee, Jong-Sam Kim, Jae-Jin Lee, Jae-Yoon Sim, Hong-June Park:
A 4 Gb/s 3-bit Parallel Transmitter With the Crosstalk-Induced Jitter Compensation Using TX Data Timing Control. IEEE J. Solid State Circuits 44(11): 2891-2900 (2009) - [j14]Seung-Jun Bae, Hyung-Joon Chi, Young-Soo Sohn, Jae-Seung Lee, Jae-Yoon Sim, Hong-June Park:
A 2-Gb/s CMOS Integrating Two-Tap DFE Receiver for Four-Drop Single-Ended Signaling. IEEE Trans. Circuits Syst. I Regul. Pap. 56-I(8): 1645-1656 (2009) - [j13]Kwang-Hee Choi, Jung-Bum Shin, Jae-Yoon Sim, Hong-June Park:
An Interpolating Digitally Controlled Oscillator for a Wide-Range All-Digital PLL. IEEE Trans. Circuits Syst. I Regul. Pap. 56-I(9): 2055-2063 (2009) - [c6]Seon-Kyoo Lee, Young-Sang Kim, Hyunsoo Ha, Young Hun Seo, Hong-June Park, Jae-Yoon Sim:
A 650Mb/s-to-8Gb/s referenceless CDR circuit with automatic acquisition of data rate. ISSCC 2009: 184-185 - 2008
- [j12]Young-Sang Kim, Yunjae Suh, Hong-June Park, Jae-Yoon Sim:
Deadzone-Minimized Systematic Offset-Free Phase Detectors. IEICE Trans. Electron. 91-C(9): 1525-1528 (2008) - [j11]Sang-Hune Park, Kwang-Hee Choi, Jung-Bum Shin, Jae-Yoon Sim, Hong-June Park:
A Single-Data-Bit Blind Oversampling Data-Recovery Circuit With an Add-Drop FIFO for USB2.0 High-Speed Interface. IEEE Trans. Circuits Syst. II Express Briefs 55-II(2): 156-160 (2008) - [c5]Dong-Woo Jee, Seung-Jin Park, Hong-June Park, Jae-Yoon Sim:
A low-voltage OP amp with digitally controlled algorithmic approximation. CICC 2008: 499-502 - [c4]Hyung-Joon Chi, Jae-Seung Lee, Seong-Hwan Jeon, Seung-Jun Bae, Jae-Yoon Sim, Hong-June Park:
A 3.2Gb/s 8b Single-Ended Integrating DFE RX for 2-Drop DRAM Interface with Internal Reference Voltage and Digital Calibration. ISSCC 2008: 112-113 - 2007
- [j10]Young-Chan Jang, Jun-Hyun Bae, Sang-Hune Park, Jae-Yoon Sim, Hong-June Park:
An 8.8-GS/s 6-bit CMOS Time-Interleaved Flash Analog-to-Digital Converter with Multi-Phase Clock Generator. IEICE Trans. Electron. 90-C(6): 1156-1164 (2007) - [c3]Jun-Hyun Bae, Jin-Ho Seo, Hwan-Seok Yeo, Jae-Whui Kim, Jae-Yoon Sim, Hong-June Park:
An All-Digital 90-Degree Phase-Shift DLL with Loop-Embedded DCC for 1.6Gbps DDR Interface. CICC 2007: 373-376 - [c2]Young-Sang Kim, Seung-Jin Park, Yong-Sub Kim, Dong-Bi Jang, Seh-Woong Jeong, Hong-June Park, Jae-Yoon Sim:
A 40-to-800MHz Locking Multi-Phase DLL. ISSCC 2007: 306-605 - 2006
- [j9]Seok-Woo Choi, Hyun-Bae Lee, Hong-June Park:
A three-data differential signaling over four conductors with pre-emphasis and equalization: a CMOS current mode implementation. IEEE J. Solid State Circuits 41(3): 633-641 (2006) - [j8]Young-Chan Jang, Jun-Hyun Bae, Hong-June Park:
A Digital CMOS PWCL With Fixed-Delay Rising Edge and Digital Stability Control. IEEE Trans. Circuits Syst. II Express Briefs 53-II(10): 1063-1067 (2006) - 2005
- [j7]Jang-Jin Nam, Hong-June Park:
An All-Digital CMOS Duty Cycle Correction Circuit with a Duty-Cycle Correction Range of 15-to-85% for Multi-Phase Applications. IEICE Trans. Electron. 88-C(4): 773-777 (2005) - [j6]Seung-Jun Bae, Hyung-Joon Chi, Young-Soo Sohn, Hong-June Park:
A VCDL-based 60-760-MHz dual-loop DLL with infinite phase-shift capability and adaptive-bandwidth scheme. IEEE J. Solid State Circuits 40(5): 1119-1129 (2005) - 2004
- [j5]Young-Jin Jeon, Joong-Ho Lee, Hyun-Chul Lee, Kyo-Won Jin, Kyeong-Sik Min, Jin-Yong Chung, Hong-June Park:
A 66-333-MHz 12-mW register-controlled DLL with a single delay line and adaptive-duty-cycle clock dividers for production DDR SDRAMs. IEEE J. Solid State Circuits 39(11): 2087-2092 (2004) - 2003
- [j4]Seong-Ik Cho, Jung-Hwan Lee, Hong-June Park, Gyu-Ho Lim, Young-Hee Kim:
Two-phase boosted voltage generator for low-voltage DRAMs. IEEE J. Solid State Circuits 38(10): 1726-1729 (2003) - [c1]Young-Soo Sohn, Seung-Jun Bae, Hong-June Park, Changhyun Kim, Soo-In Cho:
A 2.2 Gbps CMOS look-ahead DFE receiver for multidrop channel with pin-to-pin time skew compensation. CICC 2003: 473-476 - 2002
- [j3]Jae-Yoon Sim, Jang-Jin Nam, Young-Soo Sohn, Hong-June Park, Chang-Hyun Kim, Soo-In Cho:
A CMOS transceiver for DRAM bus system with a demultiplexed equalization scheme. IEEE J. Solid State Circuits 37(2): 245-250 (2002)
1990 – 1999
- 1999
- [j2]Jae-Yoon Sim, Young-Soo Sohn, Seung-Chan Heo, Hong-June Park, Soo-In Cho:
A 1-Gb/s bidirectional I/O buffer using the current-mode scheme. IEEE J. Solid State Circuits 34(4): 529-535 (1999)
1980 – 1989
- 1985
- [j1]Hong-June Park, Choong-Ki Kim:
An Empirical Model for the Threshold Voltage of Enhancement NMOSFET's. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 4(4): 629-635 (1985)
Coauthor Index
[j80] [j78] [j77] [j76] [j75] [j74] [j73] [c43] [j70] [j69] [j68] [c42] [c41] [j67] [j66] [j65] [j64] [j63] [j62] [c40] [c39] [c38] [c37] [c36] [j61] [j60] [j59] [j58] [j57] [j56] [j55] [j54] [c35] [c34] [c33] [c32] [c31] [j52] [j51] [j50] [j49] [j48] [j47] [c30] [c29] [c28] [c27] [j46] [j45] [c26] [c25] [j44] [j43] [j42] [j41] [j40] [j39] [j38] [c24] [c23] [c22] [c21] [c20] [j36] [j35] [j34] [j33] [j28]
[j80] [j78] [j77] [j76] [j75] [j74] [j73] [j72] [j71] [j70] [j69] [j68] [c42] [c41] [j67] [j66] [j65] [j64] [j63] [j62] [c40] [c39] [c38] [c37] [c36] [j61] [j60] [j59] [j58] [j57] [j56] [j55] [j54] [c35] [c34] [c33] [c32] [c31] [j53] [j52] [j51] [j50] [j49] [j48] [j47] [c30] [c29] [c28] [c27] [j46] [j45] [c26] [c25] [j44] [j43] [j42] [j41] [j40] [j39] [j38] [c24] [c23] [c22] [c21] [c20] [j37] [j36] [j35] [j34] [j33] [j32] [c19] [j31] [j30] [j29] [j28] [c18] [c17] [c16] [c15] [c14] [j27] [j26] [j25] [j24] [j23] [j22] [c13] [c12] [c11] [c10] [j21] [j20] [j19] [j18] [j17] [c9] [c8] [c7] [j16] [j15] [j14] [j13] [c6] [j12] [j11] [c5] [c4] [j10] [c3] [c2] [j3] [j2]
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