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2020 – today
- 2021
[c81]Jakub Lojda, Richard Panek, Zdenek Kotásek:
Automatic Design of Fault-Tolerant Systems for VHDL and SRAM-based FPGAs. DSD 2021: 549-552- [c80]Richard Panek, Jakub Lojda, Jakub Podivinsky, Zdenek Kotásek:
Reliability Analysis of the FPGA Control System with Reconfiguration Hardening. DSD 2021: 553-556 - [c79]Jakub Lojda, Richard Panek, Zdenek Kotásek:
Automatically-Designed Fault-Tolerant Systems: Failed Partitions Recovery. EWDTS 2021: 1-8 - [c78]Jakub Lojda, Richard Panek, Jakub Podivinsky, Ondrej Cekan, Martin Krcma, Zdenek Kotásek:
Testing Embedded Software Through Fault Injection: Case Study on Smart Lock. LATS 2021: 1-6 - 2020
- [c77]Jakub Lojda, Jakub Podivinsky, Ondrej Cekan
, Richard Panek, Martin Krcma, Zdenek Kotásek:
Automatic Design of Reliable Systems Based on the Multiple-choice Knapsack Problem. DDECS 2020: 1-4 - [c76]Jakub Lojda, Richard Panek, Jakub Podivinsky, Ondrej Cekan, Martin Krcma, Zdenek Kotásek:
Hardening of Smart Electronic Lock Software against Random and Deliberate Faults. DSD 2020: 680-683 - [c75]Jakub Lojda, Richard Panek, Jakub Podivinsky, Ondrej Cekan, Martin Krcma, Zdenek Kotásek:
Analysis of Software-Implemented Fault Tolerance: Case Study on Smart Lock. EWDTS 2020: 1-5 - [c74]Jakub Podivinsky, Ondrej Cekan, Martin Krcma, Radek Burget, Tomas Hruska, Zdenek Kotásek:
Iterative Algorithm for Multidimensional Pareto Frontiers Intersection Determination. LASCAS 2020: 1-4 - [c73]Jakub Podivinsky, Jakub Lojda, Richard Panek, Ondrej Cekan, Martin Krcma, Zdenek Kotásek:
Evaluation Platform For Testing Fault Tolerance: Testing Reliability of Smart Electronic Locks. LASCAS 2020: 1-4 - [c72]Richard Panek, Jakub Lojda, Jakub Podivinsky, Zdenek Kotásek:
Reliability Analysis of Reconfiguration Controller for FPGA-Based Fault Tolerant Systems: Case Study. VLSI-DAT 2020: 1-4
2010 – 2019
- 2019
- [c71]Karel Szurman, Zdenek Kotásek:
Run-Time Reconfigurable Fault Tolerant Architecture for Soft-Core Processor NEO430. DDECS 2019: 1-4 - [c70]Ondrej Cekan, Jakub Podivinsky, Jakub Lojda, Richard Panek, Martin Krcma, Zdenek Kotásek:
Testing Reliability of Smart Electronic Locks: Analysis and the First Steps Towards. DSD 2019: 506-513 - [c69]Jakub Podivinsky, Ondrej Cekan, Martin Krcma, Radek Burget, Tomas Hruska, Zdenek Kotásek:
Multidimensional Pareto Frontiers Intersection Determination and Processor Optimization Case Study. DSD 2019: 597-600 - [c68]Martin Krcma, Zdenek Kotásek, Jakub Lojda:
Detecting hard synapses faults in artificial neural networks. LATS 2019: 1-6 - [c67]Jakub Lojda, Jakub Podivinsky, Zdenek Kotásek:
Reliability Indicators for Automatic Design and Analysis of Fault-Tolerant FPGA Systems. LATS 2019: 1-4 - [c66]Jakub Podivinsky, Jakub Lojda, Zdenek Kotásek:
Extended Reliability Analysis of Fault-Tolerant FPGA-based Robot Controller. LATS 2019: 1-4 - [c65]Karel Szurman, Zdenek Kotásek:
Coarse-Grained TMR Soft-Core Processor Fault Tolerance Methods and State Synchronization for Run-Time Fault Recovery. LATS 2019: 1-4 - 2018
- [c64]Ondrej Cekan, Jakub Podivinsky, Zdenek Kotásek:
Program Generation Through a Probabilistic Constrained Grammar. DSD 2018: 214-220 - [c63]Jakub Podivinsky, Jakub Lojda, Ondrej Cekan, Zdenek Kotásek:
Evaluation Platform for Testing Fault Tolerance Properties: Soft-core Processor-Based Experimental Robot Controller. DSD 2018: 229-236 - [c62]Jakub Lojda, Jakub Podivinsky, Ondrej Cekan, Richard Panek, Zdenek Kotásek:
FT-EST Framework: Reliability Estimation for the Purposes of Fault-Tolerant System Design Automation. DSD 2018: 244-251 - [c61]Ondrej Cekan, Richard Panek, Zdenek Kotásek:
Input and Output Generation for the Verification of ALU: A Use Case. EWDTS 2018: 1-6 - [c60]Jakub Lojda, Jakub Podivinsky, Zdenek Kotásek:
Fault Tolerance Properties of Systems Generated with the Use of High-Level Synthesis. EWDTS 2018: 1-7 - [c59]Richard Panek, Jakub Lojda, Jakub Podivinsky, Zdenek Kotásek:
Partial Dynamic Reconfiguration in an FPGA-based Fault-Tolerant System: Simulation-based Evaluation. EWDTS 2018: 1-6 - [c58]Jalab Podivinsky, Ondrej Cekan, Martin Krcma, Radek Burget, Tomas Hruska, Zdenek Kotásek:
A Processor Optimization Framework for a Selected Application. EWDTS 2018: 1-11 - [c57]Jakub Podivinsky, Jakub Lojda, Zdenek Kotásek:
An Experimental Evaluation of Fault-Tolerant FPGA-Based Robot Controller. EWDTS 2018: 1-7 - 2017
- [j10]Jakub Podivinsky, Ondrej Cekan, Jakub Lojda, Marcela Zachariásová, Martin Krcma, Zdenek Kotásek:
Functional verification based platform for evaluating fault tolerance properties. Microprocess. Microsystems 52: 145-159 (2017) - [c56]Jakub Podivinsky, Jakub Lojda, Ondrej Cekan, Richard Panek, Zdenek Kotásek:
Reliability Analysis and Improvement of FPGA-Based Robot Controller. DSD 2017: 337-344 - [c55]Ondrej Cekan, Zdenek Kotásek:
A Probabilistic Context-Free Grammar Based Random Test Program Generation. DSD 2017: 356-359 - [c54]Martin Krcma, Zdenek Kotásek, Jakub Lojda:
Triple modular redundancy used in field programmable neural networks. EWDTS 2017: 1-6 - [c53]Jakub Lojda, Jakub Podivinsky, Zdenek Kotásek:
Redundant data types and operations in HLS and their use for a robot controller unit fault tolerance evaluation. EWDTS 2017: 1-6 - [c52]Jakub Lojda, Jakub Podivinsky, Zdenek Kotásek, Martin Krcma:
Data types and operations modifications: A practical approach to fault tolerance in HLS. EWDTS 2017: 1-6 - [c51]Martin Krcma, Zdenek Kotásek, Jakub Lojda:
Comparison of FPNNs models approximation capabilities and FPGA resources utilization. ICCP 2017: 125-132 - 2016
- [c50]Marcela Zachariásová, Michaela Kekelyova-Beleova, Zdenek Kotásek:
Regression Test Suites Optimization for Application-specific Instruction-Set Processors and Their Use for Dependability Analysis. DSD 2016: 380-387 - [c49]Jakub Podivinsky, Ondrej Cekan, Jakub Lojda, Zdenek Kotásek:
Verification of Robot Controller for Evaluating Impacts of Faults in Electro-Mechanical Systems. DSD 2016: 487-494 - [c48]Jakub Podivinsky, Ondrej Cekan, Jakub Lojda, Zdenek Kotásek:
Functional verification as a tool for monitoring impact of faults in SRAM-based FPGAs. FPT 2016: 293-294 - [c47]Ondrej Cekan, Jakub Podivinsky, Zdenek Kotásek:
Random stimuli generation based on a stochastic context-free grammar. FPT 2016: 295-296 - [c46]Martin Krcma, Zdenek Kotásek, Jakub Lojda:
Implementation of fault tolerant techniques into FPNNs. FPT 2016: 297-298 - [c45]Jakub Lojda, Jakub Podivinsky, Martin Krcma, Zdenek Kotásek:
HLS-based fault tolerance approach for SRAM-based FPGAs. FPT 2016: 301-302 - 2015
- [j9]Jakub Podivinsky, Ondrej Cekan, Marcela Simková, Zdenek Kotásek:
The evaluation platform for testing fault-tolerance methodologies in electro-mechanical applications. Microprocess. Microsystems 39(8): 1215-1230 (2015) - [c44]Michaela Beleova, Zdenek Kotásek, Marcela Simková, Toma Hruka:
Application of Evolutionary Algorithms for Regression Suites Optimization. DDECS 2015: 91-94 - [c43]Jakub Podivinsky, Marcela Simková, Ondrej Cekan, Zdenek Kotásek:
FPGA Prototyping and Accelerated Verification of ASIPs. DDECS 2015: 145-148 - [c42]Martin Krcma, Jan Kastil, Zdenek Kotásek:
Mapping Trained Neural Networks to FPNNs. DDECS 2015: 157-160 - [c41]Marcela Simková, Zdenek Kotásek:
Automation and Optimization of Coverage-driven Verification. DSD 2015: 87-94 - [c40]Ondrej Cekan, Jakub Podivinsky, Zdenek Kotásek:
Software Fault Tolerance: The Evaluation by Functional Verification. DSD 2015: 284-287 - [c39]Martin Krcma, Zdenek Kotásek, Jan Kastil:
Fault tolerant Field Programmable Neural Networks. NORCAS 2015: 1-4 - 2014
- [c38]Lukas Miculka, Zdenek Kotásek:
Generic partial dynamic reconfiguration controller for transient and permanent fault mitigation in fault tolerant systems implemented into FPGA. DDECS 2014: 171-174 - [c37]Jakub Podivinsky, Ondrej Cekan, Marcela Simková, Zdenek Kotásek:
The Evaluation Platform for Testing Fault-Tolerance Methodologies in Electro-Mechanical Applications. DSD 2014: 312-319 - [c36]Lucie Matuova, Jan Kastil, Zdenek Kotásek:
Automatic Construction of On-line Checking Circuits Based on Finite Automata. DSD 2014: 326-332 - [c35]Karel Szurman, Lukas Miculka, Zdenek Kotásek:
State Synchronization after Partial Reconfiguration of Fault Tolerant CAN Bus Control System. DSD 2014: 704-707 - 2013
- [j8]Martin Straka, Jan Kastil, Zdenek Kotásek, Lukas Miculka:
Fault tolerant system design and SEU injection based testing. Microprocess. Microsystems 37(2): 155-173 (2013) - [c34]Marcela Simková, Zdenek Kotásek, Cristiana Bolchini:
Analysis and comparison of functional verification and ATPG for testing design reliability. DDECS 2013: 275-278 - [c33]Karel Szurman, Jan Kastil, Martin Straka, Zdenek Kotásek:
Fault tolerant CAN bus control system implemented into FPGA. DDECS 2013: 289-292 - [c32]Lukas Miculka, Martin Straka, Zdenek Kotásek:
Methodology for Fault Tolerant System Design Based on FPGA into Limited Redundant Area. DSD 2013: 227-234 - [c31]Marcela Simková, Zdenek Prikryl, Zdenek Kotásek, Tomas Hruska:
Automated Functional Verification of Application Specific Instruction-set Processors. IESS 2013: 128-138 - 2012
- [j7]Zdenek Kotásek, Lukás Sekanina, Tomás Vojnar, Jan Bouda, Ivana Cerná:
pecial CAI Section Devoted to MEMICS '11: Preface. Comput. Informatics 31(3): 481- (2012) - [c30]Martin Straka, Lukas Miculka, Jan Kastil, Zdenek Kotásek:
Test platform for fault tolerant systems design properties verification. DDECS 2012: 336-341 - [c29]Jan Kastil, Martin Straka, Lukas Miculka, Zdenek Kotásek:
Dependability Analysis of Fault Tolerant Systems Based on Partial Dynamic Reconfiguration Implemented into FPGA. DSD 2012: 250-257 - [e4]Zdenek Kotásek, Jan Bouda, Ivana Cerná, Lukás Sekanina, Tomás Vojnar, David Antos:
Mathematical and Engineering Methods in Computer Science - 7th International Doctoral Workshop, MEMICS 2011, Lednice, Czech Republic, October 14-16, 2011, Revised Selected Papers. Lecture Notes in Computer Science 7119, Springer 2012, ISBN 978-3-642-25928-9 [contents] - 2011
- [c28]Pavel Bartos, Zdenek Kotásek, Jan Dohnal:
Decreasing test time by scan chain reorganization. DDECS 2011: 371-374 - [c27]Martin Straka, Jan Kastil, Jaroslav Novotný, Zdenek Kotásek:
Advanced fault tolerant bus for multicore system implemented in FPGA. DDECS 2011: 397-398 - [c26]Martin Straka, Jan Kastil, Zdenek Kotásek:
SEU Simulation Framework for Xilinx FPGA: First Step towards Testing Fault Tolerant Systems. DSD 2011: 223-230 - 2010
- [c25]Martin Straka, Jan Kastil, Zdenek Kotásek:
Modern fault tolerant architectures based on partial dynamic reconfiguration in FPGAs. DDECS 2010: 173-176 - [c24]Zdenek Kotásek, Jaroslav Skarvada, Josef Strnadel:
Reduction of power dissipation through parallel optimization of test vector and scan register sequences. DDECS 2010: 364-369 - [c23]Martin Straka, Jan Kastil, Zdenek Kotásek:
Fault Tolerant Structure for SRAM-Based FPGA via Partial Dynamic Reconfiguration. DSD 2010: 365-372 - [c22]Zdenek Kotásek, Jaroslav Skarvada, Josef Strnadel:
The Use of Genetic Algorithm to Derive Correlation Between Test Vector and Scan Register Sequences and Reduce Power Consumption. DSD 2010: 644-651 - [c21]Jaroslav Skarvada, Zdenek Kotásek, Josef Strnadel:
The Use of Genetic Algorithm to Reduce Power Consumption during Test Application. ICES 2010: 181-192 - [e3]Elena Gramatová, Zdenek Kotásek, Andreas Steininger, Heinrich Theodor Vierhaus, Horst Zimmermann:
13th IEEE International Symposium on Design and Diagnostics of Electronic Circuits and Systems, DDECS 2010, Vienna, Austria, April 14-16, 2010. IEEE Computer Society 2010, ISBN 978-1-4244-6612-2 [contents]
2000 – 2009
- 2009
- [c20]Martin Straka, Zdenek Kotásek:
High Availability Fault Tolerant Architectures Implemented into FPGAs. DSD 2009: 108-115 - [e2]Milan Ceska, Zdenek Kotásek, Mojmír Kretínský, Ludek Matyska, Tomás Vojnar:
Proceedings of the International Doctoral Workshop on Mathematical and Engineering Methods in Computer Science, MEMICS 2008, Znojmo, Czech Republic, November 14-16, 2008. Electronic Notes in Theoretical Computer Science 251, Elsevier 2009 [contents] - 2008
- [j6]Josef Strnadel, Tomas Pecenka, Zdenek Kotásek:
Measuring CADeT Performance by Means of FITTest_BENCH06 Benchmark Circuits. Comput. Informatics 27(6): 913-930 (2008) - [j5]Lukás Sekanina, Lukás Starecek, Zdenek Kotásek, Zbysek Gajda:
Polymorphic Gates in Design and Test of Digital Circuits. Int. J. Unconv. Comput. 4(2): 125-142 (2008) - [j4]Jaroslav Skarvada, Zdenek Kotásek, Tomas Herrman:
Testability analysis based on the identification of testable blocks with predefined properties. Microprocess. Microsystems 32(5-6): 296-302 (2008) - [j3]Tomas Pecenka, Lukás Sekanina, Zdenek Kotásek:
Evolution of synthetic RTL benchmark circuits with predefined testability. ACM Trans. Design Autom. Electr. Syst. 13(3): 54:1-54:21 (2008) - [c19]Lukás Starecek, Lukás Sekanina, Zdenek Kotásek:
Reduction of Test Vectors Volume by Means of Gate-Level Reconfiguration. DDECS 2008: 255-268 - [c18]Martin Straka, Zdenek Kotásek, Jan Winter:
Digital Systems Architectures Based on On-line Checkers. DSD 2008: 81-87 - [c17]Jaroslav Skarvada, Zdenek Kotásek, Tomas Herrman:
Power Conscious RTL Test Scheduling. DSD 2008: 721-728 - [c16]Milan Ceska, Zdenek Kotásek, Mojmír Kretínský, Ludek Matyska, Tomás Vojnar:
Preface. MEMICS 2008: 1-3 - 2007
- [c15]Martin Straka, Jiri Tobola, Zdenek Kotásek:
Checker Design for On-line Testing of Xilinx FPGA Communication Protocols. DFT 2007: 152-160 - [c14]Jaroslav Skarvada, Tomas Herrman, Zdenek Kotásek:
Testability Analysis Based on the Identification of Testable Blocks with Predefined Properties. DSD 2007: 611-618 - [c13]Jiri Tobola, Zdenek Kotásek, Jan Korenek, Tomás Martínek, Martin Straka:
Online Protocol Testing for FPGA Based Fault Tolerant Systems. DSD 2007: 676-679 - 2006
- [c12]Lukás Sekanina, Lukás Starecek, Zbysek Gajda, Zdenek Kotásek:
Evolution of Multifunctional Combinational Modules Controlled by the Power Supply Voltage. AHS 2006: 186-193 - [c11]Lukás Sekanina, Lukás Starecek, Zdenek Kotásek:
Novel Logic Circuits Controlled by Vdd: Transistor-Level Simulations of Polymorphic Combinational Modules. DDECS 2006: 85-86 - [c10]Tomas Pecenka, Zdenek Kotásek, Lukás Sekanina:
FITTest_BENCH06: A New Set of Benchmark Circuits Reflecting Diagnostic Properties. DDECS 2006: 285-289 - [c9]Tomas Pecenka, Josef Strnadel, Zdenek Kotásek, Lukás Sekanina:
Testability Estimation Based on Controllability and Observability Parameters. DSD 2006: 504-514 - [c8]Josef Strnadel, Zdenek Kotásek:
SET: Interactive Tool for Learning and Training Scan-Based DFT Principles and Their Consequences to Parameters of Embedded System. ECBS 2006: 497-498 - [e1]Matteo Sonza Reorda, Ondrej Novák, Bernd Straube, Hana Kubátová, Zdenek Kotásek, Pavel Kubalík, Raimund Ubar, Jirí Bucek:
Proceedings of the 9th IEEE Workshop on Design & Diagnostics of Electronic Circuits & Systems (DDECS 2006), Prague, Czech Republic, April 18-21, 2006. IEEE Computer Society 2006, ISBN 1-4244-0185-2 [contents] - 2005
- [c7]Josef Strnadel, Zdenek Kotásek:
Educational Tool for the Demonstration of DfT Principles Based on Scan Methodologies. DSD 2005: 420-427 - [c6]Tomas Pecenka, Zdenek Kotásek, Lukás Sekanina, Josef Strnadel:
Automatic Discovery of RTL Benchmark Circuits with Predefined Testability Properties. Evolvable Hardware 2005: 51-58 - 2004
- [c5]Daniel Mika, Josef Strnadel, Zdenek Kotásek:
The Identification of registers in RTL Structures for the Test Application. ISoLA (Preliminary proceedings) 2004: 317-319 - 2003
- [c4]Zdenek Kotásek, Daniel Mika, Josef Strnadel:
Test scheduling for embedded systems. DSD 2003: 463-467 - 2002
- [c3]Josef Strnadel, Zdenek Kotásek:
Testability Improvements Based on the Combination of Analytical and Evolutionary Approaches at RT Level. DSD 2002: 166-173 - 2000
- [c2]Zdenek Kotásek, Richard Ruzicka, Jan Hlavicka:
Formal Approach to the RTL Testability Analysis. LATW 2000: 256-261
1990 – 1999
- 1997
- [j2]Jan Blatný, Zdenek Kotásek, Jan Hlavicka:
RT Level Test Scheduling. Comput. Artif. Intell. 16(1): 13-29 (1997) - [c1]Zdenek Kotásek, F. Zboril:
RT level testability analysis to reduce test application time. EUROMICRO 1997: 104- - 1995
- [j1]Jan Blatný, Zdenek Kotásek:
I-Path Analysis. Comput. Artif. Intell. 14(5): 513-530 (1995)
Coauthor Index
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