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2020 – today
- 2024
[c119]Dewmini Sudara Marakkalage, Eleonora Testa, Walter Lau Neto, Alan Mishchenko, Giovanni De Micheli, Luca G. Amarù:
Scalable Sequential Optimization Under Observability Don't Cares. DATE 2024: 1-6- [c118]Yukio Miyasaka, Alan Mishchenko, John Wawrzynek, Nicholas J. Fraser:
Synthesis of LUT Networks for Random-Looking Dense Functions with Don't Cares - Towards Efficient FPGA Implementation of DNN. FCCM 2024: 126-132 - [c117]Andrea Costamagna, Alan Mishchenko, Satrajit Chatterjee, Giovanni De Micheli:
An Enhanced Resubstitution Algorithm for Area-Oriented Logic Optimization. ISCAS 2024: 1-5 - [c116]Venkata Pavan Sumanth Sikhakollu
, Shreesha Sreedhara, Rajit Manohar, Alan Mishchenko, Jaijeet Roychowdhury:
High Quality Circuit-Based 3-SAT Mappings for Oscillator Ising Machines. UCNC 2024: 269-285 - [i10]Alessandro Tempia Calvino, Alan Mishchenko, Giovanni De Micheli, Robert K. Brayton:
Practical Boolean Decomposition for Delay-driven LUT Mapping. CoRR abs/2406.06241 (2024) - 2023
- [j30]Yu-Shan Huang, Jie-Hong R. Jiang, Alan Mishchenko:
Quantized Neural Network Synthesis for Direct Logic Circuit Implementation. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 42(2): 473-482 (2023) - [c115]Alessandro Tempia Calvino, Alan Mishchenko, Herman Schmit, Ethan Mahintorabi, Giovanni De Micheli, Xiaoqing Xu:
Improving Standard-Cell Design Flow using Factored Form Optimization. DAC 2023: 1-6 - [c114]Benjamin Lukas Cajus Barzen, Arya Reais-Parsi, Eddie Hung, Minwoo Kang, Alan Mishchenko, Jonathan W. Greene, John Wawrzynek:
Narrowing the Synthesis Gap: Academic FPGA Synthesis is Catching Up With the Industry. DATE 2023: 1-6 - [c113]Yingjie Li, Mingju Liu, Alan Mishchenko, Cunxi Yu:
Invited Paper: Verilog-to-PyG - A Framework for Graph Learning and Augmentation on RTL Designs. ICCAD 2023: 1-4 - [i9]Yingjie Li, Mingju Liu, Mark Ren, Alan Mishchenko, Cunxi Yu:
DAG-aware Synthesis Orchestration. CoRR abs/2310.07846 (2023) - [i8]Yingjie Li, Mingju Liu, Alan Mishchenko, Cunxi Yu:
Verilog-to-PyG - A Framework for Graph Learning and Augmentation on RTL Designs. CoRR abs/2311.05722 (2023) - [i7]Dewmini Sudara Marakkalage, Eleonora Testa, Walter Lau Neto, Alan Mishchenko, Giovanni De Micheli, Luca G. Amarù:
Scalable Sequential Optimization Under Observability Don't Cares. CoRR abs/2311.09967 (2023) - 2022
- [j29]Siang-Yun Lee, Heinz Riener, Alan Mishchenko, Robert K. Brayton, Giovanni De Micheli:
A Simulation-Guided Paradigm for Logic Synthesis and Verification. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 41(8): 2573-2586 (2022) - [c112]Heinz Riener, Siang-Yun Lee, Alan Mishchenko, Giovanni De Micheli:
Boolean Rewriting Strikes Back: Reconvergence-Driven Windowing Meets Resynthesis. ASP-DAC 2022: 395-402 - [c111]Walter Lau Neto, Luca G. Amarù, Vinicius Possani, Patrick Vuillod, Jiong Luo, Alan Mishchenko, Pierre-Emmanuel Gaillardon:
Improving LUT-based optimization for ASICs. DAC 2022: 421-426 - 2021
- [j28]Dewmini Sudara Marakkalage, Eleonora Testa, Heinz Riener, Alan Mishchenko, Mathias Soeken, Giovanni De Micheli:
Three-Input Gates for Logic Synthesis. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 40(10): 2184-2188 (2021) - [c110]Luca Gaetano Amarù, Vinicius N. Possani, Eleonora Testa, Felipe S. Marranghello, Christopher Casares, Jiong Luo, Patrick Vuillod, Alan Mishchenko, Giovanni De Micheli:
LUT-Based Optimization For ASIC Design Flow. DAC 2021: 871-876 - [c109]He-Teng Zhang, Jie-Hong R. Jiang, Luca G. Amarù, Alan Mishchenko, Robert K. Brayton:
Deep Integration of Circuit Simulator and SAT Solver. DAC 2021: 877-882 - [c108]Shubham Rai, Walter Lau Neto, Yukio Miyasaka, Xinpei Zhang, Mingfei Yu, Qingyang Yi, Masahiro Fujita, Guilherme B. Manske, Matheus F. Pontes, Leomar S. da Rosa, Marilton S. de Aguiar, Paulo F. Butzen, Po-Chun Chien, Yu-Shan Huang, Hoa-Ren Wang, Jie-Hong R. Jiang, Jiaqi Gu, Zheng Zhao, Zixuan Jiang, David Z. Pan, Brunno A. Abreu, Isac de Souza Campos, Augusto Andre Souza Berndt, Cristina Meinhardt, Jônata Tyska Carvalho, Mateus Grellert, Sergio Bampi, Aditya Lohana, Akash Kumar, Wei Zeng, Azadeh Davoodi, Rasit Onur Topaloglu, Yuan Zhou, Jordan Dotzel, Yichi Zhang, Hanyu Wang, Zhiru Zhang, Valerio Tenace, Pierre-Emmanuel Gaillardon, Alan Mishchenko, Satrajit Chatterjee:
Logic Synthesis Meets Machine Learning: Trading Exactness for Generalization. DATE 2021: 1026-1031 - [c107]He-Teng Zhang, Jie-Hong R. Jiang, Alan Mishchenko:
A Circuit-Based SAT Solver for Logic Synthesis. ICCAD 2021: 1-6 - 2020
- [j27]Eleonora Testa, Luca G. Amarù, Mathias Soeken, Alan Mishchenko, Patrick Vuillod, Pierre-Emmanuel Gaillardon, Giovanni De Micheli:
Extending Boolean Methods for Scalable Logic Synthesis. IEEE Access 8: 226828-226844 (2020) - [j26]Xuegong Zhou, Lingli Wang, Alan Mishchenko:
Fast Exact NPN Classification by Co-Designing Canonical Form and Its Computation Algorithm. IEEE Trans. Computers 69(9): 1293-1307 (2020) - [j25]Winston Haaswijk, Mathias Soeken, Alan Mishchenko, Giovanni De Micheli:
SAT-Based Exact Synthesis: Encodings, Topology Families, and Parallelism. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 39(4): 871-884 (2020) - [j24]Vinicius N. Possani, Alan Mishchenko, Renato P. Ribas, André Inácio Reis:
Parallel Combinational Equivalence Checking. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 39(10): 3081-3092 (2020) - [c106]Luca G. Amarù, Felipe S. Marranghello, Eleonora Testa, Christopher Casares, Vinicius N. Possani, Jiong Luo, Patrick Vuillod, Alan Mishchenko, Giovanni De Micheli:
SAT-Sweeping Enhanced for Logic Synthesis. DAC 2020: 1-6 - [c105]Chang Meng, Weikang Qian, Alan Mishchenko:
ALSRAC: Approximate Logic Synthesis by Resubstitution with Approximate Care Set. DAC 2020: 1-6 - [c104]Heinz Riener, Alan Mishchenko, Mathias Soeken:
Exact DAG-Aware Rewriting. DATE 2020: 732-737 - [c103]Satrajit Chatterjee, Alan Mishchenko:
Circuit-Based Intrinsic Methods to Detect Overfitting. ICML 2020: 1459-1468 - [c102]Alan Mishchenko:
Keynote III: Boolean Logic Networks for Machine Learning. ISMVL 2020: xx - [c101]Yukio Miyasaka, Masahiro Fujita, Alan Mishchenko, John Wawrzynek:
SAT-Based Mapping of Data-Flow Graphs onto Coarse-Grained Reconfigurable Arrays. VLSI-SoC (Selected Papers) 2020: 113-131 - [i6]Siang-Yun Lee, Heinz Riener, Alan Mishchenko, Robert K. Brayton, Giovanni De Micheli:
Simulation-Guided Boolean Resubstitution. CoRR abs/2007.02579 (2020) - [i5]Shubham Rai, Walter Lau Neto, Yukio Miyasaka, Xinpei Zhang, Mingfei Yu, Qingyang Yi, Masahiro Fujita, Guilherme B. Manske, Matheus F. Pontes, Leomar S. da Rosa Jr., Marilton S. de Aguiar, Paulo F. Butzen, Po-Chun Chien, Yu-Shan Huang, Hoa-Ren Wang, Jie-Hong R. Jiang, Jiaqi Gu, Zheng Zhao, Zixuan Jiang, David Z. Pan, Brunno A. Abreu, Isac de Souza Campos, Augusto Andre Souza Berndt, Cristina Meinhardt, Jônata Tyska Carvalho, Mateus Grellert, Sergio Bampi, Aditya Lohana, Akash Kumar, Wei Zeng, Azadeh Davoodi, Rasit Onur Topaloglu, Yuan Zhou, Jordan Dotzel, Yichi Zhang, Hanyu Wang, Zhiru Zhang, Valerio Tenace, Pierre-Emmanuel Gaillardon, Alan Mishchenko, Satrajit Chatterjee:
Logic Synthesis Meets Machine Learning: Trading Exactness for Generalization. CoRR abs/2012.02530 (2020)
2010 – 2019
- 2019
- [j23]Augusto Neutzling, Jody Maick Matos, Alan Mishchenko, André Inácio Reis, Renato P. Ribas:
Effective Logic Synthesis for Threshold Logic Circuit Design. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 38(5): 926-937 (2019) - [j22]Xuegong Zhou, Lingli Wang, Alan Mishchenko:
Fast Adjustable NPN Classification Using Generalized Symmetries. ACM Trans. Reconfigurable Technol. Syst. 12(2): 7:1-7:16 (2019) - [c100]Heinz Riener, Eleonora Testa, Winston Haaswijk, Alan Mishchenko, Luca G. Amarù, Giovanni De Micheli, Mathias Soeken:
Scalable Generic Logic Synthesis: One Approach to Rule Them All. DAC 2019: 70 - [c99]Eleonora Testa, Luca G. Amarù, Mathias Soeken, Alan Mishchenko, Patrick Vuillod, Jiong Luo, Christopher Casares, Pierre-Emmanuel Gaillardon, Giovanni De Micheli:
Scalable Boolean Methods in a Modern Synthesis Flow. DATE 2019: 1643-1648 - [c98]Heinz Riener, Winston Haaswijk, Alan Mishchenko, Giovanni De Micheli, Mathias Soeken:
On-the-fly and DAG-aware: Rewriting Boolean Networks with Exact Synthesis. DATE 2019: 1649-1654 - [c97]Bruno Schmitt, Mathias Soeken, Giovanni De Micheli, Alan Mishchenko:
Scaling-up ESOP Synthesis for Quantum Compilation. ISMVL 2019: 13-18 - [c96]Heinz Riener, Eleonora Testa, Winston Haaswijk, Alan Mishchenko, Luca G. Amarù, Giovanni De Micheli, Mathias Soeken:
Logic Optimization of Majority-Inverter Graphs. MBMV 2019: 1-4 - [c95]Augusto Andre Souza Berndt, Alan Mishchenko, Paulo Francisco Butzen, André Inácio Reis:
Reduction of neural network circuits by constant and nearly constant signal propagation. SBCCI 2019: 29 - [i4]Satrajit Chatterjee, Alan Mishchenko:
Circuit-Based Intrinsic Methods to Detect Overfitting. CoRR abs/1907.01991 (2019) - 2018
- [j21]Mathias Soeken, Eleonora Testa, Alan Mishchenko, Giovanni De Micheli:
Pairs of majority-decomposing functions. Inf. Process. Lett. 139: 35-38 (2018) - [j20]Cunxi Yu, Maciej J. Ciesielski, Alan Mishchenko:
Fast Algebraic Rewriting Based on And-Inverter Graphs. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 37(9): 1907-1911 (2018) - [j19]Ai Quoc Dao, Mark Po-Hung Lin, Alan Mishchenko:
SAT-Based Fault Equivalence Checking in Functional Safety Verification. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 37(12): 3198-3205 (2018) - [c94]Bruno de O. Schmitt, Alan Mishchenko, Robert K. Brayton:
SAT-based area recovery in structural technology mapping. ASP-DAC 2018: 586-591 - [c93]Ai Quoc Dao, Nian-Ze Lee, Li-Cheng Chen, Mark Po-Hung Lin, Jie-Hong R. Jiang, Alan Mishchenko, Robert K. Brayton:
Efficient computation of ECO patch functions. DAC 2018: 51:1-51:6 - [c92]Alan Mishchenko, Robert K. Brayton, Ana Petkovska, Mathias Soeken, Luca G. Amarù, Antun Domic:
Canonical computation without canonical representation. DAC 2018: 52:1-52:6 - [c91]Winston Haaswijk, Alan Mishchenko, Mathias Soeken, Giovanni De Micheli:
SAT based exact synthesis using DAG topology families. DAC 2018: 53:1-53:6 - [c90]Mathias Soeken, Winston Haaswijk, Eleonora Testa, Alan Mishchenko, Luca Gaetano Amarù, Robert K. Brayton, Giovanni De Micheli:
Practical exact synthesis. DATE 2018: 309-314 - [c89]Luca Gaetano Amarù, Mathias Soeken, Patrick Vuillod, Jiong Luo, Alan Mishchenko, Janet Olson, Robert K. Brayton, Giovanni De Micheli:
Improvements to boolean resynthesis. DATE 2018: 755-760 - [c88]Wenyi Feng, Jonathan W. Greene, Alan Mishchenko:
Improving FPGA Performance with a S44 LUT Structure. FPGA 2018: 61-66 - [c87]Xuegong Zhou, Lingli Wang, Peiyi Zhao, Alan Mishchenko:
Fast Adjustable NPN Classification using Generalized Symmetries. FPL 2018: 1-7 - [c86]Vinicius N. Possani, Yi-Shan Lu, Alan Mishchenko, Keshav Pingali, Renato P. Ribas, André Inácio Reis:
Unlocking fine-grain parallelism for AIG rewriting. ICCAD 2018: 87 - [c85]Cunxi Yu, Atif Yasin, Tiankai Su, Alan Mishchenko, Maciej J. Ciesielski:
Rewriting Environment for Arithmetic Circuit Verification. LPAR 2018: 656-666 - [p1]Ana Petkovska, Alan Mishchenko, David Novo, Muhsen Owaida, Paolo Ienne:
Progressive Generation of Canonical Irredundant Sums of Products Using a SAT Solver. Advanced Logic Synthesis 2018: 169-188 - 2017
- [j18]Gianpiero Cabodi, Paolo Camurati, Alan Mishchenko, Marco Palena, Paolo Pasini:
SAT solver management strategies in IC3: an experimental approach. Formal Methods Syst. Des. 50(1): 39-74 (2017) - [j17]Nurul Ain Binti Adnan, Shigeru Yamashita, Alan Mishchenko:
Reduction of Quantum Cost by Making Temporary Changes to the Function. IEICE Trans. Inf. Syst. 100-D(7): 1393-1402 (2017) - [c84]Bruno de O. Schmitt, Alan Mishchenko, Victor N. Kravets, Robert K. Brayton, André Inácio Reis:
Fast-extract with cube hashing. ASP-DAC 2017: 145-150 - [c83]Mathias Soeken, Giovanni De Micheli, Alan Mishchenko:
Busy man's synthesis: Combinational delay optimization with SAT. DATE 2017: 830-835 - [c82]Yen-Sheng Ho, Alan Mishchenko, Robert K. Brayton:
Property directed reachability with word-level abstraction. FMCAD 2017: 132-139 - [c81]Luca Gaetano Amarù, Mathias Soeken, Patrick Vuillod, Jiong Luo, Alan Mishchenko, Pierre-Emmanuel Gaillardon, Janet Olson, Robert K. Brayton, Giovanni De Micheli:
Enabling exact delay synthesis. ICCAD 2017: 352-359 - 2016
- [j16]Hamid Savoj, Alan Mishchenko, Robert K. Brayton:
m-Inductive Property of Sequential Circuits. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 35(6): 919-930 (2016) - [c80]Valeriy Balabanov, Jie-Hong Roland Jiang, Alan Mishchenko, Christoph Scholl:
Clauses Versus Gates in CEGAR-Based 2QBF Solving. AAAI Workshop: Beyond NP 2016 - [c79]Yen-Sheng Ho, Pankaj Chauhan, Pritam Roy, Alan Mishchenko, Robert K. Brayton:
Efficient uninterpreted function abstraction and refinement for word-level model checking. FMCAD 2016: 65-72 - [c78]Ana Petkovska, Mathias Soeken, Giovanni De Micheli, Paolo Ienne, Alan Mishchenko:
Fast hierarchical NPN classification. FPL 2016: 1-4 - [c77]Ana Petkovska, Alan Mishchenko, Mathias Soeken, Giovanni De Micheli, Robert K. Brayton, Paolo Ienne:
Fast generation of lexicographic satisfiable assignments: enabling canonicity in SAT-based applications. ICCAD 2016: 4 - [c76]Mathias Soeken, Alan Mishchenko, Ana Petkovska, Baruch Sterin, Paolo Ienne, Robert K. Brayton, Giovanni De Micheli:
Heuristic NPN Classification for Large Functions Using AIGs and LEXSAT. SAT 2016: 212-227 - [c75]Valeriy Balabanov, Jie-Hong Roland Jiang, Christoph Scholl, Alan Mishchenko, Robert K. Brayton:
2QBF: Challenges and Solutions. SAT 2016: 453-469 - 2015
- [j15]Tiziano Villa, Alexandre Petrenko, Nina Yevtushenko, Alan Mishchenko, Robert K. Brayton:
Component-Based Design by Solving Language Equations. Proc. IEEE 103(11): 2152-2167 (2015) - [c74]Alan Mishchenko, Robert K. Brayton, Wenyi Feng, Jonathan W. Greene:
Technology Mapping into General Programmable Cells. FPGA 2015: 70-73 - [c73]Ana Petkovska, Grace Zgheib, David Novo, Muhsen Owaida, Alan Mishchenko, Paolo Ienne:
Improved carry chain mapping for the VTR flow. FPT 2015: 80-87 - [c72]Augusto Neutzling, Jody Maick Matos, André Inácio Reis, Renato P. Ribas, Alan Mishchenko:
Threshold Logic Synthesis Based on Cut Pruning. ICCAD 2015: 494-499 - [c71]Masahiro Fujita, Naoki Taguchi, Kentaro Iwata, Alan Mishchenko:
Incremental ATPG methods for multiple faults under multiple fault models. ISQED 2015: 177-180 - [c70]Luca Gaetano Amarù, Pierre-Emmanuel Gaillardon, Alan Mishchenko, Maciej J. Ciesielski, Giovanni De Micheli:
Exploiting Circuit Duality to Speed up SAT. ISVLSI 2015: 101-106 - [c69]Giovanni Castagnetti, Matteo Piccolo, Tiziano Villa, Nina Yevtushenko, Robert K. Brayton, Alan Mishchenko:
Automated Synthesis of Protocol Converters with BALM-II. SEFM Workshops 2015: 281-296 - 2014
- [j14]Hamid Savoj, Alan Mishchenko, Robert K. Brayton:
Sequential Equivalence Checking for Clock-Gated Circuits. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 33(2): 305-317 (2014) - [c68]Aadithya V. Karthik, Sayak Ray, Pierluigi Nuzzo, Alan Mishchenko, Robert K. Brayton, Jaijeet Roychowdhury:
ABCD-NL: Approximating Continuous non-linear dynamical systems using purely Boolean models for analog/mixed-signal verification. ASP-DAC 2014: 250-255 - [c67]Aadithya V. Karthik, David Soloveichik, Sayak Ray, Baruch Sterin, Alan Mishchenko, Robert K. Brayton, Jaijeet Roychowdhury:
NINJA: boolean modelling and formal verification of tiered-rate chemical reaction networks (extended abstract). BCB 2014: 623-624 - [c66]Ana Petkovska, David Novo, Alan Mishchenko, Paolo Ienne:
Constrained interpolation for guided logic synthesis. ICCAD 2014: 462-469 - [c65]Masahiro Fujita, Alan Mishchenko:
Efficient SAT-based ATPG techniques for all multiple stuck-at faults. ITC 2014: 1-10 - [c64]Masahiro Fujita, Alan Mishchenko:
Logic synthesis and verification on fixed topology. VLSI-SoC 2014: 1-6 - 2013
- [c63]Alan Mishchenko, Niklas Eén, Robert K. Brayton, Michael L. Case, Pankaj Chauhan, Nikhil Sharma:
A semi-canonical form for sequential AIGs. DATE 2013: 797-802 - [c62]Alan Mishchenko, Niklas Eén, Robert K. Brayton, Jason Baumgartner, Hari Mony, Pradeep Kumar Nalla:
GLA: gate-level abstraction revisited. DATE 2013: 1399-1404 - [c61]Anton Belov, Huan Chen, Alan Mishchenko, João Marques-Silva:
Core minimization in SAT-based abstraction. DATE 2013: 1411-1416 - [c60]Niklas Eén, Alan Mishchenko:
A Fast Reparameterization Procedure. DIFTS@FMCAD 2013 - [c59]Marco Palena, Gianpiero Cabodi, Alan Mishchenko:
Trading-off Incrementality and Dynamic Restart of Multiple Solvers in IC3. DIFTS@FMCAD 2013 - [c58]Zheng Huang, Lingli Wang, Yakov Nasikovskiy, Alan Mishchenko:
Fast Boolean matching based on NPN classification. FPT 2013: 310-313 - 2012
- [c57]Sayak Ray, Alan Mishchenko, Niklas Eén, Robert K. Brayton, Stephen Jang, Chao Chen:
Mapping into LUT structures. DATE 2012: 1579-1584 - [c56]Wenlong Yang, Lingli Wang, Alan Mishchenko:
Lazy man's logic synthesis. ICCAD 2012: 597-604 - 2011
- [j13]Alan Mishchenko, Robert K. Brayton, Jie-Hong R. Jiang, Stephen Jang:
Scalable don't-care-based logic optimization and resynthesis. ACM Trans. Reconfigurable Technol. Syst. 4(4): 34:1-34:23 (2011) - [c55]Niklas Eén, Alan Mishchenko, Robert K. Brayton:
Efficient implementation of property directed reachability. FMCAD 2011: 125-134 - [c54]Jiang Long, Sayak Ray, Baruch Sterin, Alan Mishchenko, Robert K. Brayton:
Enhancing ABC for stabilization verification of SystemVerilog/VHDL models. DIFTS@FMCAD 2011 - [c53]Alan Mishchenko, Robert K. Brayton, Stephen Jang, Victor N. Kravets:
Delay optimization using SOP balancing. ICCAD 2011: 375-382 - 2010
- [j12]Jie-Hong Roland Jiang, Chih-Chun Lee, Alan Mishchenko, Chung-Yang Huang:
To SAT or Not to SAT: Scalable Exploration of Functional Dependency. IEEE Trans. Computers 59(4): 457-467 (2010) - [j11]Kai-Hui Chang, Valeria Bertacco, Igor L. Markov, Alan Mishchenko:
Logic synthesis and circuit customization using extensive external don't-cares. ACM Trans. Design Autom. Electr. Syst. 15(3): 26:1-26:24 (2010) - [c52]Robert K. Brayton, Alan Mishchenko:
ABC: An Academic Industrial-Strength Verification Tool. CAV 2010: 24-40 - [c51]Dmitri B. Strukov, Alan Mishchenko:
Monolithically stackable hybrid FPGA. DATE 2010: 661-666 - [c50]Hamid Savoj, David Berthelot, Alan Mishchenko, Robert K. Brayton:
Combinational techniques for sequential equivalence checking. FMCAD 2010: 145-149 - [c49]Niklas Eén, Alan Mishchenko, Nina Amla:
A single-instance incremental SAT formulation of proof- and counterexample-based abstraction. FMCAD 2010: 181-188 - [c48]Alan Mishchenko, Robert K. Brayton, Stephen Jang:
Global delay optimization using structural choices. FPGA 2010: 181-184 - [c47]Andrew A. Kennings, Alan Mishchenko, Kristofer Vorwerk, Val Pevzner, Arun Kundu:
Efficient FPGA Resynthesis Using Precomputed LUT Structures. FPL 2010: 532-537 - [i3]Niklas Eén, Alan Mishchenko, Nina Amla:
A Single-Instance Incremental SAT Formulation of Proof- and Counterexample-Based Abstraction. CoRR abs/1008.2021 (2010)
2000 – 2009
- 2009
- [j10]Stephen Jang, Billy Chan, Kevin Chung, Alan Mishchenko:
WireMap: FPGA Technology Mapping for Improved Routability and Enhanced LUT Merging. ACM Trans. Reconfigurable Technol. Syst. 2(2): 14:1-14:24 (2009) - [c46]Victor N. Kravets, Alan Mishchenko:
Sequential logic synthesis using symbolic bi-decomposition. DATE 2009: 1458-1463 - [c45]Hari Mony, Jason Baumgartner, Alan Mishchenko, Robert K. Brayton:
Speculative reduction-based scalable redundancy identification. DATE 2009: 1674-1679 - [c44]Alan Mishchenko, Robert K. Brayton, Jie-Hong Roland Jiang, Stephen Jang:
Scalable don't-care-based logic optimization and resynthesis. FPGA 2009: 151-160 - [c43]Stephen Jang, Dennis Wu, Mark Jarvin, Billy Chan, Kevin Chung, Alan Mishchenko, Robert K. Brayton:
SmartOpt: an industrial strength framework for logic synthesis. FPGA 2009: 237-240 - 2008
- [c42]Aaron P. Hurst, Alan Mishchenko, Robert K. Brayton:
Scalable min-register retiming under timing and initializability constraints. DAC 2008: 534-539 - [c41]Michael L. Case, Victor N. Kravets, Alan Mishchenko, Robert K. Brayton:
Merging nodes under sequential observability. DAC 2008: 540-545 - [c40]Michael L. Case, Alan Mishchenko, Robert K. Brayton, Jason Baumgartner, Hari Mony:
Invariant-Strengthened Elimination of Dependent State Elements. FMCAD 2008: 1-9 - [c39]Alan Mishchenko, Robert K. Brayton:
Recording Synthesis History for Sequential Verification. FMCAD 2008: 1-8 - [c38]Stephen Jang, Billy Chan, Kevin Chung, Alan Mishchenko:
WireMap: FPGA technology mapping for improved routability. FPGA 2008: 47-55 - [c37]Alan Mishchenko, Robert K. Brayton, Satrajit Chatterjee:
Boolean factoring and decomposition of logic networks. ICCAD 2008: 38-44 - [c36]Alan Mishchenko, Michael L. Case, Robert K. Brayton, Stephen Jang:
Scalable and scalably-verifiable sequential synthesis. ICCAD 2008: 234-241 - 2007
- [j9]Alan Mishchenko, Satrajit Chatterjee, Robert K. Brayton:
Improvements to Technology Mapping for LUT-Based FPGAs. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 26(2): 240-253 (2007) - [c35]Satrajit Chatterjee, Alan Mishchenko, Robert K. Brayton, Andreas Kuehlmann:
On Resolution Proofs for Combinational Equivalence. DAC 2007: 600-605 - [c34]Michael L. Case, Alan Mishchenko, Robert K. Brayton:
Automated Extraction of Inductive Invariants to Aid Model Checking. FMCAD 2007: 165-172 - [c33]Aaron P. Hurst, Alan Mishchenko, Robert K. Brayton:
Fast Minimum-Register Retiming via Binary Maximum-Flow. FMCAD 2007: 181-187 - [c32]Chih-Chun Lee, Jie-Hong Roland Jiang, Chung-Yang Huang, Alan Mishchenko:
Scalable exploration of functional dependency by interpolation and incremental SAT solving. ICCAD 2007: 227-233 - [c31]Alan Mishchenko, Sungmin Cho, Satrajit Chatterjee, Robert K. Brayton:
Combinational and sequential mapping with priority cuts. ICCAD 2007: 354-361 - [c30]Niklas Eén, Alan Mishchenko, Niklas Sörensson:
Applying Logic Synthesis for Speeding Up SAT. SAT 2007: 272-286 - [i2]Alan Mishchenko, Robert K. Brayton:
SAT-Based Complete Don't-Care Computation for Network Optimization. CoRR abs/0710.4695 (2007) - [i1]Alan Mishchenko, Robert K. Brayton, Jie-Hong Roland Jiang, Tiziano Villa, Nina Yevtushenko:
Efficient Solution of Language Equations Using Partitioned Representations. CoRR abs/0710.4743 (2007) - 2006
- [j8]Alan Mishchenko, Jin S. Zhang, Subarnarekha Sinha, Jerry R. Burch, Robert K. Brayton, Malgorzata Chrzanowska-Jeske:
Using simulation and satisfiability to compute flexibilities in Boolean networks. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 25(5): 743-755 (2006) - [j7]Alan Mishchenko, Robert K. Brayton:
A theory of nondeterministic networks. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 25(6): 977-999 (2006) - [j6]Jin S. Zhang, Malgorzata Chrzanowska-Jeske, Alan Mishchenko, Jerry R. Burch:
Linear cofactor relationships in Boolean functions. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 25(6): 1011-1023 (2006) - [j5]Satrajit Chatterjee, Alan Mishchenko, Robert K. Brayton, Xinning Wang, Timothy Kam:
Reducing Structural Bias in Technology Mapping. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 25(12): 2894-2903 (2006) - [c29]Jin S. Zhang, Alan Mishchenko, Robert K. Brayton, Malgorzata Chrzanowska-Jeske:
Symmetry detection for large Boolean functions using circuit representation, simulation, and satisfiability. DAC 2006: 510-515 - [c28]Alan Mishchenko, Satrajit Chatterjee, Robert K. Brayton:
DAG-aware AIG rewriting a fresh look at combinational logic synthesis. DAC 2006: 532-535 - [c27]Alan Mishchenko, Satrajit Chatterjee, Robert K. Brayton:
Improvements to technology mapping for LUT-based FPGAs. FPGA 2006: 41-49 - [c26]Satrajit Chatterjee, Alan Mishchenko, Robert K. Brayton:
Factor cuts. ICCAD 2006: 143-150 - [c25]Alan Mishchenko, Satrajit Chatterjee, Robert K. Brayton, Niklas Eén:
Improvements to combinational equivalence checking. ICCAD 2006: 836-843 - 2005
- [j4]Shinobu Nagayama, Alan Mishchenko, Tsutomu Sasao, Jon T. Butler:
Exact and Heuristic Minimization of the Average Path Length in Decision Diagrams. J. Multiple Valued Log. Soft Comput. 11(5-6): 437-465 (2005) - [c24]Jin S. Zhang, Malgorzata Chrzanowska-Jeske, Alan Mishchenko, Jerry R. Burch:
Detecting support-reducing bound sets using two-cofactor symmetries. ASP-DAC 2005: 266-271 - [c23]Alan Mishchenko, Robert K. Brayton:
SAT-Based Complete Don't-Care Computation for Network Optimization. DATE 2005: 412-417 - [c22]Alan Mishchenko, Robert K. Brayton, Jie-Hong Roland Jiang, Tiziano Villa, Nina Yevtushenko:
Efficient Solution of Language Equations Using Partitioned Representations. DATE 2005: 418-423 - [c21]Satrajit Chatterjee, Alan Mishchenko, Robert K. Brayton, Xinning Wang, Timothy Kam:
Reducing structural bias in technology mapping. ICCAD 2005: 519-526 - [c20]Malgorzata Chrzanowska-Jeske, Alan Mishchenko:
Synthesis for regularity using decision diagrams [logic IC synthesis and layout]. ISCAS (5) 2005: 4721-4724 - 2004
- [c19]Jie-Hong Roland Jiang, Alan Mishchenko, Robert K. Brayton:
On breakable cyclic definitions. ICCAD 2004: 411-418 - 2003
- [j3]Alan Mishchenko:
Fast computation of symmetries in Boolean functions. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 22(11): 1588-1593 (2003) - [j2]Xiaoyu Song, William N. N. Hung, Alan Mishchenko, Malgorzata Chrzanowska-Jeske, Andrew A. Kennings, Alan J. Coppola:
Board-level multiterminal net assignment for the partial cross-bar architecture. IEEE Trans. Very Large Scale Integr. Syst. 11(3): 511-514 (2003) - [c18]Alan Mishchenko, Xinning Wang, Timothy Kam:
A new enhanced constructive decomposition and mapping algorithm. DAC 2003: 143-148 - [c17]Alan Mishchenko, Tsutomu Sasao:
Large-scale SOP minimization using decomposition and functional properties. DAC 2003: 149-154 - [c16]Jie-Hong Roland Jiang, Alan Mishchenko, Robert K. Brayton:
Reducing Multi-Valued Algebraic Operations to Binary. DATE 2003: 10752-10757 - [c15]Alan Mishchenko, Robert K. Brayton:
A Theory of Non-Deterministic Networks. ICCAD 2003: 709-717 - 2002
- [j1]Malgorzata Chrzanowska-Jeske, Alan Mishchenko, Marek A. Perkowski:
Generalized Inclusive Forms - New Canonical Reed-Muller Forms Including Minimum ESOPs. VLSI Design 14(1): 13-21 (2002) - [c14]Xiaoyu Song, William N. N. Hung, Alan Mishchenko, Malgorzata Chrzanowska-Jeske, Alan J. Coppola, Andrew A. Kennings:
Board-level multiterminal net assignment. ACM Great Lakes Symposium on VLSI 2002: 130-135 - [c13]Alan Mishchenko, Robert K. Brayton:
Simplification of non-deterministic multi-valued networks. ICCAD 2002: 557-562 - [c12]Subarnarekha Sinha, Alan Mishchenko, Robert K. Brayton:
Topologically constrained logic synthesis. ICCAD 2002: 679-686 - [c11]Robert K. Brayton, M. Gao, Jie-Hong Roland Jiang, Yunjian Jiang, Yinghua Li, Alan Mishchenko, Subarnarekha Sinha, Tiziano Villa:
Optimization of Multi-Valued Multi-Level Networks. ISMVL 2002: 168-179 - [c10]Subarnarekha Sinha, Alan Mishchenko, Robert K. Brayton:
Topologically Constrained Logic Synthesis. IWLS 2002: 13-20 - [c9]Alan Mishchenko, Tsutomu Sasao:
Encoding of Boolean Functions and its Application to LUT Cascade Synthesis. IWLS 2002: 115-120 - [c8]Alan Mishchenko, Robert K. Brayton:
A Boolean Paradigm in Multi-Valued Logic Synthesis. IWLS 2002: 173-177 - [c7]Alan Mishchenko, Marek A. Perkowski:
Logic Synthesis of Reversible Wave Cascades. IWLS 2002: 197-202 - [c6]Alan Mishchenko, Robert K. Brayton:
Simplification of Non-Deterministic Multi-Valued Networks. IWLS 2002: 333-338 - [c5]Jie-Hong Roland Jiang, Alan Mishchenko, Robert K. Brayton:
Reducing Multi-Valued Algebraic Operations to Binary. IWLS 2002: 339-344 - 2001
- [c4]Alan Mishchenko, Bernd Steinbach, Marek A. Perkowski:
An Algorithm for Bi-Decomposition of Logic Functions. DAC 2001: 103-108 - [c3]Marek A. Perkowski, Malgorzata Chrzanowska-Jeske, Alan Mishchenko, Xiaoyu Song, Anas Al-Rabadi, Bart Massey, Pawel Kerntopf, Andrzej Buller, Lech Józwiak, Alan J. Coppola:
Regular Realization of Symmetric Functions Using Reversible Logic. DSD 2001: 245-253
1990 – 1999
- 1999
- [c2]Marek A. Perkowski, Rahul Malvi, Stan Grygiel, Michael Burns, Alan Mishchenko:
Graph Coloring Algorithms for Fast Evaluation of Curtis Decompositions. DAC 1999: 225-230 - [c1]Marek A. Perkowski, Alan Mishchenko, Anatoli N. Chebotarev:
Evolvable Hardware or Learning Hardware? Induction of State Machines from Temporal Logic Constraints. Evolvable Hardware 1999: 129-138
Coauthor Index
Luca G. Amarù
aka: Luca Gaetano Amarù
aka: Luca Gaetano Amarù
[i10] [j29] [c109] [i6] [c94] [c93] [c92] [c90] [c89] [c84] [c82] [c81] [j16] [c79] [c77] [c76] [c75] [j15] [c74] [c69] [j14] [c68] [c67] [c63] [c62] [c57] [j13] [c55] [c54] [c53] [c52] [c50] [c48] [c45] [c44] [c43] [c42] [c41] [c40] [c39] [c37] [c36] [j9] [c35] [c34] [c33] [c31] [i2] [i1] [j8] [j7] [j5] [c29] [c28] [c27] [c26] [c25] [c23] [c22] [c21] [c19] [c16] [c15] [c13] [c12] [c11] [c10] [c8] [c6] [c5]
Jie-Hong Roland Jiang
aka: Jie-Hong R. Jiang
aka: Jie-Hong R. Jiang
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