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2010 – 2019
- 2011
[j4]Sang-Yoon Lee, Hyung-Rok Lee, Young-Ho Kwak, Woo-Seok Choi, Byoung-Joo Yoo, Daeyun Shim, Chulwoo Kim, Deog-Kyoon Jeong:
250 Mbps-5 Gbps Wide-Range CDR With Digital Vernier Phase Shifting and Dual-Mode Control in 0.13 μ m CMOS. IEEE J. Solid State Circuits 46(11): 2560-2570 (2011)
2000 – 2009
- 2006
- [c2]Yongsam Moon, Gijung Ahn, Hoon Choi, Namhoon Kim, Daeyun Shim:
A Quad 6Gb/s Multi-rate CMOS Transceiver with TX Rise/Fall-Time Control. ISSCC 2006: 233-242 - 2005
- [j3]Yongsam Moon, Sang-Hyun Lee, Daeyun Shim:
A divide-by-16.5 circuit for 10-gb ethernet transceiver in 0.13-μm CMOS. IEEE J. Solid State Circuits 40(5): 1175-1179 (2005) - 2001
- [j2]Yeon-Jae Jung, Seung-Wook Lee, Daeyun Shim, Wonchan Kim, Changhyun Kim, Soo-In Cho:
A dual-loop delay-locked loop using multiple voltage-controlled delay lines. IEEE J. Solid State Circuits 36(5): 784-791 (2001)
1990 – 1999
- 1999
- [j1]Daeyun Shim, Dong-Yun Lee, Sanghun Jung, Chang-Hyun Kim, Wonchan Kim:
An analog synchronous mirror delay for high-speed DRAM application. IEEE J. Solid State Circuits 34(4): 484-493 (1999) - [c1]Seung-Wook Lee, Daeyun Shim, Yeon-Jae Jung, Dong-Yun Lee, Chang-Hyun Kim, Wonchan Kim:
A load-adaptive, low switching-noise data output buffer. ISCAS (1) 1999: 39-42
Coauthor Index
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