Provider: Schloss Dagstuhl - Leibniz Center for Informatics
Database: dblp computer science bibliography
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TY - JOUR
ID - DBLP:journals/esticas/SuRMVKIBN24
AU - Su, Zhe
AU - Ramini, Simone
AU - Marcolin, Demetra Coffen
AU - Veronesi, Alessandro
AU - Krstic, Milos
AU - Indiveri, Giacomo
AU - Bertozzi, Davide
AU - Nowick, Steven M.
TI - An Ultra-Low Cost and Multicast-Enabled Asynchronous NoC for Neuromorphic Edge Computing.
JO - IEEE J. Emerg. Sel. Topics Circuits Syst.
VL - 14
IS - 3
SP - 409
EP - 424
PY - 2024/09/
DO - 10.1109/JETCAS.2024.3433427
UR - https://doi.org/10.1109/JETCAS.2024.3433427
ER -
TY - JOUR
ID - DBLP:journals/jsac/KhalidFBBFTBPC24
AU - Khalid, Muhammad
AU - Ferraresi, Simone
AU - Bellanca, Gaetano
AU - Barbiroli, Marina
AU - Fuschini, Franco
AU - Tralli, Velio
AU - Bertozzi, Davide
AU - Petruzzelli, Vincenzo
AU - Calò, Giovanna
TI - LNOI Wireless Switches Based on Optical Phased Arrays for On-Chip Communication.
JO - IEEE J. Sel. Areas Commun.
VL - 42
IS - 8
SP - 2054
EP - 2065
PY - 2024/08/
DO - 10.1109/JSAC.2024.3399207
UR - https://doi.org/10.1109/JSAC.2024.3399207
ER -
TY - CPAPER
ID - DBLP:conf/date/GavioliBBB24
AU - Gavioli, Federico
AU - Brilli, Gianluca
AU - Burgio, Paolo
AU - Bertozzi, Davide
TI - Adaptive Localization for Autonomous Racing Vehicles with Resource-Constrained Embedded Platforms.
BT - Design, Automation & Test in Europe Conference & Exhibition, DATE 2024, Valencia, Spain, March 25-27, 2024
SP - 1
EP - 6
PY - 2024//
DO - 10.23919/DATE58400.2024.10546748
UR - https://doi.org/10.23919/DATE58400.2024.10546748
ER -
TY - CPAPER
ID - DBLP:conf/ets/VeronesiNPKFCMBB24
AU - Veronesi, Alessandro
AU - Nazzari, Alessandro
AU - Passarello, Dario
AU - Krstic, Milos
AU - Favalli, Michele
AU - Cassano, Luca
AU - Miele, Antonio
AU - Bertozzi, Davide
AU - Bolchini, Cristiana
TI - Cross-Layer Reliability Analysis of NVDLA Accelerators: Exploring the Configuration Space.
BT - IEEE European Test Symposium, ETS 2024, The Hague, Netherlands, May 20-24, 2024
SP - 1
EP - 6
PY - 2024//
DO - 10.1109/ETS61313.2024.10568018
UR - https://doi.org/10.1109/ETS61313.2024.10568018
ER -
TY - CPAPER
ID - DBLP:conf/icton/KhalidCBNBFTBP23
AU - Khalid, M.
AU - Calò, Giovanna
AU - Bellanca, Gaetano
AU - Nanni, Jacopo
AU - Barbiroli, Marina
AU - Fuschini, Franco
AU - Tralli, Velio
AU - Bertozzi, Davide
AU - Petruzzelli, Vincenzo
TI - Integrated Optical Phased Arrays for on-Chip Communication.
BT - 23rd International Conference on Transparent Optical Networks, ICTON 2023, Bucharest, Romania, July 2-6, 2023
SP - 1
EP - 4
PY - 2023//
DO - 10.1109/ICTON59386.2023.10207378
UR - https://doi.org/10.1109/ICTON59386.2023.10207378
ER -
TY - CPAPER
ID - DBLP:conf/mcsoc/BellodiBBFFZ23
AU - Bellodi, Elena
AU - Bertozzi, Davide
AU - Bizzarri, Alice
AU - Favalli, Michele
AU - Fraccaroli, Michele
AU - Zese, Riccardo
TI - Efficient Resource-Aware Neural Architecture Search with a Neuro-Symbolic Approach.
BT - 16th IEEE International Symposium on Embedded Multicore/Many-core Systems-on-Chip, MCSoC 2023, Singapore, December 18-21, 2023
SP - 171
EP - 178
PY - 2023//
DO - 10.1109/MCSOC60832.2023.00034
UR - https://doi.org/10.1109/MCSoC60832.2023.00034
ER -
TY - CPAPER
ID - DBLP:conf/newcas/ReiserRRBFWZB23
AU - Reiser, Daniel
AU - Reichenbach, Marc
AU - Rizzi, Tommaso
AU - Baroni, Andrea
AU - Fritscher, Markus
AU - Wenger, Christian
AU - Zambelli, Cristian
AU - Bertozzi, Davide
TI - Technology-Aware Drift Resilience Analysis of RRAM Crossbar Array Configurations.
BT - 21st IEEE Interregional NEWCAS Conference, NEWCAS 2023, Edinburgh, United Kingdom, June 26-28, 2023
SP - 1
EP - 5
PY - 2023//
DO - 10.1109/NEWCAS57931.2023.10198076
UR - https://doi.org/10.1109/NEWCAS57931.2023.10198076
ER -
TY - CPAPER
ID - DBLP:conf/aicas/BertozziBN22
AU - Bertozzi, Davide
AU - Bhardwaj, Kshitij
AU - Nowick, Steven M.
TI - An Asynchronous Soft Macro for Ultra-Low Power Communication in Neuromorphic Computing.
BT - 4th IEEE International Conference on Artificial Intelligence Circuits and Systems, AICAS 2022, Incheon, Republic of Korea, June 13-15, 2022
SP - 178
EP - 181
PY - 2022//
DO - 10.1109/AICAS54282.2022.9869944
UR - https://doi.org/10.1109/AICAS54282.2022.9869944
ER -
TY - CPAPER
ID - DBLP:conf/ddecs/VeronesiDBFK22
AU - Veronesi, Alessandro
AU - Dall'Occo, Francesco
AU - Bertozzi, Davide
AU - Favalli, Michele
AU - Krstic, Milos
TI - Exploring Software Models for the Resilience Analysis of Deep Learning Accelerators: the NVDLA Case Study.
BT - 25th International Symposium on Design and Diagnostics of Electronic Circuits and Systems, DDECS 2022, Prague, Czech Republic, April 6-8, 2022
SP - 142
EP - 147
PY - 2022//
DO - 10.1109/DDECS54261.2022.9770169
UR - https://doi.org/10.1109/DDECS54261.2022.9770169
ER -
TY - JOUR
ID - DBLP:journals/micro/BertozziMGBSBJN21
AU - Bertozzi, Davide
AU - Miorandi, Gabriele
AU - Ghiribaldi, Alberto
AU - Burleson, Wayne P.
AU - Sadowski, Greg
AU - Bhardwaj, Kshitij
AU - Jiang, Weiwei
AU - Nowick, Steven M.
TI - Cost-Effective and Flexible Asynchronous Interconnect Technology for GALS Systems.
JO - IEEE Micro
VL - 41
IS - 1
SP - 69
EP - 81
PY - 2021//
DO - 10.1109/MM.2020.3002790
UR - https://doi.org/10.1109/MM.2020.3002790
ER -
TY - CPAPER
ID - DBLP:conf/dcis/RizziQWZB21
AU - Rizzi, Tommaso
AU - Quesada, Emilio Pérez-Bosch
AU - Wenger, Christian
AU - Zambelli, Cristian
AU - Bertozzi, Davide
TI - Comparative Analysis and Optimization of the SystemC-AMS Analog Simulation Efficiency of Resistive Crossbar Arrays.
BT - XXXVI Conference on Design of Circuits and Integrated Systems, DCIS 2021, Vila do Conde, Portugal, November 24-26, 2021
SP - 1
EP - 6
PY - 2021//
DO - 10.1109/DCIS53048.2021.9666193
UR - https://doi.org/10.1109/DCIS53048.2021.9666193
ER -
TY - CPAPER
ID - DBLP:conf/samos/DallOccoBABF21
AU - Dall'Occo, Francesco
AU - Bueno-Crespo, Andrés
AU - Abellán, José L.
AU - Bertozzi, Davide
AU - Favalli, Michele
TI - The Challenge of Classification Confidence Estimation in Dynamically-Adaptive Neural Networks.
BT - Embedded Computer Systems: Architectures, Modeling, and Simulation - 21st International Conference, SAMOS 2021, Virtual Event, July 4-8, 2021, Proceedings
SP - 505
EP - 522
PY - 2021//
DO - 10.1007/978-3-031-04580-6_34
UR - https://doi.org/10.1007/978-3-031-04580-6_34
ER -
TY - CPAPER
ID - DBLP:conf/slip/CaloBBBFTSP21
AU - Calò, Giovanna
AU - Barbiroli, Marina
AU - Bellanca, Gaetano
AU - Bertozzi, Davide
AU - Fuschini, Franco
AU - Tralli, Velio
AU - Serafino, Giovanni
AU - Petruzzelli, Vincenzo
TI - Reconfigurable on-chip wireless interconnections through optical phased arrays (Invited).
BT - ACM/IEEE International Workshop on System Level Interconnect Prediction, SLIP 2021, Munich, Germany, November 4, 2021
SP - 33
EP - 40
PY - 2021//
DO - 10.1109/SLIP52707.2021.00014
UR - https://doi.org/10.1109/SLIP52707.2021.00014
ER -
TY - JOUR
ID - DBLP:journals/tcad/TruppelTBAS20
AU - Truppel, Alexandre
AU - Tseng, Tsun-Ming
AU - Bertozzi, Davide
AU - Alves, José Carlos
AU - Schlichtmann, Ulf
TI - PSION+: Combining Logical Topology and Physical Layout Optimization for Wavelength-Routed ONoCs.
JO - IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
VL - 39
IS - 12
SP - 5197
EP - 5210
PY - 2020//
DO - 10.1109/TCAD.2020.2971536
UR - https://doi.org/10.1109/TCAD.2020.2971536
ER -
TY - CPAPER
ID - DBLP:conf/vlsi/VeronesiKB20
AU - Veronesi, Alessandro
AU - Krstic, Milos
AU - Bertozzi, Davide
TI - Cross-Layer Hardware/Software Assessment of the Open-Source NVDLA Configurable Deep Learning Accelerator.
BT - 28th IFIP/IEEE International Conference on Very Large Scale Integration, VLSI-SOC 2020, Salt Lake City, UT, USA, October 5-7, 2020
SP - 58
EP - 63
PY - 2020//
DO - 10.1109/VLSI-SOC46417.2020.9344109
UR - https://doi.org/10.1109/VLSI-SOC46417.2020.9344109
ER -
TY - CPAPER
ID - DBLP:conf/vlsi/VeronesiBK20
AU - Veronesi, Alessandro
AU - Bertozzi, Davide
AU - Krstic, Milos
TI - Assessing the Configuration Space of the Open Source NVDLA Deep Learning Accelerator on a Mainstream MPSoC Platform.
BT - VLSI-SoC: Design Trends - 28th IFIP WG 10.5/IEEE International Conference on Very Large Scale Integration, VLSI-SoC 2020, Salt Lake City, UT, USA, October 6-9, 2020, Revised and Extended Selected Papers
SP - 87
EP - 112
PY - 2020//
DO - 10.1007/978-3-030-81641-4_5
UR - https://doi.org/10.1007/978-3-030-81641-4_5
ER -
TY - CPAPER
ID - DBLP:conf/dcis/TurkiB19
AU - Turki, Mariem
AU - Bertozzi, Davide
TI - An Interconnect-Centric Approach to the Flexible Partitioning and Isolation of Many-Core Accelerators for Fog Computing.
BT - XXXIV Conference on Design of Circuits and Integrated Systems, DCIS 2019, Bilbao, Spain, November 20-22, 2019
SP - 1
EP - 6
PY - 2019//
DO - 10.1109/DCIS201949030.2019.8959943
UR - https://doi.org/10.1109/DCIS201949030.2019.8959943
ER -
TY - CPAPER
ID - DBLP:conf/ispd/TruppelTBAS19
AU - Truppel, Alexandre
AU - Tseng, Tsun-Ming
AU - Bertozzi, Davide
AU - Alves, José Carlos
AU - Schlichtmann, Ulf
TI - PSION: Combining Logical Topology and Physical Layout Optimization for Wavelength-Routed ONoCs.
BT - Proceedings of the 2019 International Symposium on Physical Design, ISPD 2019, San Francisco, CA, USA, April 14-17, 2019
SP - 49
EP - 56
PY - 2019//
DO - 10.1145/3299902.3309747
UR - https://doi.org/10.1145/3299902.3309747
ER -
TY - CPAPER
ID - DBLP:conf/mcsoc/AlonsoFTB19
AU - Alonso, Miguel Gorgues
AU - Flich, José
AU - Turki, Meriem
AU - Bertozzi, Davide
TI - A Low-Latency and Flexible TDM NoC for Strong Isolation in Security-Critical Systems.
BT - 13th IEEE International Symposium on Embedded Multicore/Many-core Systems-on-Chip, MCSoC 2019, Singapore, Singapore, October 1-4, 2019
SP - 149
EP - 156
PY - 2019//
DO - 10.1109/MCSOC.2019.00029
UR - https://doi.org/10.1109/MCSoC.2019.00029
ER -
TY - JOUR
ID - DBLP:journals/endm/NonatoBGP18
AU - Nonato, Maddalena
AU - Bertozzi, Davide
AU - Gavanelli, Marco
AU - Peano, Andrea
TI - A network model for routing-fault-free wavelength selection in WRONoCs design.
JO - Electron. Notes Discret. Math.
VL - 64
SP - 285
EP - 294
PY - 2018//
DO - 10.1016/J.ENDM.2018.02.003
UR - https://doi.org/10.1016/j.endm.2018.02.003
ER -
TY - CPAPER
ID - DBLP:conf/date/DalpassoBF18
AU - Dalpasso, Marcello
AU - Bertozzi, Davide
AU - Favalli, Michele
TI - A Boolean model for delay fault testing of emerging digital technologies based on ambipolar devices.
BT - 2018 Design, Automation & Test in Europe Conference & Exhibition, DATE 2018, Dresden, Germany, March 19-23, 2018
SP - 297
EP - 300
PY - 2018//
DO - 10.23919/DATE.2018.8342024
UR - https://doi.org/10.23919/DATE.2018.8342024
ER -
TY - CPAPER
ID - DBLP:conf/dcis/TalaSKB18
AU - Tala, Mahdi
AU - Schrape, Oliver
AU - Krstic, Milos
AU - Bertozzi, Davide
TI - Exploring the Performance-Energy Optimization Space of a Bridge Between 3D-Stacked Electronic and Optical Networks-on-Chip.
BT - Conference on Design of Circuits and Integrated Systems, DCIS 2018, Lyon, France, November 14-16, 2018
SP - 1
EP - 6
PY - 2018//
DO - 10.1109/DCIS.2018.8681461
UR - https://doi.org/10.1109/DCIS.2018.8681461
ER -
TY - CPAPER
ID - DBLP:conf/glvlsi/TalaSKB18
AU - Tala, Mahdi
AU - Schrape, Oliver
AU - Krstic, Milos
AU - Bertozzi, Davide
TI - Interfacing 3D-stacked Electronic and Optical NoCs with Mixed CMOS-ECL Bridges: a Realistic Preliminary Assessment.
BT - Proceedings of the 2018 on Great Lakes Symposium on VLSI, GLSVLSI 2018, Chicago, IL, USA, May 23-25, 2018
SP - 81
EP - 86
PY - 2018//
DO - 10.1145/3194554.3194593
UR - https://doi.org/10.1145/3194554.3194593
ER -
TY - CPAPER
ID - DBLP:conf/glvlsi/BertozziGN18
AU - Bertozzi, Davide
AU - Gavanelli, Marco
AU - Nonato, Maddalena
TI - Wavelength-Routed Optical Networks-on-Chip: Design Methods and Tools to Bridge the Gap Between Logic Topologies and Physical Ones in 3D Architectures.
BT - Proceedings of the 2018 on Great Lakes Symposium on VLSI, GLSVLSI 2018, Chicago, IL, USA, May 23-25, 2018
SP - 311
EP - 316
PY - 2018//
DO - 10.1145/3194554.3194607
UR - https://doi.org/10.1145/3194554.3194607
ER -
TY - CPAPER
ID - DBLP:conf/iccad/LiTBTS18
AU - Li, Mengchu
AU - Tseng, Tsun-Ming
AU - Bertozzi, Davide
AU - Tala, Mahdi
AU - Schlichtmann, Ulf
TI - CustomTopo: a topology generation method for application-specific wavelength-routed optical NoCs.
BT - Proceedings of the International Conference on Computer-Aided Design, ICCAD 2018, San Diego, CA, USA, November 05-08, 2018
SP - 100
PY - 2018//
DO - 10.1145/3240765.3240789
UR - https://doi.org/10.1145/3240765.3240789
UR - https://ieeexplore.ieee.org/document/8587714/
ER -
TY - CPAPER
ID - DBLP:conf/ngcas/ZambelliCOB18
AU - Zambelli, Cristian
AU - Castellari, Marco
AU - Olivo, Piero
AU - Bertozzi, Davide
TI - Correlating Power Efficiency and Lifetime to Programming Strategies in RRAM-Based FPGAs.
BT - 2018 New Generation of CAS, NGCAS 2018, Valletta, Malta, November 20-23, 2018
SP - 21
EP - 24
PY - 2018//
DO - 10.1109/NGCAS.2018.8572050
UR - https://doi.org/10.1109/NGCAS.2018.8572050
ER -
TY - CPAPER
ID - DBLP:conf/vlsi/TalaB18
AU - Tala, Mahdi
AU - Bertozzi, Davide
TI - Understanding the Design Space of Wavelength-Routed Optical NoC Topologies for Power-Performance Optimization.
BT - IFIP/IEEE International Conference on Very Large Scale Integration, VLSI-SoC 2018, Verona, Italy, October 8-10, 2018
SP - 255
EP - 260
PY - 2018//
DO - 10.1109/VLSI-SOC.2018.8644998
UR - https://doi.org/10.1109/VLSI-SoC.2018.8644998
ER -
TY - CPAPER
ID - DBLP:conf/vts/PasrichaBL18
AU - Pasricha, Sudeep
AU - Bertozzi, Davide
AU - Li, Hui
TI - Special session on overcoming reliability and energy-efficiency challenges with silicon photonics for future manycore computing.
BT - 36th IEEE VLSI Test Symposium, VTS 2018, San Francisco, CA, USA, April 22-25, 2018
SP - 1
PY - 2018//
DO - 10.1109/VTS.2018.8368643
UR - https://doi.org/10.1109/VTS.2018.8368643
UR - https://doi.ieeecomputersociety.org/10.1109/VTS.2018.8368643
ER -
TY - JOUR
ID - DBLP:journals/tplp/GavanelliNPB17
AU - Gavanelli, Marco
AU - Nonato, Maddalena
AU - Peano, Andrea
AU - Bertozzi, Davide
TI - Logic programming approaches for routing fault-free and maximally parallel wavelength-routed optical networks-on-chip (Application paper).
JO - Theory Pract. Log. Program.
VL - 17
IS - 5-6
SP - 800
EP - 818
PY - 2017//
DO - 10.1017/S1471068417000424
UR - https://doi.org/10.1017/S1471068417000424
ER -
TY - JOUR
ID - DBLP:journals/tvlsi/Ortin-ObonTRYB17
AU - Ortín-Obón, Marta
AU - Tala, Mahdi
AU - Ramini, Luca
AU - Yúfera, Víctor Viñals
AU - Bertozzi, Davide
TI - Contrasting Laser Power Requirements of Wavelength-Routed Optical NoC Topologies Subject to the Floorplanning, Placement, and Routing Constraints of a 3-D-Stacked System.
JO - IEEE Trans. Very Large Scale Integr. Syst.
VL - 25
IS - 7
SP - 2081
EP - 2094
PY - 2017//
DO - 10.1109/TVLSI.2017.2677779
UR - https://doi.org/10.1109/TVLSI.2017.2677779
UR - http://doi.ieeecomputersociety.org/10.1109/TVLSI.2017.2677779
UR - https://www.wikidata.org/entity/Q61678004
ER -
TY - CPAPER
ID - DBLP:conf/aspdac/Ortin-ObonRVB17
AU - Ortín-Obón, Marta
AU - Ramini, Luca
AU - Yúfera, Víctor Viñals
AU - Bertozzi, Davide
TI - A tool for synthesizing power-efficient and custom-tailored wavelength-routed optical rings.
BT - 22nd Asia and South Pacific Design Automation Conference, ASP-DAC 2017, Chiba, Japan, January 16-19, 2017
SP - 300
EP - 305
PY - 2017//
DO - 10.1109/ASPDAC.2017.7858339
UR - https://doi.org/10.1109/ASPDAC.2017.7858339
UR - https://www.wikidata.org/entity/Q61678002
ER -
TY - CPAPER
ID - DBLP:conf/async/MiorandiBNB17
AU - Miorandi, Gabriele
AU - Balboni, Marco
AU - Nowick, Steven M.
AU - Bertozzi, Davide
TI - Accurate Assessment of Bundled-Data Asynchronous NoCs Enabled by a Predictable and Efficient Hierarchical Synthesis Flow.
BT - 23rd IEEE International Symposium on Asynchronous Circuits and Systems, ASYNC 2017, San Diego, CA, USA, May 21-24, 2017
SP - 10
EP - 17
PY - 2017//
DO - 10.1109/ASYNC.2017.22
UR - https://doi.org/10.1109/ASYNC.2017.22
UR - https://doi.ieeecomputersociety.org/10.1109/ASYNC.2017.22
ER -
TY - CPAPER
ID - DBLP:conf/date/JiangBMNBS17
AU - Jiang, Weiwei
AU - Bertozzi, Davide
AU - Miorandi, Gabriele
AU - Nowick, Steven M.
AU - Burleson, Wayne P.
AU - Sadowski, Greg
TI - An asynchronous NoC router in a 14nm FinFET library: Comparison to an industrial synchronous counterpart.
BT - Design, Automation & Test in Europe Conference & Exhibition, DATE 2017, Lausanne, Switzerland, March 27-31, 2017
SP - 732
EP - 733
PY - 2017//
DO - 10.23919/DATE.2017.7927084
UR - https://doi.org/10.23919/DATE.2017.7927084
UR - http://dl.acm.org/citation.cfm?id=3130555
ER -
TY - CPAPER
ID - DBLP:conf/hipeac/BalboniB17
AU - Balboni, Marco
AU - Bertozzi, Davide
TI - Transparent lifetime built-in self-testing of networks-on-chip through the selective non-concurrent testing of their communication channels.
BT - Proceedings of the 2nd International Workshop on Advanced Interconnect Solutions and Technologies for Emerging Computing Systems, AISTECS@HiPEAC 2017, Stockholm, Sweden, January 25, 2017
SP - 12
EP - 17
PY - 2017//
DO - 10.1145/3073763.3073765
UR - https://doi.org/10.1145/3073763.3073765
ER -
TY - CPAPER
ID - DBLP:conf/newcas/BalboniB17
AU - Balboni, Marco
AU - Bertozzi, Davide
TI - Concurrent network-on-chip lifetime testing through selective disconnection of its communication channels.
BT - 15th IEEE International New Circuits and Systems Conference, NEWCAS 2017, Strasbourg, France, June 25-28, 2017
SP - 69
EP - 72
PY - 2017//
DO - 10.1109/NEWCAS.2017.8010107
UR - https://doi.org/10.1109/NEWCAS.2017.8010107
ER -
TY - CPAPER
ID - DBLP:conf/ngcas/BertozziMTN17
AU - Bertozzi, Davide
AU - Miorandi, Gabriele
AU - Tala, Mahdi
AU - Nowick, Steven M.
TI - Cost-Effective and Flexible Asynchronous Interconnect Technology for GALS Networks-on-Chip.
BT - New Generation of CAS, NGCAS 2017, Genova, Italy, September 6-9, 2017
SP - 77
EP - 80
PY - 2017//
DO - 10.1109/NGCAS.2017.49
UR - https://doi.org/10.1109/NGCAS.2017.49
ER -
TY - CPAPER
ID - DBLP:conf/socc/BertozziR17
AU - Bertozzi, Davide
AU - Rumley, Sébastien
TI - Propelling breakthrough embedded microprocessors by means of integrated photonics.
BT - 30th IEEE International System-on-Chip Conference, SOCC 2017, Munich, Germany, September 5-8, 2017
SP - 1
EP - 3
PY - 2017//
DO - 10.1109/SOCC.2017.8225981
UR - https://doi.org/10.1109/SOCC.2017.8225981
ER -
TY - Informal or Other Publication
ID - DBLP:journals/corr/GavanelliNPB17
AU - Gavanelli, Marco
AU - Nonato, Maddalena
AU - Peano, Andrea
AU - Bertozzi, Davide
TI - Logic Programming approaches for routing fault-free and maximally-parallel Wavelength Routed Optical Networks on Chip (Application paper).
JO - CoRR
VL - abs/1707.05858
PY - 2017//
UR - http://arxiv.org/abs/1707.05858
ER -
TY - JOUR
ID - DBLP:journals/jetc/BeuningenRBS16
AU - Beuningen, Anja von
AU - Ramini, Luca
AU - Bertozzi, Davide
AU - Schlichtmann, Ulf
TI - PROTON+: A Placement and Routing Tool for 3D Optical Networks-on-Chip with a Single Optical Layer.
JO - ACM J. Emerg. Technol. Comput. Syst.
VL - 12
IS - 4
SP - 44:1
EP - 44:28
PY - 2016//
DO - 10.1145/2830716
UR - https://doi.org/10.1145/2830716
ER -
TY - CPAPER
ID - DBLP:conf/hipeac/MiorandiTBRB16
AU - Miorandi, Gabriele
AU - Tala, Mahdi
AU - Balboni, Marco
AU - Ramini, Luca
AU - Bertozzi, Davide
TI - Evolutionary vs. Revolutionary Interconnect Technologies for Future Low-Power Multi-Core Systems.
BT - Proceedings of the 1st International Workshop on Advanced Interconnect Solutions and Technologies for Emerging Computing Systems, AISTECS@HiPEAC 2016, Prague, Czech Republic, January 18, 2016
SP - 3:1
EP - 3:6
PY - 2016//
DO - 10.1145/2857058.2857063
UR - https://doi.org/10.1145/2857058.2857063
ER -
TY - CPAPER
ID - DBLP:conf/iccad/PeanoRGNB16
AU - Peano, Andrea
AU - Ramini, Luca
AU - Gavanelli, Marco
AU - Nonato, Maddalena
AU - Bertozzi, Davide
TI - Design technology for fault-free and maximally-parallel wavelength-routed optical networks-on-chip.
BT - Proceedings of the 35th International Conference on Computer-Aided Design, ICCAD 2016, Austin, TX, USA, November 7-10, 2016
SP - 3
PY - 2016//
DO - 10.1145/2966986.2967023
UR - https://doi.org/10.1145/2966986.2967023
ER -
TY - CPAPER
ID - DBLP:conf/nocs/MiorandiCFB16
AU - Miorandi, Gabriele
AU - Celin, Alberto
AU - Favalli, Michele
AU - Bertozzi, Davide
TI - A built-in self-testing framework for asynchronous bundled-data NoC switches resilient to delay variations.
BT - Tenth IEEE/ACM International Symposium on Networks-on-Chip, NOCS 2016, Nara, Japan, August 31 - September 2, 2016
SP - 1
EP - 8
PY - 2016//
DO - 10.1109/NOCS.2016.7579332
UR - https://doi.org/10.1109/NOCS.2016.7579332
ER -
TY - CPAPER
ID - DBLP:conf/nocs/TalaCBB16
AU - Tala, Mahdi
AU - Castellari, Marco
AU - Balboni, Marco
AU - Bertozzi, Davide
TI - Populating and exploring the design space of wavelength-routed optical network-on-chip topologies by leveraging the add-drop filtering primitive.
BT - Tenth IEEE/ACM International Symposium on Networks-on-Chip, NOCS 2016, Nara, Japan, August 31 - September 2, 2016
SP - 1
EP - 8
PY - 2016//
DO - 10.1109/NOCS.2016.7579331
UR - https://doi.org/10.1109/NOCS.2016.7579331
ER -
TY - JOUR
ID - DBLP:journals/dafes/BertozziDFS15
AU - Bertozzi, Davide
AU - Dimitrakopoulos, Giorgos
AU - Flich, José
AU - Sonntag, Sören
TI - The fast evolving landscape of on-chip communication - Selected future challenges and research avenues.
JO - Des. Autom. Embed. Syst.
VL - 19
IS - 1-2
SP - 59
EP - 76
PY - 2015//
DO - 10.1007/S10617-014-9137-6
UR - https://doi.org/10.1007/s10617-014-9137-6
ER -
TY - JOUR
ID - DBLP:journals/tcad/ZuoloZMICPBO15
AU - Zuolo, Lorenzo
AU - Zambelli, Cristian
AU - Micheloni, Rino
AU - Indaco, Marco
AU - Carlo, Stefano Di
AU - Prinetto, Paolo
AU - Bertozzi, Davide
AU - Olivo, Piero
TI - SSDExplorer: A Virtual Platform for Performance/Reliability-Oriented Fine-Grained Design Space Exploration of Solid State Drives.
JO - IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
VL - 34
IS - 10
SP - 1627
EP - 1638
PY - 2015//
DO - 10.1109/TCAD.2015.2422834
UR - https://doi.org/10.1109/TCAD.2015.2422834
ER -
TY - JOUR
ID - DBLP:journals/tecs/BertozziCGIOPZ15
AU - Bertozzi, Davide
AU - Carlo, Stefano Di
AU - Galfano, Salvatore
AU - Indaco, Marco
AU - Olivo, Piero
AU - Prinetto, Paolo
AU - Zambelli, Cristian
TI - Performance and Reliability Analysis of Cross-Layer Optimizations of NAND Flash Controllers.
JO - ACM Trans. Embed. Comput. Syst.
VL - 14
IS - 1
SP - 7:1
EP - 7:24
PY - 2015//
DO - 10.1145/2629562
UR - https://doi.org/10.1145/2629562
ER -
TY - CPAPER
ID - DBLP:conf/arc/CastilloMBC15
AU - Castillo, Ernesto Villegas
AU - Miorandi, Gabriele
AU - Bertozzi, Davide
AU - Wang, Jiang Chau
TI - DyAFNoC: Dynamically Reconfigurable NoC Characterization Using a Simple Adaptive Deadlock-Free Routing Algorithm with a Low Implementation Cost.
BT - Applied Reconfigurable Computing - 11th International Symposium, ARC 2015, Bochum, Germany, April 13-17, 2015, Proceedings
SP - 419
EP - 426
PY - 2015//
DO - 10.1007/978-3-319-16214-0_38
UR - https://doi.org/10.1007/978-3-319-16214-0_38
ER -
TY - CPAPER
ID - DBLP:conf/async/MiorandiBN15
AU - Miorandi, Gabriele
AU - Bertozzi, Davide
AU - Nowick, Steven M.
TI - Increasing Impartiality and Robustness in High-Performance N-Way Asynchronous Arbiters.
BT - 21st IEEE International Symposium on Asynchronous Circuits and Systems, ASYNC 2015, Mountain View, CA, USA, May 4-6, 2015
SP - 108
EP - 115
PY - 2015//
DO - 10.1109/ASYNC.2015.24
UR - https://doi.org/10.1109/ASYNC.2015.24
UR - https://doi.ieeecomputersociety.org/10.1109/ASYNC.2015.24
ER -
TY - CPAPER
ID - DBLP:conf/date/BalboniFB15
AU - Balboni, Marco
AU - Flich, José
AU - Bertozzi, Davide
TI - Synergistic use of multiple on-chip networks for ultra-low latency and scalable distributed routing reconfiguration.
BT - Proceedings of the 2015 Design, Automation & Test in Europe Conference & Exhibition, DATE 2015, Grenoble, France, March 9-13, 2015
SP - 806
EP - 811
PY - 2015//
UR - http://dl.acm.org/citation.cfm?id=2755936
UR - https://ieeexplore.ieee.org/document/7092496/
ER -
TY - CPAPER
ID - DBLP:conf/hipeac/RaminiTB15
AU - Ramini, Luca
AU - Tala, Mahdi
AU - Bertozzi, Davide
TI - Contrasting Power Efficiency of Contention Resolution vs. Avoidance Strategies in Optical Ring Interconnects for Photonically-Integrated Embedded Systems.
BT - Ninth International Workshop on Interconnection Network Architectures: On-Chip, Multi-Chip, INA-OCMC@HiPEAC 2015, Amsterdam, Netherlands, January 19, 2015
SP - 5
EP - 8
PY - 2015//
DO - 10.1109/INA-OCMC.2015.10
UR - https://doi.org/10.1109/INA-OCMC.2015.10
UR - https://doi.ieeecomputersociety.org/10.1109/INA-OCMC.2015.10
ER -
TY - CPAPER
ID - DBLP:conf/hipeac/OrtinRBZNVB15
AU - Ortín, Marta
AU - Ramini, Luca
AU - Balboni, Marco
AU - Zuolo, Lorenzo
AU - Nonato, Maddalena
AU - Viñals, Víctor
AU - Bertozzi, Davide
TI - Partitioning Strategies of Wavelength-Routed Optical Networks-on-Chip for Laser Power Minimization.
BT - 2015 Workshop on Exploiting Silicon Photonics for Energy-Efficient High Performance Computing, SiPhotonics@HiPEAC 2015, Amsterdam, Netherlands, January 19, 2015
SP - 17
EP - 24
PY - 2015//
DO - 10.1109/SIPHOTONICS.2015.13
UR - https://doi.org/10.1109/SiPhotonics.2015.13
UR - https://doi.ieeecomputersociety.org/10.1109/SiPhotonics.2015.13
UR - https://www.wikidata.org/entity/Q61678012
ER -
TY - CPAPER
ID - DBLP:conf/ieeehpcs/BalboniB15
AU - Balboni, Marco
AU - Bertozzi, Davide
TI - NoC-centric partitioning and reconfiguration technologies for the efficient sharing of multi-core programmable accelerators.
BT - 2015 International Conference on High Performance Computing & Simulation, HPCS 2015, Amsterdam, Netherlands, July 20-24, 2015
SP - 643
EP - 645
PY - 2015//
DO - 10.1109/HPCSIM.2015.7237107
UR - https://doi.org/10.1109/HPCSim.2015.7237107
ER -
TY - CPAPER
ID - DBLP:conf/lascas/CastilloCMB15
AU - Castillo, Ernesto Villegas
AU - Wang, Jiang Chau
AU - Miorandi, Gabriele
AU - Bertozzi, Davide
TI - Dynamically Reconfigurable NoC using a deadlock-free flexible routing algorithm with a low hardware implementation cost.
BT - IEEE 6th Latin American Symposium on Circuits & Systems, LASCAS 2015, Montevideo, Uruguay, February 24-27, 2015
SP - 1
EP - 4
PY - 2015//
DO - 10.1109/LASCAS.2015.7250477
UR - https://doi.org/10.1109/LASCAS.2015.7250477
ER -
TY - JOUR
ID - DBLP:journals/concurrency/Ortin-ObonRVB14
AU - Ortín-Obón, Marta
AU - Ramini, Luca
AU - Viñals, Víctor
AU - Bertozzi, Davide
TI - Capturing the sensitivity of optical network quality metrics to its network interface parameters.
JO - Concurr. Comput. Pract. Exp.
VL - 26
IS - 15
SP - 2504
EP - 2517
PY - 2014//
DO - 10.1002/CPE.3330
UR - https://doi.org/10.1002/cpe.3330
UR - https://www.wikidata.org/entity/Q61678015
ER -
TY - JOUR
ID - DBLP:journals/dafes/BertozziDS14
AU - Bertozzi, Davide
AU - Dimitrakopoulos, Giorgos
AU - Sonntag, Sören
TI - Editorial.
JO - Des. Autom. Embed. Syst.
VL - 18
IS - 3-4
SP - 119
EP - 120
PY - 2014//
DO - 10.1007/S10617-014-9136-7
UR - https://doi.org/10.1007/s10617-014-9136-7
ER -
TY - JOUR
ID - DBLP:journals/taco/CarloGIPBOZ14
AU - Carlo, Stefano Di
AU - Galfano, Salvatore
AU - Indaco, Marco
AU - Prinetto, Paolo
AU - Bertozzi, Davide
AU - Olivo, Piero
AU - Zambelli, Cristian
TI - FLARES: An Aging Aware Algorithm to Autonomously Adapt the Error Correction Capability in NAND Flash Memories.
JO - ACM Trans. Archit. Code Optim.
VL - 11
IS - 3
SP - 26:1
EP - 26:25
PY - 2014//
DO - 10.1145/2631919
UR - https://doi.org/10.1145/2631919
ER -
TY - CPAPER
ID - DBLP:conf/aspdac/GhiribaldiFASBB14
AU - Ghiribaldi, Alberto
AU - Fankem, Hervé Tatenguem
AU - Angiolini, Federico
AU - Stensgaard, Mikkel Bystrup
AU - Bjerregaard, Tobias
AU - Bertozzi, Davide
TI - A vertically integrated and interoperable multi-vendor synthesis flow for predictable noc design in nanoscale technologies.
BT - 19th Asia and South Pacific Design Automation Conference, ASP-DAC 2014, Singapore, January 20-23, 2014
SP - 337
EP - 342
PY - 2014//
DO - 10.1109/ASPDAC.2014.6742912
UR - https://doi.org/10.1109/ASPDAC.2014.6742912
ER -
TY - CPAPER
ID - DBLP:conf/csedu/MazzoniMCB14
AU - Mazzoni, Valentina
AU - Mortari, Luigina
AU - Corni, Federico
AU - Bertozzi, Davide
TI - Guided Participatory Research on Parallel Computer Architectures for K-12 Students Through a Narrative Approach.
BT - CSEDU 2014 - Proceedings of the 6th International Conference on Computer Supported Education, Volume 3, Barcelona, Spain, 1-3 April, 2014
SP - 111
EP - 117
PY - 2014//
DO - 10.5220/0004957601110117
UR - https://doi.org/10.5220/0004957601110117
ER -
TY - CPAPER
ID - DBLP:conf/date/RaminiGGBFB14
AU - Ramini, Luca
AU - Ghiribaldi, Alberto
AU - Grani, Paolo
AU - Bartolini, Sandro
AU - Fankem, Hervé Tatenguem
AU - Bertozzi, Davide
TI - Assessing the energy break-even point between an optical NoC architecture and an aggressive electronic baseline.
BT - Design, Automation & Test in Europe Conference & Exhibition, DATE 2014, Dresden, Germany, March 24-28, 2014
SP - 1
EP - 6
PY - 2014//
DO - 10.7873/DATE.2014.321
UR - https://doi.org/10.7873/DATE.2014.321
UR - http://dl.acm.org/citation.cfm?id=2617051
ER -
TY - CPAPER
ID - DBLP:conf/date/ZuoloZMGICPOB14
AU - Zuolo, Lorenzo
AU - Zambelli, Cristian
AU - Micheloni, Rino
AU - Galfano, Salvatore
AU - Indaco, Marco
AU - Carlo, Stefano Di
AU - Prinetto, Paolo
AU - Olivo, Piero
AU - Bertozzi, Davide
TI - SSDExplorer: A virtual platform for fine-grained design space exploration of Solid State Drives.
BT - Design, Automation & Test in Europe Conference & Exhibition, DATE 2014, Dresden, Germany, March 24-28, 2014
SP - 1
EP - 6
PY - 2014//
DO - 10.7873/DATE.2014.297
UR - https://doi.org/10.7873/DATE.2014.297
UR - http://dl.acm.org/citation.cfm?id=2617021
ER -
TY - CPAPER
ID - DBLP:conf/ewme/MazzoniB14
AU - Mazzoni, Valentina
AU - Bertozzi, Davide
TI - Interdisciplinary design of a research experience on microelectronic systems for K-12 students.
BT - 10th European Workshop on Microelectronics Education (EWME), Tallinn, Estonia, May 14-16, 2014
SP - 64
EP - 69
PY - 2014//
DO - 10.1109/EWME.2014.6877397
UR - https://doi.org/10.1109/EWME.2014.6877397
ER -
TY - CPAPER
ID - DBLP:conf/glvlsi/Ortin-ObonRFVB14
AU - Ortín-Obón, Marta
AU - Ramini, Luca
AU - Fankem, Hervé Tatenguem
AU - Viñals, Víctor
AU - Bertozzi, Davide
TI - A complete electronic network interface architecture for global contention-free communication over emerging optical networks-on-chip.
BT - Great Lakes Symposium on VLSI 2014, GLSVLSI '14, Houston, TX, USA - May 21 - 23, 2014
SP - 267
EP - 272
PY - 2014//
DO - 10.1145/2591513.2591536
UR - https://doi.org/10.1145/2591513.2591536
ER -
TY - CPAPER
ID - DBLP:conf/hipeac/StranoGFB14
AU - Strano, Alessandro
AU - Ghiribaldi, Alberto
AU - Fankem, Hervé Tatenguem
AU - Bertozzi, Davide
TI - A feature-rich NoC switch with cross-feature optimizations for the next generation of reliable and reconfigurable embedded systems.
BT - Proceedings of the 8th International Workshop on Interconnection Network Architecture - On-Chip, Multi-Chip, INA-OCMC 2014, Vienna, Austria, January 22, 2014
SP - 2:1
EP - 2:4
PY - 2014//
DO - 10.1145/2556857.2556859
UR - https://doi.org/10.1145/2556857.2556859
ER -
TY - CPAPER
ID - DBLP:conf/nocs/BalboniOCFGRVMB14
AU - Balboni, Marco
AU - Ortín-Obón, Marta
AU - Capotondi, Alessandro
AU - Fankem, Hervé Tatenguem
AU - Ghiribaldi, Alberto
AU - Ramini, Luca
AU - Viñals, Víctor
AU - Marongiu, Andrea
AU - Bertozzi, Davide
TI - Augmenting manycore programmable accelerators with photonic interconnect technology for the high-end embedded computing domain.
BT - Eighth IEEE/ACM International Symposium on Networks-on-Chip, NoCS 2014, Ferrara, Italy, September 17-19, 2014
SP - 72
EP - 79
PY - 2014//
DO - 10.1109/NOCS.2014.7008764
UR - https://doi.org/10.1109/NOCS.2014.7008764
ER -
TY - CPAPER
ID - DBLP:conf/vlsi/MiorandiGNB14
AU - Miorandi, Gabriele
AU - Ghiribaldi, Alberto
AU - Nowick, Steven M.
AU - Bertozzi, Davide
TI - Crossbar replication vs. sharing for virtual channel flow control in asynchronous NoCs: A comparative study.
BT - 22nd International Conference on Very Large Scale Integration, VLSI-SoC, Playa del Carmen, Mexico, October 6-8, 2014
SP - 1
EP - 6
PY - 2014//
DO - 10.1109/VLSI-SOC.2014.7004164
UR - https://doi.org/10.1109/VLSI-SoC.2014.7004164
ER -
TY - CONF
ID - DBLP:conf/nocs/2014
ED - Bertozzi, Davide
ED - Benini, Luca
ED - Yalamanchili, Sudhakar
ED - Henkel, Jörg
TI - Eighth IEEE/ACM International Symposium on Networks-on-Chip, NoCS 2014, Ferrara, Italy, September 17-19, 2014
PY - 2014//
PB - IEEE
UR - https://ieeexplore.ieee.org/xpl/conhome/7000615/proceeding
SN - ISBN 978-1-4799-5347-9
ER -
TY - JOUR
ID - DBLP:journals/iet-cdt/StranoCTB13
AU - Strano, Alessandro
AU - Caselli, Nicola
AU - Terenzi, Simone
AU - Bertozzi, Davide
TI - Optimising pseudo-random built-in self-testing of fully synchronous as well as multisynchronous networks-on-chip.
JO - IET Comput. Digit. Tech.
VL - 7
IS - 2
PY - 2013//
DO - 10.1049/IET-CDT.2012.0064
UR - https://doi.org/10.1049/iet-cdt.2012.0064
ER -
TY - JOUR
ID - DBLP:journals/tecs/GhiribaldiLTSFSAFB13
AU - Ghiribaldi, Alberto
AU - Ludovici, Daniele
AU - Triviño, Francisco
AU - Strano, Alessandro
AU - Flich, José
AU - Sánchez, José L.
AU - Alfaro, Francisco J.
AU - Favalli, Michele
AU - Bertozzi, Davide
TI - A complete self-testing and self-configuring NoC infrastructure for cost-effective MPSoCs.
JO - ACM Trans. Embed. Comput. Syst.
VL - 12
IS - 4
SP - 106:1
EP - 106:29
PY - 2013//
DO - 10.1145/2485984.2485994
UR - https://doi.org/10.1145/2485984.2485994
ER -
TY - JOUR
ID - DBLP:journals/tecs/Sem-JacobsenRSSB13
AU - Sem-Jacobsen, Frank Olaf
AU - Rodrigo, Samuel
AU - Skeie, Tor
AU - Strano, Alessandro
AU - Bertozzi, Davide
TI - An efficient, low-cost routing framework for convex mesh partitions to support virtualization.
JO - ACM Trans. Embed. Comput. Syst.
VL - 12
IS - 4
SP - 107:1
EP - 107:24
PY - 2013//
DO - 10.1145/2485984.2485995
UR - https://doi.org/10.1145/2485984.2485995
ER -
TY - JOUR
ID - DBLP:journals/tecs/Sem-JacobsenRSSBV13
AU - Sem-Jacobsen, Frank Olaf
AU - Rodrigo, Samuel
AU - Strano, Alessandro
AU - Skeie, Tor
AU - Bertozzi, Davide
AU - Villamón, Francisco Gilabert
TI - Enabling power efficiency through dynamic rerouting on-chip.
JO - ACM Trans. Embed. Comput. Syst.
VL - 12
IS - 4
SP - 111:1
EP - 111:23
PY - 2013//
DO - 10.1145/2485984.2485999
UR - https://doi.org/10.1145/2485984.2485999
ER -
TY - CPAPER
ID - DBLP:conf/date/GhiribaldiBN13
AU - Ghiribaldi, Alberto
AU - Bertozzi, Davide
AU - Nowick, Steven M.
TI - A transition-signaling bundled data NoC switch architecture for cost-effective GALS multicore systems.
BT - Design, Automation and Test in Europe, DATE 13, Grenoble, France, March 18-22, 2013
SP - 332
EP - 337
PY - 2013//
DO - 10.7873/DATE.2013.079
UR - https://doi.org/10.7873/DATE.2013.079
UR - http://dl.acm.org/citation.cfm?id=2485370
ER -
TY - CPAPER
ID - DBLP:conf/date/RaminiGBB13
AU - Ramini, Luca
AU - Grani, Paolo
AU - Bartolini, Sandro
AU - Bertozzi, Davide
TI - Contrasting wavelength-routed optical NoC topologies for power-efficient 3D-stacked multicore processors using physical-layer analysis.
BT - Design, Automation and Test in Europe, DATE 13, Grenoble, France, March 18-22, 2013
SP - 1589
EP - 1594
PY - 2013//
DO - 10.7873/DATE.2013.323
UR - https://doi.org/10.7873/DATE.2013.323
UR - http://dl.acm.org/citation.cfm?id=2485666
ER -
TY - CPAPER
ID - DBLP:conf/europar/LysneHLB13
AU - Lysne, Olav
AU - Hoefler, Torsten
AU - López, Pedro
AU - Bertozzi, Davide
TI - Topic 13: High-Performance Networks and Communication - (Introduction).
BT - Euro-Par 2013 Parallel Processing - 19th International Conference, Aachen, Germany, August 26-30, 2013. Proceedings
SP - 684
PY - 2013//
DO - 10.1007/978-3-642-40047-6_68
UR - https://doi.org/10.1007/978-3-642-40047-6_68
ER -
TY - CPAPER
ID - DBLP:conf/hipeac/TrivinoBF13
AU - Triviño, Francisco
AU - Bertozzi, Davide
AU - Flich, José
TI - A fast algorithm for runtime reconfiguration to maximize the lifetime of nanoscale NoCs.
BT - Proceedings of the 2013 Interconnection Network Architecture: On-Chip, Multi-Chip, IMA-OCMC@HiPEAC 2013, Berlin, Germany, January 23, 2013
SP - 1
EP - 4
PY - 2013//
DO - 10.1145/2482759.2482760
UR - https://doi.org/10.1145/2482759.2482760
ER -
TY - CPAPER
ID - DBLP:conf/iccad/BoosRSB13
AU - Boos, Anja
AU - Ramini, Luca
AU - Schlichtmann, Ulf
AU - Bertozzi, Davide
TI - PROTON: an automatic place-and-route tool for optical networks-on-chip.
BT - The IEEE/ACM International Conference on Computer-Aided Design, ICCAD'13, San Jose, CA, USA, November 18-21, 2013
SP - 138
EP - 145
PY - 2013//
DO - 10.1109/ICCAD.2013.6691109
UR - https://doi.org/10.1109/ICCAD.2013.6691109
UR - http://dl.acm.org/citation.cfm?id=2561855
ER -
TY - CPAPER
ID - DBLP:conf/issoc/BalboniTFB13
AU - Balboni, Marco
AU - Triviño, Francisco
AU - Flich, José
AU - Bertozzi, Davide
TI - Optimizing the overhead for network-on-chip routing reconfiguration in parallel multi-core platforms.
BT - 2013 International Symposium on System on Chip, ISSoC 2013, Tampere, Finland, October 23-24, 2013
SP - 1
EP - 6
PY - 2013//
DO - 10.1109/ISSOC.2013.6675258
UR - https://doi.org/10.1109/ISSoC.2013.6675258
ER -
TY - CPAPER
ID - DBLP:conf/issoc/ZuoloMZOB13
AU - Zuolo, Lorenzo
AU - Miorandi, Gabriele
AU - Zambelli, Cristian
AU - Olivo, Piero
AU - Bertozzi, Davide
TI - System interconnect extensions for fully transparent demand paging in low-cost MMU-less embedded systems.
BT - 2013 International Symposium on System on Chip, ISSoC 2013, Tampere, Finland, October 23-24, 2013
SP - 1
EP - 6
PY - 2013//
DO - 10.1109/ISSOC.2013.6675257
UR - https://doi.org/10.1109/ISSoC.2013.6675257
ER -
TY - JOUR
ID - DBLP:journals/ijertcs/KrsticFGBKHSSB12
AU - Krstic, Milos
AU - Fan, Xin
AU - Grass, Eckhard
AU - Benini, Luca
AU - Kakoee, Mohammad Reza
AU - Heer, Christoph
AU - Sanders, Birgit
AU - Strano, Alessandro
AU - Bertozzi, Davide
TI - Evaluation of GALS Methods in Scaled CMOS Technology: Moonrake Chip Experience.
JO - Int. J. Embed. Real Time Commun. Syst.
VL - 3
IS - 4
SP - 1
EP - 18
PY - 2012//
DO - 10.4018/JERTCS.2012100101
UR - https://doi.org/10.4018/jertcs.2012100101
ER -
TY - CPAPER
ID - DBLP:conf/codes/TodorovGRBS12
AU - Todorov, Vladimir
AU - Ghiribaldi, Alberto
AU - Reinig, Helmut
AU - Bertozzi, Davide
AU - Schlichtmann, Ulf
TI - Non-intrusive trace & debug noc architecture with accurate timestamping for GALS SoCs.
BT - Proceedings of the 10th International Conference on Hardware/Software Codesign and System Synthesis, CODES+ISSS 2012, part of ESWeek '12 Eighth Embedded Systems Week, Tampere, Finland, October 7-12, 2012
SP - 181
EP - 186
PY - 2012//
DO - 10.1145/2380445.2380477
UR - https://doi.org/10.1145/2380445.2380477
ER -
TY - CPAPER
ID - DBLP:conf/date/AbellanPABBMB12
AU - Abellán, José L.
AU - Peinador, Juan Fernández
AU - Acacio, Manuel E.
AU - Bertozzi, Davide
AU - Bortolotti, Daniele
AU - Marongiu, Andrea
AU - Benini, Luca
TI - Design of a collective communication infrastructure for barrier synchronization in cluster-based nanoscale MPSoCs.
BT - 2012 Design, Automation & Test in Europe Conference & Exhibition, DATE 2012, Dresden, Germany, March 12-16, 2012
SP - 491
EP - 496
PY - 2012//
DO - 10.1109/DATE.2012.6176519
UR - https://doi.org/10.1109/DATE.2012.6176519
UR - https://doi.ieeecomputersociety.org/10.1109/DATE.2012.6176519
UR - http://dl.acm.org/citation.cfm?id=2492831
ER -
TY - CPAPER
ID - DBLP:conf/date/ZambelliIFCPOB12
AU - Zambelli, Cristian
AU - Indaco, Marco
AU - Fabiano, Michele
AU - Carlo, Stefano Di
AU - Prinetto, Paolo
AU - Olivo, Piero
AU - Bertozzi, Davide
TI - A cross-layer approach for new reliability-performance trade-offs in MLC NAND flash memories.
BT - 2012 Design, Automation & Test in Europe Conference & Exhibition, DATE 2012, Dresden, Germany, March 12-16, 2012
SP - 881
EP - 886
PY - 2012//
DO - 10.1109/DATE.2012.6176622
UR - https://doi.org/10.1109/DATE.2012.6176622
UR - https://doi.ieeecomputersociety.org/10.1109/DATE.2012.6176622
UR - http://dl.acm.org/citation.cfm?id=2492931
ER -
TY - CPAPER
ID - DBLP:conf/europar/RodrigoSTSB12
AU - Rodrigo, Samuel
AU - Sem-Jacobsen, Frank Olaf
AU - Tatenguem, Hervé
AU - Skeie, Tor
AU - Bertozzi, Davide
TI - Cost-Effective Contention Avoidance in a CMP with Shared Memory Controllers.
BT - Euro-Par 2012 Parallel Processing - 18th International Conference, Euro-Par 2012, Rhodes Island, Greece, August 27-31, 2012. Proceedings
SP - 741
EP - 752
PY - 2012//
DO - 10.1007/978-3-642-32820-6_73
UR - https://doi.org/10.1007/978-3-642-32820-6_73
ER -
TY - CPAPER
ID - DBLP:conf/green/GhiribaldiSFB12
AU - Ghiribaldi, Alberto
AU - Strano, Alessandro
AU - Favalli, Michele
AU - Bertozzi, Davide
TI - Power efficiency of switch architecture extensions for fault tolerant NoC design.
BT - 2012 International Green Computing Conference, IGCC 2012, San Jose, CA, USA, June 4-8, 2012
SP - 1
EP - 6
PY - 2012//
DO - 10.1109/IGCC.2012.6322281
UR - https://doi.org/10.1109/IGCC.2012.6322281
UR - https://doi.ieeecomputersociety.org/10.1109/IGCC.2012.6322281
ER -
TY - CPAPER
ID - DBLP:conf/hipeac/TerenziSB12
AU - Terenzi, Simone
AU - Strano, Alessandro
AU - Bertozzi, Davide
TI - Optimizing built-in pseudo-random self-testing for network-on-chip switches.
BT - Proceedings of the 2012 Interconnection Network Architecture - On-Chip, Multi-Chip Workshop, INA-OCMC@HiPEAC 2012, Paris, France, January 25, 2012
SP - 21
EP - 24
PY - 2012//
DO - 10.1145/2107763.2107769
UR - https://doi.org/10.1145/2107763.2107769
ER -
TY - CPAPER
ID - DBLP:conf/hipeac/StranoBAGSTFSB12
AU - Strano, Alessandro
AU - Bertozzi, Davide
AU - Angiolini, Federico
AU - Gregorio, Leonardo Di G.
AU - Sem-Jacobsen, Frank Olaf
AU - Todorov, Vladimir
AU - Flich, José
AU - Silla, José
AU - Bjerregaard, Tobias
TI - Quest for the ultimate network-on-chip: the NaNoC project.
BT - Proceedings of the 2012 Interconnection Network Architecture - On-Chip, Multi-Chip Workshop, INA-OCMC@HiPEAC 2012, Paris, France, January 25, 2012
SP - 43
EP - 46
PY - 2012//
DO - 10.1145/2107763.2107775
UR - https://doi.org/10.1145/2107763.2107775
ER -
TY - CPAPER
ID - DBLP:conf/iccd/BertozziB12
AU - Bertozzi, Davide
AU - Benini, Luca
TI - A retrospective look at xpipes: The exciting ride from a design experience to a design platform for nanoscale networks-on-chip.
BT - 30th International IEEE Conference on Computer Design, ICCD 2012, Montreal, QC, Canada, September 30 - Oct. 3, 2012
SP - 43
EP - 44
PY - 2012//
DO - 10.1109/ICCD.2012.6378614
UR - https://doi.org/10.1109/ICCD.2012.6378614
UR - https://doi.ieeecomputersociety.org/10.1109/ICCD.2012.6378614
ER -
TY - CPAPER
ID - DBLP:conf/iccd/DallOssoBGBB12
AU - Dall'Osso, Matteo
AU - Biccari, Gianluca
AU - Giovannini, Luca
AU - Bertozzi, Davide
AU - Benini, Luca
TI - Xpipes: A latency insensitive parameterized network-on-chip architecture for multi-processor SoCs.
BT - 30th International IEEE Conference on Computer Design, ICCD 2012, Montreal, QC, Canada, September 30 - Oct. 3, 2012
SP - 45
EP - 48
PY - 2012//
DO - 10.1109/ICCD.2012.6378615
UR - https://doi.org/10.1109/ICCD.2012.6378615
UR - https://doi.ieeecomputersociety.org/10.1109/ICCD.2012.6378615
ER -
TY - CPAPER
ID - DBLP:conf/issoc/TatenguemSGRB12
AU - Tatenguem, Hervé
AU - Strano, Alessandro
AU - Govind, Vineeth
AU - Raik, Jaan
AU - Bertozzi, Davide
TI - Ultra-low latency NoC testing via pseudo-random test pattern compaction.
BT - 2012 International Symposium on System on Chip, ISSoC 2012, Tampere, Finland, October 10-12, 2012
SP - 1
EP - 6
PY - 2012//
DO - 10.1109/ISSOC.2012.6376370
UR - https://doi.org/10.1109/ISSoC.2012.6376370
ER -
TY - CPAPER
ID - DBLP:conf/mcsoc/CaselliSLB12
AU - Caselli, Nicola
AU - Strano, Alessandro
AU - Ludovici, Daniele
AU - Bertozzi, Davide
TI - Cooperative Built-in Self-Testing and Self-Diagnosis of NoC Bisynchronous Channels.
BT - IEEE 6th International Symposium on Embedded Multicore/Manycore SoCs, MCSoC 2012, Fukushima, Japan, September 20-22, 2012
SP - 159
EP - 166
PY - 2012//
DO - 10.1109/MCSOC.2012.13
UR - https://doi.org/10.1109/MCSoC.2012.13
UR - https://doi.ieeecomputersociety.org/10.1109/MCSoC.2012.13
ER -
TY - CPAPER
ID - DBLP:conf/micro/RaminiB12
AU - Ramini, Luca
AU - Bertozzi, Davide
TI - Power efficiency of wavelength-routed optical NoC topologies for global connectivity of 3D multi-core processors.
BT - Fifth International Workshop on Network on Chip Architectures, NoCArc '12, Vancouver, BC, Canada, December 1, 2012
SP - 25
EP - 30
PY - 2012//
DO - 10.1145/2401716.2401723
UR - https://doi.org/10.1145/2401716.2401723
ER -
TY - CPAPER
ID - DBLP:conf/nocs/RaminiBC12
AU - Ramini, Luca
AU - Bertozzi, Davide
AU - Carloni, Luca P.
TI - Engineering a Bandwidth-Scalable Optical Layer for a 3D Multi-core Processor with Awareness of Layout Constraints.
BT - 2012 Sixth IEEE/ACM International Symposium on Networks-on-Chip (NoCS), Copenhagen, Denmark, 9-11 May, 2012
SP - 185
EP - 192
PY - 2012//
DO - 10.1109/NOCS.2012.29
UR - https://doi.org/10.1109/NOCS.2012.29
UR - https://doi.ieeecomputersociety.org/10.1109/NOCS.2012.29
ER -
TY - CPAPER
ID - DBLP:conf/samos/StranoBTSAF12
AU - Strano, Alessandro
AU - Bertozzi, Davide
AU - Triviño, Francisco
AU - Sánchez, José L.
AU - Alfaro, Francisco J.
AU - Flich, José
TI - OSR-Lite: Fast and deadlock-free NoC reconfiguration framework.
BT - 2012 International Conference on Embedded Computer Systems: Architectures, Modeling, and Simulation, SAMOS XII, Samos, Greece, July 16-19, 2012
SP - 86
EP - 95
PY - 2012//
DO - 10.1109/SAMOS.2012.6404161
UR - https://doi.org/10.1109/SAMOS.2012.6404161
ER -
TY - JOUR
ID - DBLP:journals/esl/ZambelliBCO11
AU - Zambelli, Cristian
AU - Bertozzi, Davide
AU - Chimenton, Andrea
AU - Olivo, Piero
TI - Nonvolatile Memory Partitioning Scheme for Technology-Based Performance-Reliability Tradeoff.
JO - IEEE Embed. Syst. Lett.
VL - 3
IS - 1
SP - 13
EP - 15
PY - 2011//
DO - 10.1109/LES.2010.2092411
UR - https://doi.org/10.1109/LES.2010.2092411
ER -
TY - JOUR
ID - DBLP:journals/iet-cdt/PaciBB11
AU - Paci, Giacomo
AU - Bertozzi, Davide
AU - Benini, Luca
TI - Variability compensation for full-swing against low-swing on-chip communication.
JO - IET Comput. Digit. Tech.
VL - 5
IS - 5
SP - 355
EP - 365
PY - 2011//
DO - 10.1049/IET-CDT.2009.0103
UR - https://doi.org/10.1049/iet-cdt.2009.0103
ER -
TY - JOUR
ID - DBLP:journals/ijertcs/StranoHSB11
AU - Strano, Alessandro
AU - Hernández, Carles
AU - Silla, Federico
AU - Bertozzi, Davide
TI - Self-Calibrating Source Synchronous Communication for Delay Variation Tolerant GALS Network-on-Chip Design.
JO - Int. J. Embed. Real Time Commun. Syst.
VL - 2
IS - 4
SP - 1
EP - 20
PY - 2011//
DO - 10.4018/JERTCS.2011100101
UR - https://doi.org/10.4018/jertcs.2011100101
ER -
TY - JOUR
ID - DBLP:journals/tcad/RodrigoFRMBCSD11
AU - Rodrigo, Samuel
AU - Flich, José
AU - Roca, Antoni
AU - Medardoni, Simone
AU - Bertozzi, Davide
AU - Villanueva, Jesús Camacho
AU - Silla, Federico
AU - Duato, José
TI - Cost-Efficient On-Chip Routing Implementations for CMP and MPSoC Systems.
JO - IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
VL - 30
IS - 4
SP - 534
EP - 547
PY - 2011//
DO - 10.1109/TCAD.2011.2119150
UR - https://doi.org/10.1109/TCAD.2011.2119150
ER -
TY - CPAPER
ID - DBLP:conf/asap/StranoBGY11
AU - Strano, Alessandro
AU - Bertozzi, Davide
AU - Grasset, Arnaud
AU - Yehia, Sami
TI - Exploiting structural redundancy of SIMD accelerators for their built-in self-testing/diagnosis and reconfiguration.
BT - 22nd IEEE International Conference on Application-specific Systems, Architectures and Processors, ASAP 2011, Santa Monica, CA, USA, Sept. 11-14, 2011
SP - 141
EP - 148
PY - 2011//
DO - 10.1109/ASAP.2011.6043262
UR - https://doi.org/10.1109/ASAP.2011.6043262
UR - https://doi.ieeecomputersociety.org/10.1109/ASAP.2011.6043262
ER -
TY - CPAPER
ID - DBLP:conf/date/StranoGLFGB11
AU - Strano, Alessandro
AU - Requena, Crispín Gómez
AU - Ludovici, Daniele
AU - Favalli, Michele
AU - Gómez, María Engracia
AU - Bertozzi, Davide
TI - Exploiting Network-on-Chip structural redundancy for a cooperative and scalable built-in self-test architecture.
BT - Design, Automation and Test in Europe, DATE 2011, Grenoble, France, March 14-18, 2011
SP - 661
EP - 666
PY - 2011//
DO - 10.1109/DATE.2011.5763109
UR - https://doi.org/10.1109/DATE.2011.5763109
UR - https://doi.ieeecomputersociety.org/10.1109/DATE.2011.5763109
ER -
TY - CPAPER
ID - DBLP:conf/hipeac/LudoviciSGB11
AU - Ludovici, Daniele
AU - Strano, Alessandro
AU - Gaydadjiev, Georgi Nedeltchev
AU - Bertozzi, Davide
TI - Mesochronous NoC technology for power-efficient GALS MPSoCs.
BT - Proceedings of the Fifth International Workshop on Interconnection Network Architecture - On-Chip, Multi-Chip, INA-OCMC '11, Heraklion, Greece, January 23, 2011
SP - 27
EP - 30
PY - 2011//
DO - 10.1145/1930037.1930045
UR - https://doi.org/10.1145/1930037.1930045
ER -
TY - CPAPER
ID - DBLP:conf/hipeac/PariniRBB11
AU - Parini, Alberto
AU - Ramini, Luca
AU - Bellanca, Gaetano
AU - Bertozzi, Davide
TI - Abstract modelling of switching elements for optical networks-on-chip with technology platform awareness.
BT - Proceedings of the Fifth International Workshop on Interconnection Network Architecture - On-Chip, Multi-Chip, INA-OCMC '11, Heraklion, Greece, January 23, 2011
SP - 31
EP - 34
PY - 2011//
DO - 10.1145/1930037.1930046
UR - https://doi.org/10.1145/1930037.1930046
ER -
TY - CPAPER
ID - DBLP:conf/issoc/KrsticFGHSBKSB11
AU - Krstic, Milos
AU - Fan, Xin
AU - Grass, Eckhard
AU - Heer, Christoph
AU - Sanders, Birgit
AU - Benini, Luca
AU - Kakoee, Mohammad Reza
AU - Strano, Alessandro
AU - Bertozzi, Davide
TI - Moonrake chip - GALS demonstrator in 40 nm CMOS technology.
BT - 2011 International Symposium on System on Chip, SoC 2011, Tampere, Finland, October 31 - November 2, 2011
SP - 9
EP - 13
PY - 2011//
DO - 10.1109/ISSOC.2011.6089693
UR - https://doi.org/10.1109/ISSOC.2011.6089693
ER -
TY - CPAPER
ID - DBLP:conf/issoc/FerraresiGLB11
AU - Ferraresi, Marco
AU - Gobbo, Giuseppina
AU - Ludovici, Daniele
AU - Bertozzi, Davide
TI - Bringing Network-on-Chip links to 45nm.
BT - 2011 International Symposium on System on Chip, SoC 2011, Tampere, Finland, October 31 - November 2, 2011
SP - 122
EP - 127
PY - 2011//
DO - 10.1109/ISSOC.2011.6089686
UR - https://doi.org/10.1109/ISSOC.2011.6089686
ER -
TY - CPAPER
ID - DBLP:conf/micro/TatenguemLSBR11
AU - Tatenguem, Hervé
AU - Ludovici, Daniele
AU - Strano, Alessandro
AU - Bertozzi, Davide
AU - Reinig, Helmut
TI - Contrasting multi-synchronous MPSoC design styles for fine-grained clock domain partitioning: the full-HD video playback case study.
BT - 4th International Workshop on Network on Chip Architectures, NoCArc '11, Porto Alegre, Brazil, December 4-5, 2011
SP - 37
EP - 42
PY - 2011//
DO - 10.1145/2076501.2076509
UR - https://doi.org/10.1145/2076501.2076509
ER -
TY - CPAPER
ID - DBLP:conf/vlsi/GhiribaldiLFB11
AU - Ghiribaldi, Alberto
AU - Ludovici, Daniele
AU - Favalli, Michele
AU - Bertozzi, Davide
TI - System-level infrastructure for boot-time testing and configuration of networks-on-chip with programmable routing logic.
BT - IEEE/IFIP 19th International Conference on VLSI and System-on-Chip, VLSI-SoC 2011, Kowloon, Hong Kong, China, October 3-5, 2011
SP - 308
EP - 313
PY - 2011//
DO - 10.1109/VLSISOC.2011.6081597
UR - https://doi.org/10.1109/VLSISoC.2011.6081597
ER -
TY - CONF
ID - DBLP:conf/hipeac/2011ina-ocmc
ED - Flich, José
ED - Bertozzi, Davide
ED - Skeie, Tor
ED - Ludovici, Daniele
TI - Proceedings of the Fifth International Workshop on Interconnection Network Architecture - On-Chip, Multi-Chip, INA-OCMC '11, Heraklion, Greece, January 23, 2011
PY - 2011//
PB - ACM
DO - 10.1145/1930037
UR - https://doi.org/10.1145/1930037
SN - ISBN 978-1-4503-0272-2
ER -
TY - CPAPER
ID - DBLP:conf/date/LudoviciSGBB10
AU - Ludovici, Daniele
AU - Strano, Alessandro
AU - Gaydadjiev, Georgi Nedeltchev
AU - Benini, Luca
AU - Bertozzi, Davide
TI - Design space exploration of a mesochronous link for cost-effective and flexible GALS NOCs.
BT - Design, Automation and Test in Europe, DATE 2010, Dresden, Germany, March 8-12, 2010
SP - 679
EP - 684
PY - 2010//
DO - 10.1109/DATE.2010.5457116
UR - https://doi.org/10.1109/DATE.2010.5457116
UR - http://dl.acm.org/citation.cfm?id=1871091
ER -
TY - CPAPER
ID - DBLP:conf/issoc/StranoHSB10
AU - Strano, Alessandro
AU - Hernández, Carles
AU - Silla, Federico
AU - Bertozzi, Davide
TI - Process variation and layout mismatch tolerant design of source synchronous links for GALS networks-on-chip.
BT - 2010 International Symposium on System on Chip, SoC 2010, Tampere, September 29-30, 2010
SP - 43
EP - 48
PY - 2010//
DO - 10.1109/ISSOC.2010.5625539
UR - https://doi.org/10.1109/ISSOC.2010.5625539
ER -
TY - CPAPER
ID - DBLP:conf/micro/LudoviciGVGB10
AU - Ludovici, Daniele
AU - Gaydadjiev, Georgi Nedeltchev
AU - Villamón, Francisco Gilabert
AU - Gómez, María Engracia
AU - Bertozzi, Davide
TI - Contrasting topologies for regular interconnection networks under the constraints of nanoscale silicon technology.
BT - Third International Workshop on Network on Chip Architectures, NoCArc'10, Atlanta, GA, USA, December 4, 2010
SP - 37
EP - 42
PY - 2010//
DO - 10.1145/1921249.1921259
UR - https://doi.org/10.1145/1921249.1921259
ER -
TY - CPAPER
ID - DBLP:conf/nocs/RodrigoFRMBCSD10
AU - Rodrigo, Samuel
AU - Flich, José
AU - Roca, Antoni
AU - Medardoni, Simone
AU - Bertozzi, Davide
AU - Villanueva, Jesús Camacho
AU - Silla, Federico
AU - Duato, José
TI - Addressing Manufacturing Challenges with Cost-Efficient Fault Tolerant Routing.
BT - NOCS 2010, Fourth ACM/IEEE International Symposium on Networks-on-Chip, Grenoble, France, May 3-6, 2010
SP - 25
EP - 32
PY - 2010//
DO - 10.1109/NOCS.2010.12
UR - https://doi.org/10.1109/NOCS.2010.12
UR - https://doi.ieeecomputersociety.org/10.1109/NOCS.2010.12
ER -
TY - CPAPER
ID - DBLP:conf/nocs/VillamonGMB10
AU - Villamón, Francisco Gilabert
AU - Gómez, María Engracia
AU - Medardoni, Simone
AU - Bertozzi, Davide
TI - Improved Utilization of NoC Channel Bandwidth by Switch Replication for Cost-Effective Multi-processor Systems-on-Chip.
BT - NOCS 2010, Fourth ACM/IEEE International Symposium on Networks-on-Chip, Grenoble, France, May 3-6, 2010
SP - 165
EP - 172
PY - 2010//
DO - 10.1109/NOCS.2010.25
UR - https://doi.org/10.1109/NOCS.2010.25
UR - https://doi.ieeecomputersociety.org/10.1109/NOCS.2010.25
ER -
TY - CPAPER
ID - DBLP:conf/samos/StranoLB10
AU - Strano, Alessandro
AU - Ludovici, Daniele
AU - Bertozzi, Davide
TI - A library of dual-clock FIFOs for cost-effective and flexible MPSoC design.
BT - Proceedings of the 2010 International Conference on Embedded Computer Systems: Architectures, Modeling and Simulation (IC-SAMOS 2010), Samos, Greece, July 19-22, 2010
SP - 20
EP - 27
PY - 2010//
DO - 10.1109/ICSAMOS.2010.5642098
UR - https://doi.org/10.1109/ICSAMOS.2010.5642098
ER -
TY - JOUR
ID - DBLP:journals/iet-cdt/BertozziG09
AU - Bertozzi, Davide
AU - Goossens, Kees
TI - Networks on chips [editorial].
JO - IET Comput. Digit. Tech.
VL - 3
IS - 5
SP - 395
EP - 397
PY - 2009//
DO - 10.1049/IET-CDT.2009.9039
UR - https://doi.org/10.1049/iet-cdt.2009.9039
ER -
TY - JOUR
ID - DBLP:journals/iet-cdt/RodrigoMFBD09
AU - Rodrigo, Samuel
AU - Medardoni, Simone
AU - Flich, José
AU - Bertozzi, Davide
AU - Duato, José
TI - Efficient implementation of distributed routing algorithms for NoCs.
JO - IET Comput. Digit. Tech.
VL - 3
IS - 5
SP - 460
EP - 475
PY - 2009//
DO - 10.1049/IET-CDT.2008.0092
UR - https://doi.org/10.1049/iet-cdt.2008.0092
ER -
TY - JOUR
ID - DBLP:journals/tcad/RuggieroBBMA09
AU - Ruggiero, Martino
AU - Bertozzi, Davide
AU - Benini, Luca
AU - Milano, Michela
AU - Andrei, Alexandru
TI - Reducing the Abstraction and Optimality Gaps in the Allocation and Scheduling for Variable Voltage/Frequency MPSoC Platforms.
JO - IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
VL - 28
IS - 3
SP - 378
EP - 391
PY - 2009//
DO - 10.1109/TCAD.2009.2013536
UR - https://doi.org/10.1109/TCAD.2009.2013536
ER -
TY - CPAPER
ID - DBLP:conf/cisis/VillamonLMBBG09
AU - Villamón, Francisco Gilabert
AU - Ludovici, Daniele
AU - Medardoni, Simone
AU - Bertozzi, Davide
AU - Benini, Luca
AU - Gaydadjiev, Georgi Nedeltchev
TI - Designing Regular Network-on-Chip Topologies under Technology, Architecture and Software Constraints.
BT - 2009 International Conference on Complex, Intelligent and Software Intensive Systems, CISIS 2009, Fukuoka, Japan, March 16-19, 2009
SP - 681
EP - 687
PY - 2009//
DO - 10.1109/CISIS.2009.30
UR - https://doi.org/10.1109/CISIS.2009.30
UR - https://doi.ieeecomputersociety.org/10.1109/CISIS.2009.30
ER -
TY - CPAPER
ID - DBLP:conf/date/LudoviciVMRGLGB09
AU - Ludovici, Daniele
AU - Villamón, Francisco Gilabert
AU - Medardoni, Simone
AU - Requena, Crispín Gómez
AU - Gómez, María Engracia
AU - López, Pedro
AU - Gaydadjiev, Georgi Nedeltchev
AU - Bertozzi, Davide
TI - Assessing fat-tree topologies for regular network-on-chip design under nanoscale technology constraints.
BT - Design, Automation and Test in Europe, DATE 2009, Nice, France, April 20-24, 2009
SP - 562
EP - 565
PY - 2009//
DO - 10.1109/DATE.2009.5090727
UR - https://doi.org/10.1109/DATE.2009.5090727
UR - http://dl.acm.org/citation.cfm?id=1874757
ER -
TY - CPAPER
ID - DBLP:conf/date/PaciBB09
AU - Paci, Giacomo
AU - Bertozzi, Davide
AU - Benini, Luca
TI - Effectiveness of adaptive supply voltage and body bias as post-silicon variability compensation techniques for full-swing and low-swing on-chip communication channels.
BT - Design, Automation and Test in Europe, DATE 2009, Nice, France, April 20-24, 2009
SP - 1404
EP - 1409
PY - 2009//
DO - 10.1109/DATE.2009.5090884
UR - https://doi.org/10.1109/DATE.2009.5090884
UR - http://dl.acm.org/citation.cfm?id=1874959
ER -
TY - CPAPER
ID - DBLP:conf/glvlsi/LudoviciGBB09
AU - Ludovici, Daniele
AU - Gaydadjiev, Georgi Nedeltchev
AU - Bertozzi, Davide
AU - Benini, Luca
TI - Capturing topology-level implications of link synthesis techniques for nanoscale networks-on-chip.
BT - Proceedings of the 19th ACM Great Lakes Symposium on VLSI 2009, Boston Area, MA, USA, May 10-12 2009
SP - 125
EP - 128
PY - 2009//
DO - 10.1145/1531542.1531574
UR - https://doi.org/10.1145/1531542.1531574
ER -
TY - CPAPER
ID - DBLP:conf/issoc/SkeieSRFBM09
AU - Skeie, Tor
AU - Sem-Jacobsen, Frank Olaf
AU - Rodrigo, Samuel
AU - Flich, José
AU - Bertozzi, Davide
AU - Medardoni, Simone
TI - Flexible DOR routing for virtualization of multicore chips.
BT - 2008 IEEE International Symposium on System-on-Chip, SOC 2009, Tampere, Finland, October 6-7, 2008
SP - 73
EP - 76
PY - 2009//
DO - 10.1109/SOCC.2009.5335673
UR - https://doi.org/10.1109/SOCC.2009.5335673
ER -
TY - CPAPER
ID - DBLP:conf/issoc/RodrigoHFSDMBMD09
AU - Rodrigo, Samuel
AU - Hernández, Carles
AU - Flich, José
AU - Silla, Federico
AU - Duato, José
AU - Medardoni, Simone
AU - Bertozzi, Davide
AU - Mejia, Andres
AU - Dai, Donglai
TI - Yield-oriented evaluation methodology of network-on-chip routing implementations.
BT - 2008 IEEE International Symposium on System-on-Chip, SOC 2009, Tampere, Finland, October 6-7, 2008
SP - 100
EP - 105
PY - 2009//
DO - 10.1109/SOCC.2009.5335667
UR - https://doi.org/10.1109/SOCC.2009.5335667
ER -
TY - CPAPER
ID - DBLP:conf/micro/LudoviciSB09
AU - Ludovici, Daniele
AU - Strano, Alessandro
AU - Bertozzi, Davide
TI - Architecture design principles for the integration of synchronization interfaces into Network-on-Chip switches.
BT - Second International Workshop on Network on Chip Architectures, NoCArc 2009, In conjunction with the 42nd Annual IEEE/ACM International Symposium on Microarchitecture (MICRO-42), December 12, 2009, New York, NY, USA
SP - 31
EP - 36
PY - 2009//
DO - 10.1145/1645213.1645222
UR - https://doi.org/10.1145/1645213.1645222
ER -
TY - CPAPER
ID - DBLP:conf/nocs/LudoviciSBBG09
AU - Ludovici, Daniele
AU - Strano, Alessandro
AU - Bertozzi, Davide
AU - Benini, Luca
AU - Gaydadjiev, Georgi
TI - Comparing tightly and loosely coupled mesochronous synchronizers in a NoC switch architecture.
BT - Third International Symposium on Networks-on-Chips, NOCS 2009, May 10-13 2009, La Jolla, CA, USA. Proceedings
SP - 244
EP - 249
PY - 2009//
DO - 10.1109/NOCS.2009.5071473
UR - https://doi.org/10.1109/NOCS.2009.5071473
UR - https://doi.ieeecomputersociety.org/10.1109/NOCS.2009.5071473
ER -
TY - CHAP
ID - DBLP:books/crc/zurawski2009/AyalaLBB09
AU - Ayala, José L.
AU - López-Vallejo, Marisa
AU - Bertozzi, Davide
AU - Benini, Luca
TI - SoC Communication Architectures: From Interconnection Buses to Packet-Switched NoCs.
BT - Embedded Systems Design and Verification - Volume 1 of the Embedded Systems Handbook
SP - 14
PY - 2009//
DO - 10.1201/9781439807637.CH14
UR - https://doi.org/10.1201/9781439807637.ch14
ER -
TY - CHAP
ID - DBLP:books/crc/zurawski2009/VillamonBBM09
AU - Villamón, Francisco Gilabert
AU - Bertozzi, Davide
AU - Benini, Luca
AU - Micheli, Giovanni De
TI - Networks-on-Chip: an Interconnect Fabric for Multiprocessor Systems-on-Chip.
BT - Embedded Systems Design and Verification - Volume 1 of the Embedded Systems Handbook
SP - 15
PY - 2009//
DO - 10.1201/9781439807637.CH15
UR - https://doi.org/10.1201/9781439807637.ch15
ER -
TY - JOUR
ID - DBLP:journals/ijpp/RuggieroGBMB08
AU - Ruggiero, Martino
AU - Guerri, Alessio
AU - Bertozzi, Davide
AU - Milano, Michela
AU - Benini, Luca
TI - A Fast and Accurate Technique for Mapping Parallel Applications on Stream-Oriented MPSoC Platforms with Communication Awareness.
JO - Int. J. Parallel Program.
VL - 36
IS - 1
SP - 3
EP - 36
PY - 2008//
DO - 10.1007/S10766-007-0032-7
UR - https://doi.org/10.1007/s10766-007-0032-7
ER -
TY - JOUR
ID - DBLP:journals/todaes/KhatibPBBBKJN08
AU - Khatib, Iyad Al
AU - Poletti, Francesco
AU - Bertozzi, Davide
AU - Benini, Luca
AU - Bechara, Mohamed
AU - Khalifeh, Hasan
AU - Jantsch, Axel
AU - Nabiev, Rustam
TI - A multiprocessor system-on-chip for real-time biomedical monitoring and analysis: ECG prototype architectural design space exploration.
JO - ACM Trans. Design Autom. Electr. Syst.
VL - 13
IS - 2
SP - 31:1
EP - 31:21
PY - 2008//
DO - 10.1145/1344418.1344427
UR - https://doi.org/10.1145/1344418.1344427
ER -
TY - CPAPER
ID - DBLP:conf/date/StefanoBBM08
AU - Stefano, Bonesi
AU - Bertozzi, Davide
AU - Benini, Luca
AU - Macii, Enrico
TI - Process Variation Tolerant Pipeline Design Through a Placement-Aware Multiple Voltage Island Design Style.
BT - Design, Automation and Test in Europe, DATE 2008, Munich, Germany, March 10-14, 2008
SP - 967
EP - 972
PY - 2008//
DO - 10.1109/DATE.2008.4484806
UR - https://doi.org/10.1109/DATE.2008.4484806
UR - https://doi.ieeecomputersociety.org/10.1109/DATE.2008.4484806
UR - https://doi.org/10.1145/1403375.1403610
ER -
TY - CPAPER
ID - DBLP:conf/date/MedardoniLB08
AU - Medardoni, Simone
AU - Lajolo, Marcello
AU - Bertozzi, Davide
TI - Variation tolerant NoC design by means of self-calibrating links.
BT - Design, Automation and Test in Europe, DATE 2008, Munich, Germany, March 10-14, 2008
SP - 1402
EP - 1407
PY - 2008//
DO - 10.1109/DATE.2008.4484870
UR - https://doi.org/10.1109/DATE.2008.4484870
UR - https://doi.ieeecomputersociety.org/10.1109/DATE.2008.4484870
UR - https://doi.org/10.1145/1403375.1403715
ER -
TY - CPAPER
ID - DBLP:conf/dsd/FerranteMB08
AU - Ferrante, Alberto
AU - Medardoni, Simone
AU - Bertozzi, Davide
TI - Network Interface Sharing Techniques for Area Optimized NoC Architectures.
BT - 11th Euromicro Conference on Digital System Design: Architectures, Methods and Tools, DSD 2008, Parma, Italy, September 3-5, 2008
SP - 10
EP - 17
PY - 2008//
DO - 10.1109/DSD.2008.111
UR - https://doi.org/10.1109/DSD.2008.111
UR - https://doi.ieeecomputersociety.org/10.1109/DSD.2008.111
ER -
TY - CPAPER
ID - DBLP:conf/iclp/BeniniBM08
AU - Benini, Luca
AU - Bertozzi, Davide
AU - Milano, Michela
TI - Resource Management Policy Handling Multiple Use-Cases in MPSoC Platforms Using Constraint Programming.
BT - Logic Programming, 24th International Conference, ICLP 2008, Udine, Italy, December 9-13 2008, Proceedings
SP - 470
EP - 484
PY - 2008//
DO - 10.1007/978-3-540-89982-2_41
UR - https://doi.org/10.1007/978-3-540-89982-2_41
ER -
TY - CPAPER
ID - DBLP:conf/nocs/GilabertMBBGLD08
AU - Villamón, Francisco Gilabert
AU - Medardoni, Simone
AU - Bertozzi, Davide
AU - Benini, Luca
AU - Gómez, María Engracia
AU - López, Pedro
AU - Duato, José
TI - Exploring High-Dimensional Topologies for NoC Design Through an Integrated Analysis and Synthesis Framework.
BT - Second International Symposium on Networks-on-Chips, NOCS 2008, 5-6 April 2008, Newcastle University, UK. Proceedings
SP - 107
EP - 116
PY - 2008//
DO - 10.1109/NOCS.2008.14
UR - https://doi.ieeecomputersociety.org/10.1109/NOCS.2008.14
ER -
TY - JOUR
ID - DBLP:journals/tc/PolettiPBBMLP07
AU - Poletti, Francesco
AU - Poggiali, Antonio
AU - Bertozzi, Davide
AU - Benini, Luca
AU - Marchal, Pol
AU - Loghi, Mirko
AU - Poncino, Massimo
TI - Energy-Efficient Multiprocessor Systems-on-Chip for Embedded Computing: Exploring Programming Models and Their Architectural Support.
JO - IEEE Trans. Computers
VL - 56
IS - 5
SP - 606
EP - 621
PY - 2007//
DO - 10.1109/TC.2007.1040
UR - https://doi.org/10.1109/TC.2007.1040
UR - https://doi.ieeecomputersociety.org/10.1109/TC.2007.1040
ER -
TY - JOUR
ID - DBLP:journals/thipeac/KhatibBPBJBKHNJ07
AU - Khatib, Iyad Al
AU - Bertozzi, Davide
AU - Poletti, Francesco
AU - Benini, Luca
AU - Jantsch, Axel
AU - Bechara, Mohamed
AU - Khalifeh, Hasan
AU - Hajjar, Mazen
AU - Nabiev, Rustam
AU - Jonsson, Sven
TI - Hardware/Software Architecture for Real-Time ECG Monitoring and Analysis Leveraging MPSoC Technology.
JO - Trans. High Perform. Embed. Archit. Compil.
VL - 1
SP - 239
EP - 258
PY - 2007//
DO - 10.1007/978-3-540-71528-3_16
UR - https://doi.org/10.1007/978-3-540-71528-3_16
ER -
TY - JOUR
ID - DBLP:journals/vlsi/BertozziKP07
AU - Bertozzi, Davide
AU - Kumar, Shashi
AU - Palesi, Maurizio
TI - Networks-on-Chip: Emerging Research Topics and Novel Ideas.
JO - VLSI Design
VL - 2007
SP - 26454:1
EP - 26454:3
PY - 2007//
DO - 10.1155/2007/26454
UR - https://doi.org/10.1155/2007/26454
ER -
TY - CPAPER
ID - DBLP:conf/codes/KhatibBJB07
AU - Khatib, Iyad Al
AU - Bertozzi, Davide
AU - Jantsch, Axel
AU - Benini, Luca
TI - Performance analysis and design space exploration for high-end biomedical applications: challenges and solutions.
BT - Proceedings of the 5th International Conference on Hardware/Software Codesign and System Synthesis, CODES+ISSS 2007, Salzburg, Austria, September 30 - October 3, 2007
SP - 217
EP - 226
PY - 2007//
DO - 10.1145/1289816.1289870
UR - https://doi.org/10.1145/1289816.1289870
ER -
TY - CPAPER
ID - DBLP:conf/date/MedardoniRBBSP07
AU - Medardoni, Simone
AU - Ruggiero, Martino
AU - Bertozzi, Davide
AU - Benini, Luca
AU - Strano, Giovanni
AU - Pistritto, Carlo
TI - Interactive presentation: Capturing the interaction of the communication, memory and I/O subsystems in memory-centric industrial MPSoC platforms.
BT - 2007 Design, Automation and Test in Europe Conference and Exposition, DATE 2007, Nice, France, April 16-20, 2007
SP - 660
EP - 665
PY - 2007//
DO - 10.1109/DATE.2007.364669
UR - https://doi.org/10.1109/DATE.2007.364669
UR - https://doi.ieeecomputersociety.org/10.1109/DATE.2007.364669
UR - http://dl.acm.org/citation.cfm?id=1266505
ER -
TY - CPAPER
ID - DBLP:conf/islped/MedardoniBM07
AU - Medardoni, Simone
AU - Bertozzi, Davide
AU - Macii, Enrico
TI - Power-optimal RTL arithmetic unit soft-macro selection strategy for leakage-sensitive technologies.
BT - Proceedings of the 2007 International Symposium on Low Power Electronics and Design, 2007, Portland, OR, USA, August 27-29, 2007
SP - 159
EP - 164
PY - 2007//
DO - 10.1145/1283780.1283815
UR - https://doi.org/10.1145/1283780.1283815
ER -
TY - CPAPER
ID - DBLP:conf/issoc/MedardoniBBM07
AU - Medardoni, Simone
AU - Bertozzi, Davide
AU - Benini, Luca
AU - Macii, Enrico
TI - Control and datapath decoupling in the design of a NoC switch: area, power and performance implications.
BT - International Symposium on System-on-Chip, SoC 2007, Tampere, Finland, November 20-21, 2007
SP - 1
EP - 4
PY - 2007//
DO - 10.1109/ISSOC.2007.4427438
UR - https://doi.org/10.1109/ISSOC.2007.4427438
ER -
TY - CPAPER
ID - DBLP:conf/cf/KhatibBPBJBKHNJ06
AU - Khatib, Iyad Al
AU - Bertozzi, Davide
AU - Poletti, Francesco
AU - Benini, Luca
AU - Jantsch, Axel
AU - Bechara, Mohamed
AU - Khalifeh, Hasan
AU - Hajjar, Mazen
AU - Nabiev, Rustam
AU - Jonsson, Sven
TI - MPSoC ECG biochip: a multiprocessor system-on-chip for real-time human heart monitoring and analysis.
BT - Proceedings of the Third Conference on Computing Frontiers, 2006, Ischia, Italy, May 3-5, 2006
SP - 21
EP - 28
PY - 2006//
DO - 10.1145/1128022.1128028
UR - https://doi.org/10.1145/1128022.1128028
ER -
TY - CPAPER
ID - DBLP:conf/cpaior/BeniniBGM06
AU - Benini, Luca
AU - Bertozzi, Davide
AU - Guerri, Alessio
AU - Milano, Michela
TI - Allocation, Scheduling and Voltage Scaling on Energy Aware MPSoCs.
BT - Integration of AI and OR Techniques in Constraint Programming for Combinatorial Optimization Problems, Third International Conference, CPAIOR 2006, Cork, Ireland, May 31 - June 2, 2006, Proceedings
SP - 44
EP - 58
PY - 2006//
DO - 10.1007/11757375_6
UR - https://doi.org/10.1007/11757375_6
ER -
TY - CPAPER
ID - DBLP:conf/dac/KhatibPBBBKJN06
AU - Khatib, Iyad Al
AU - Poletti, Francesco
AU - Bertozzi, Davide
AU - Benini, Luca
AU - Bechara, Mohamed
AU - Khalifeh, Hasan
AU - Jantsch, Axel
AU - Nabiev, Rustam
TI - A multiprocessor system-on-chip for real-time biomedical monitoring and analysis: architectural design space exploration.
BT - Proceedings of the 43rd Design Automation Conference, DAC 2006, San Francisco, CA, USA, July 24-28, 2006
SP - 125
EP - 130
PY - 2006//
DO - 10.1145/1146909.1146947
UR - https://doi.org/10.1145/1146909.1146947
ER -
TY - CPAPER
ID - DBLP:conf/date/RuggieroGBPM06
AU - Ruggiero, Martino
AU - Guerri, Alessio
AU - Bertozzi, Davide
AU - Poletti, Francesco
AU - Milano, Michela
TI - Communication-aware allocation and scheduling framework for stream-oriented multi-processor systems-on-chip.
BT - Proceedings of the Conference on Design, Automation and Test in Europe, DATE 2006, Munich, Germany, March 6-10, 2006
SP - 3
EP - 8
PY - 2006//
DO - 10.1109/DATE.2006.243950
UR - https://doi.org/10.1109/DATE.2006.243950
UR - https://doi.ieeecomputersociety.org/10.1109/DATE.2006.243950
UR - http://dl.acm.org/citation.cfm?id=1131486
ER -
TY - CPAPER
ID - DBLP:conf/date/BertozziABP06
AU - Bertozzi, Stefano
AU - Acquaviva, Andrea
AU - Bertozzi, Davide
AU - Poggiali, Antonio
TI - Supporting task migration in multi-processor systems-on-chip: a feasibility study.
BT - Proceedings of the Conference on Design, Automation and Test in Europe, DATE 2006, Munich, Germany, March 6-10, 2006
SP - 15
EP - 20
PY - 2006//
DO - 10.1109/DATE.2006.243952
UR - https://doi.org/10.1109/DATE.2006.243952
UR - https://doi.ieeecomputersociety.org/10.1109/DATE.2006.243952
UR - http://dl.acm.org/citation.cfm?id=1131488
ER -
TY - CPAPER
ID - DBLP:conf/issoc/RuggieroGABMBA06
AU - Ruggiero, Martino
AU - Gioia, Pari
AU - Alessio, Guerri
AU - Benini, Luca
AU - Milano, Michela
AU - Bertozzi, Davide
AU - Andrei, Alexandru
TI - A Cooperative, Accurate Solving Framework for Optimal Allocation, Scheduling and Frequency Selection on Energy-Efficient MPSoCs.
BT - International Symposium on System-on-Chip, SoC 2006, Tampere, Finland, November 13-16, 2006
SP - 1
EP - 4
PY - 2006//
DO - 10.1109/ISSOC.2006.321997
UR - https://doi.org/10.1109/ISSOC.2006.321997
ER -
TY - JOUR
ID - DBLP:journals/ia/BeniniBGMP05
AU - Benini, Luca
AU - Bertozzi, Davide
AU - Guerri, Alessio
AU - Milano, Michela
AU - Poletti, Francesco
TI - Measuring Efficiency and Executability of Allocation and Scheduling in Multi-Processor Systems-on-Chip.
JO - Intelligenza Artificiale
VL - 2
IS - 3
SP - 13
EP - 20
PY - 2005//
ER -
TY - JOUR
ID - DBLP:journals/tcad/BertozziBM05
AU - Bertozzi, Davide
AU - Benini, Luca
AU - Micheli, Giovanni De
TI - Error control schemes for on-chip communication links: the energy-reliability tradeoff.
JO - IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
VL - 24
IS - 6
SP - 818
EP - 831
PY - 2005//
DO - 10.1109/TCAD.2005.847907
UR - https://doi.org/10.1109/TCAD.2005.847907
ER -
TY - JOUR
ID - DBLP:journals/tpds/BertozziJMTSBM05
AU - Bertozzi, Davide
AU - Jalabert, Antoine
AU - Murali, Srinivasan
AU - Tamhankar, Rutuparna
AU - Stergiou, Stergios
AU - Benini, Luca
AU - Micheli, Giovanni De
TI - NoC Synthesis Flow for Customized Domain Specific Multiprocessor Systems-on-Chip.
JO - IEEE Trans. Parallel Distributed Syst.
VL - 16
IS - 2
SP - 113
EP - 129
PY - 2005//
DO - 10.1109/TPDS.2005.22
UR - https://doi.org/10.1109/TPDS.2005.22
UR - http://doi.ieeecomputersociety.org/10.1109/TPDS.2005.22
ER -
TY - JOUR
ID - DBLP:journals/vlsisp/BeniniBBMO05
AU - Benini, Luca
AU - Bertozzi, Davide
AU - Bogliolo, Alessandro
AU - Menichelli, Francesco
AU - Olivieri, Mauro
TI - MPARM: Exploring the Multi-Processor SoC Design Space with SystemC.
JO - J. VLSI Signal Process.
VL - 41
IS - 2
SP - 169
EP - 182
PY - 2005//
DO - 10.1007/S11265-005-6648-1
UR - https://doi.org/10.1007/s11265-005-6648-1
ER -
TY - CPAPER
ID - DBLP:conf/cp/BeniniBGM05
AU - Benini, Luca
AU - Bertozzi, Davide
AU - Guerri, Alessio
AU - Milano, Michela
TI - Allocation and Scheduling for MPSoCs via Decomposition and No-Good Generation.
BT - Principles and Practice of Constraint Programming - CP 2005, 11th International Conference, CP 2005, Sitges, Spain, October 1-5, 2005, Proceedings
SP - 107
EP - 121
PY - 2005//
DO - 10.1007/11564751_11
UR - https://doi.org/10.1007/11564751_11
ER -
TY - CPAPER
ID - DBLP:conf/date/StergiouACRBM05
AU - Stergiou, Stergios
AU - Angiolini, Federico
AU - Carta, Salvatore
AU - Raffo, Luigi
AU - Bertozzi, Davide
AU - Micheli, Giovanni De
TI - xpipes Lite: A Synthesis Oriented Design Library For Networks on Chips.
BT - 2005 Design, Automation and Test in Europe Conference and Exposition (DATE 2005), 7-11 March 2005, Munich, Germany
SP - 1188
EP - 1193
PY - 2005//
DO - 10.1109/DATE.2005.1
UR - https://doi.org/10.1109/DATE.2005.1
UR - https://doi.ieeecomputersociety.org/10.1109/DATE.2005.1
UR - http://dl.acm.org/citation.cfm?id=1049297
ER -
TY - CPAPER
ID - DBLP:conf/iccd/RuggieroABB05
AU - Ruggiero, Martino
AU - Acquaviva, Andrea
AU - Bertozzi, Davide
AU - Benini, Luca
TI - Application-Specific Power-Aware Workload Allocation for Voltage Scalable MPSoC Platforms.
BT - 23rd International Conference on Computer Design (ICCD 2005), 2-5 October 2005, San Jose, CA, USA
SP - 87
EP - 93
PY - 2005//
DO - 10.1109/ICCD.2005.24
UR - https://doi.org/10.1109/ICCD.2005.24
UR - https://doi.ieeecomputersociety.org/10.1109/ICCD.2005.24
ER -
TY - CPAPER
ID - DBLP:conf/ijcai/BeniniBGM05
AU - Benini, Luca
AU - Bertozzi, Davide
AU - Guerri, Alessio
AU - Milano, Michela
TI - Allocation and Scheduling for MPSoCs via decomposition and no-good generation.
BT - IJCAI-05, Proceedings of the Nineteenth International Joint Conference on Artificial Intelligence, Edinburgh, Scotland, UK, July 30 - August 5, 2005
SP - 1517
EP - 1518
PY - 2005//
UR - http://ijcai.org/Proceedings/05/Papers/post-0368.pdf
ER -
TY - CPAPER
ID - DBLP:conf/sbcci/PulliniABB05
AU - Pullini, Antonio
AU - Angiolini, Federico
AU - Bertozzi, Davide
AU - Benini, Luca
TI - Fault tolerance overhead in network-on-chip flow control schemes.
BT - Proceedings of the 18th Annual Symposium on Integrated Circuits and Systems Design, SBCCI 2005, Florianolpolis, Brazil, September 4-7, 2005
SP - 224
EP - 229
PY - 2005//
DO - 10.1145/1081081.1081138
UR - https://doi.org/10.1145/1081081.1081138
ER -
TY - CHAP
ID - DBLP:books/crc/IIR2005/BertozziBM05
AU - Bertozzi, Davide
AU - Benini, Luca
AU - Micheli, Giovanni De
TI - Network On-Chip Design for Gigascale Systems-on-Chip.
BT - The Industrial Information Technology Handbook
PY - 2005//
ER -
TY - ENCYC
ID - DBLP:reference/crc/BeniniBM05
AU - Benini, Luca
AU - Bertozzi, Davide
AU - Micheli, Giovanni De
TI - Network-on-Chip Design for Gigascale Systems-on-Chip.
BT - Embedded Systems Handbook.
PY - 2005//
DO - 10.1201/9781420038163.CH21
UR - https://doi.org/10.1201/9781420038163.ch21
ER -
TY - ENCYC
ID - DBLP:reference/crc/BertozziBLA05
AU - Bertozzi, Davide
AU - Benini, Luca
AU - López-Vallejo, Marisa
AU - Ayala, José L.
TI - State-of-the-Art SoC Communication Architectures.
BT - Embedded Systems Handbook.
PY - 2005//
DO - 10.1201/9781420038163.CH20
UR - https://doi.org/10.1201/9781420038163.ch20
ER -
TY - CPAPER
ID - DBLP:conf/date/LoghiABBZ04
AU - Loghi, Mirko
AU - Angiolini, Federico
AU - Bertozzi, Davide
AU - Benini, Luca
AU - Zafalon, Roberto
TI - Analyzing On-Chip Communication in a MPSoC Environment.
BT - 2004 Design, Automation and Test in Europe Conference and Exposition (DATE 2004), 16-20 February 2004, Paris, France
SP - 752
EP - 757
PY - 2004//
DO - 10.1109/DATE.2004.1268966
UR - https://doi.org/10.1109/DATE.2004.1268966
UR - https://doi.ieeecomputersociety.org/10.1109/DATE.2004.1268966
UR - http://dl.acm.org/citation.cfm?id=969124
ER -
TY - CHAP
ID - DBLP:books/sp/04/BertozziBM04
AU - Bertozzi, Davide
AU - Benini, Luca
AU - Micheli, Giovanni De
TI - Energy-Efficient Network-On-Chip Design.
BT - Ultra Low-Power Electronics and Design
SP - 214
EP - 232
PY - 2004//
DO - 10.1007/1-4020-8076-X_12
UR - https://doi.org/10.1007/1-4020-8076-X_12
ER -
TY - JOUR
ID - DBLP:journals/computer/BeniniBBDFP03
AU - Benini, Luca
AU - Bertozzi, Davide
AU - Bruni, Davide
AU - Drago, Nicola
AU - Fummi, Franco
AU - Poncino, Massimo
TI - SystemC Cosimulation and Emulation of Multiprocessor SoC Designs.
JO - Computer
VL - 36
IS - 4
SP - 53
EP - 59
PY - 2003//
DO - 10.1109/MC.2003.1193229
UR - https://doi.org/10.1109/MC.2003.1193229
UR - http://doi.ieeecomputersociety.org/10.1109/MC.2003.1193229
ER -
TY - JOUR
ID - DBLP:journals/dafes/PolettiBBB03
AU - Poletti, Francesco
AU - Bertozzi, Davide
AU - Benini, Luca
AU - Bogliolo, Alessandro
TI - Performance Analysis of Arbitration Policies for SoC Communication Architectures.
JO - Des. Autom. Embed. Syst.
VL - 8
IS - 2-3
SP - 189
EP - 210
PY - 2003//
DO - 10.1023/B:DAEM.0000003962.54165.5C
UR - https://doi.org/10.1023/B:DAEM.0000003962.54165.5c
ER -
TY - CPAPER
ID - DBLP:conf/date/BertozziRBR03
AU - Bertozzi, Davide
AU - Raghunathan, Anand
AU - Benini, Luca
AU - Ravi, Srivaths
TI - Transport Protocol Optimization for Energy Efficient Wireless Embedded Systems.
BT - 2003 Design, Automation and Test in Europe Conference and Exposition (DATE 2003), 3-7 March 2003, Munich, Germany
SP - 10706
EP - 10713
PY - 2003//
DO - 10.1109/DATE.2003.10152
UR - https://doi.ieeecomputersociety.org/10.1109/DATE.2003.10152
UR - http://dl.acm.org/citation.cfm?id=1022808
ER -
TY - CPAPER
ID - DBLP:conf/iccd/DallOssoBGBB03
AU - Dall'Osso, Matteo
AU - Biccari, Gianluca
AU - Giovannini, Luca
AU - Bertozzi, Davide
AU - Benini, Luca
TI - xpipes: a Latency Insensitive Parameterized Network-on-chip Architecture For Multi-Processor SoCs.
BT - 21st International Conference on Computer Design (ICCD 2003),VLSI in Computers and Processors, 13-15 October 2003, San Jose, CA, USA, Proceedings
SP - 536
EP -
PY - 2003//
DO - 10.1109/ICCD.2003.1240952
UR - https://doi.org/10.1109/ICCD.2003.1240952
UR - https://doi.ieeecomputersociety.org/10.1109/ICCD.2003.1240952
ER -
TY - CHAP
ID - DBLP:books/sp/03/BertozziBM03
AU - Bertozzi, Davide
AU - Benini, Luca
AU - Micheli, Giovanni De
TI - Energy-Reliability trade-Off for NoCs.
BT - Networks on Chip
SP - 107
EP - 129
PY - 2003//
DO - 10.1007/0-306-48727-6_6
UR - https://doi.org/10.1007/0-306-48727-6_6
ER -
TY - CPAPER
ID - DBLP:conf/date/BertozziBM02
AU - Bertozzi, Davide
AU - Benini, Luca
AU - Micheli, Giovanni De
TI - Low Power Error Resilient Encoding for On-Chip Data Buses.
BT - 2002 Design, Automation and Test in Europe Conference and Exposition (DATE 2002), 4-8 March 2002, Paris, France
SP - 102
EP - 109
PY - 2002//
DO - 10.1109/DATE.2002.998256
UR - https://doi.org/10.1109/DATE.2002.998256
UR - https://doi.ieeecomputersociety.org/10.1109/DATE.2002.998256
UR - http://dl.acm.org/citation.cfm?id=874339
ER -
TY - CPAPER
ID - DBLP:conf/iccd/BeniniBBDFP02
AU - Benini, Luca
AU - Bertozzi, Davide
AU - Bruni, Davide
AU - Drago, Nicola
AU - Fummi, Franco
AU - Poncino, Massimo
TI - Legacy SystemC Co-Simulation of Multi-Processor Systems-on-Chip.
BT - 20th International Conference on Computer Design (ICCD 2002), VLSI in Computers and Processors, 16-18 September 2002, Freiburg, Germany, Proceedings
SP - 494
EP - 499
PY - 2002//
DO - 10.1109/ICCD.2002.1106819
UR - https://doi.org/10.1109/ICCD.2002.1106819
UR - https://doi.ieeecomputersociety.org/10.1109/ICCD.2002.1106819
ER -
TY - CPAPER
ID - DBLP:conf/iscas/BertozziBR02
AU - Bertozzi, Davide
AU - Benini, Luca
AU - Riccò, Bruno
TI - Energy-efficient and reliable low-swing signaling for on-chip buses based on redundant coding.
BT - Proceedings of the 2002 International Symposium on Circuits and Systems, ISCAS 2002, Scottsdale, Arizona, USA, May 26-29, 2002
SP - 93
EP - 96
PY - 2002//
DO - 10.1109/ISCAS.2002.1009785
UR - https://doi.org/10.1109/ISCAS.2002.1009785
ER -
TY - CPAPER
ID - DBLP:conf/islped/BertozziBR02
AU - Bertozzi, Davide
AU - Benini, Luca
AU - Riccò, Bruno
TI - Parametric timing and power macromodels for high level simulation of low-swing interconnects.
BT - Proceedings of the 2002 International Symposium on Low Power Electronics and Design, 2002, Monterey, California, USA, August 12-14, 2002
SP - 307
EP - 312
PY - 2002//
DO - 10.1145/566408.566488
UR - https://doi.org/10.1145/566408.566488
ER -
TY - CPAPER
ID - DBLP:conf/wcnc/BertozziBR02
AU - Bertozzi, Davide
AU - Benini, Luca
AU - Riccò, Bruno
TI - Power aware network interface management for streaming multimedia.
BT - 2002 IEEE Wireless Communications and Networking Conference Record, WCNC 2002, Orlando, Florida, USA, MArch 17-21, 2002
SP - 926
EP - 930
PY - 2002//
DO - 10.1109/WCNC.2002.993395
UR - https://doi.org/10.1109/WCNC.2002.993395
ER -
