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Ashwini K. Nanda
H. Peter Hofstee Ashwini K. Nanda John J. Ritsko Preface. 501-502 2007 51 IBM J. Res. Dev. 5 https://doi.org/10.1147/rd.515.0501 db/journals/ibmrd/ibmrd51.html#HofsteeNR07
Ashwini K. Nanda J. Randal Moulic Robert E. Hanson Gottfried Goldrian Michael N. Day Bruce D. D'Amora Sreeni Kesavarapu Cell/B.E. blades: Building blocks for scalable, real-time, interactive, and digital media servers. 573-582 2007 51 IBM J. Res. Dev. 5 https://doi.org/10.1147/rd.515.0573 db/journals/ibmrd/ibmrd51.html#NandaMHGDDK07
Yang Liu Holger Jones Sheila Vaidya Michael Perrone Borivoj Tydlitát Ashwini K. Nanda Speech recognition systems on the Cell Broadband Engine processor. 583-592 2007 51 IBM J. Res. Dev. 5 https://doi.org/10.1147/rd.515.0583 db/journals/ibmrd/ibmrd51.html#LiuJVPTN07
Bruce D'Amora Ashwini K. Nanda Karen A. Magerlein Atman Binstock Bernard Yee High-performance server systems and the next generation of online games. 103-118 2006 45 IBM Syst. J. 1 https://doi.org/10.1147/sj.451.0103 db/journals/ibmsj/ibmsj45.html#DAmoraNMBY06
Kimberly Keeton Russell M. Clapp Ashwini K. Nanda Guest Editors' Introduction: Evaluating Servers with Commercial Workloads. 29-32 2003 36 Computer 2 https://doi.org/10.1109/MC.2003.1178043 http://doi.ieeecomputersociety.org/10.1109/MC.2003.1178043 db/journals/computer/computer36.html#KeetonCN03
Michel Dubois 0001 Jaeheon Jeong Ashwini K. Nanda Shared cache architectures for decision support systems. 283-298 2002 49 Perform. Evaluation 1/4 db/journals/pe/pe49.html#DuboisJN02
Ashwini K. Nanda Anthony-Trung Nguyen Maged M. Michael Douglas J. Joseph High-throughout coherence control and hardware messaging in Everest. 229-244 2001 45 IBM J. Res. Dev. 2 https://doi.org/10.1147/rd.452.0299 db/journals/ibmrd/ibmrd45.html#NandaNMJ01
Yiming Hu Ashwini K. Nanda Qing Yang 0001 Measurement, Analysis and Performance Improvement of the Apache Web Server. 2001 8 Int. J. Comput. Their Appl. 4 db/journals/isca/isca8.html#HuNY01
Ashwini K. Nanda Kwok-Ken Mak Krishnan Sugavanam Ramendra K. Sahoo Vijayaraghavan Soundararajan T. Basil Smith MemorIES: A Programmable, Real-Time Hardware Emulation Tool for Multiprocessor Server Design. 37-48 2000 conf/asplos/2000 ASPLOS https://doi.org/10.1145/378993.378999 https://doi.org/10.1145/384264.378999 https://doi.org/10.1145/378995.378999 https://doi.org/10.1145/356989.356993 db/conf/asplos/asplos2000.html#NandaMSSSS00 Ashwini K. Nanda Anthony-Trung Nguyen Maged M. Michael Douglas J. Joseph High-Throughput Coherence Controllers. 145-155 2000 conf/hpca/2000 HPCA https://doi.org/10.1109/HPCA.2000.824346 https://doi.ieeecomputersociety.org/10.1109/HPCA.2000.824346 db/conf/hpca/hpca2000.html#NandaNMJ00 Ravi R. Iyer 0001 Laxmi N. Bhuyan Ashwini K. Nanda Using Switch Directories to Speed Up Cache-to-Cache Transfers in CC-NUMA Multiprocessors. 721-728 2000 conf/ipps/2000 IPDPS https://doi.org/10.1109/IPDPS.2000.846057 https://doi.ieeecomputersociety.org/10.1109/IPDPS.2000.846057 db/conf/ipps/ipdps2000.html#IyerBN00
Maged M. Michael Ashwini K. Nanda Beng-Hong Lim Coherence Controller Architectures for Scalable Shared-Memory Multiprocessors. 245-255 1999 48 IEEE Trans. Computers 2 https://doi.org/10.1109/12.752666 http://doi.ieeecomputersociety.org/10.1109/12.752666 db/journals/tc/tc48.html#MichaelNL99
Maged M. Michael Ashwini K. Nanda Design and Performance of Directory Caches for Scalable Shared Memory Multiprocessors. 142-151 1999 conf/hpca/1999 HPCA https://doi.org/10.1109/HPCA.1999.744354 https://doi.ieeecomputersociety.org/10.1109/HPCA.1999.744354 db/conf/hpca/hpca1999.html#MichaelN99 Russell M. Clapp Ashwini K. Nanda Josep Torrellas Second Workshop on Computer Architecture Evaluation Using Commercial Workloads. 322 1999 conf/hpca/1999 HPCA https://doi.ieeecomputersociety.org/10.1109/HPCA.1999.10001 db/conf/hpca/hpca1999.html#ClappNT99 Yiming Hu Ashwini K. Nanda Qing Yang 0001 Measurement, analysis and performance improvement of the Apache Web server. 261-267 1999 conf/ipccc/1999 IPCCC https://doi.org/10.1109/PCCC.1999.749447 db/conf/ipccc/ipccc1999.html#HuNY99
Ashwini K. Nanda James O. Bondi Simonjit Dutta The Misprediction Recovery Cache. 383-415 1998 26 Int. J. Parallel Program. 4 db/journals/ijpp/ijpp26.html#NandaBD98 https://doi.org/10.1023/A:1018798331295
Uming Ko Poras T. Balsara Ashwini K. Nanda Energy optimization of multilevel cache architectures for RISC and CISC processors. 299-308 1998 6 IEEE Trans. Very Large Scale Integr. Syst. 2 https://doi.org/10.1109/92.678891 db/journals/tvlsi/tvlsi6.html#KoBN98
Ashwini K. Nanda Yiming Hu Moriyoshi Ohara Caroline Benveniste Mark Giampapa Maged M. Michael The Design of COMPASS: An Execution Driven Simulator for Commercial Applications Running on Shared Memory Multiprocessors. 503-509 1998 conf/ipps/1998 IPPS/SPDP https://doi.org/10.1109/IPPS.1998.669963 https://doi.ieeecomputersociety.org/10.1109/IPPS.1998.669963 db/conf/ipps/ipps1998.html#NandaHOBGM98
Laxmi N. Bhuyan Ravi R. Iyer 0001 Tahsin Askar Ashwini K. Nanda Mohan Kumar Performance of Multistage Bus Networks for a Distributed Shared Memory Multiprocessor. 82-95 https://doi.org/10.1109/71.569657 http://doi.ieeecomputersociety.org/10.1109/71.569657 1997 8 IEEE Trans. Parallel Distributed Syst. 1 db/journals/tpds/tpds8.html#BhuyanIANK97
Anthony-Trung Nguyen Pradip Bose Kattamuri Ekanadham Ashwini K. Nanda Maged M. Michael Accuracy and Speedup of Parallel Trace-Driven Architectural Simulation. 39-44 1997 conf/ipps/1997 IPPS https://doi.org/10.1109/IPPS.1997.580842 https://doi.ieeecomputersociety.org/10.1109/IPPS.1997.580842 db/conf/ipps/ipps1997.html#NguyenBENM97 Maged M. Michael Ashwini K. Nanda Beng-Hong Lim Michael L. Scott Coherence Controller Architectures for SMP-Based CC-NUMA Multiprocessors. 219-228 1997 conf/isca/1997 ISCA https://doi.org/10.1145/264107.264203 https://doi.ieeecomputersociety.org/10.1109/ISCA.1997.604690 db/conf/isca/isca97.html#MichaelNLS97 James O. Bondi Ashwini K. Nanda Simonjit Dutta Integrating a Misprediction Recovery Cache (MRC) into a Superscalar Pipeline. 14-23 1996 conf/micro/1996 MICRO https://doi.org/10.1109/MICRO.1996.566446 https://doi.ieeecomputersociety.org/10.1109/MICRO.1996.566446 https://dl.acm.org/doi/10.5555/243846.243852 db/conf/micro/micro96.html#BondiND96 Uming Ko Poras T. Balsara Ashwini K. Nanda Energy optimization of multi-level processor cache architectures. 45-49 1995 conf/islped/1995 ISLPD https://doi.org/10.1145/224081.224090 db/conf/islped/islped1995.html#KoBN95 Laxmi N. Bhuyan Ashwini K. Nanda Tahsin Askar Performance and Reliability of the Multistage Bus Network. 26-33 1994 conf/icpp/1994-1 ICPP (1) db/conf/icpp/icpp1994-1.html#BhuyanNA94 https://doi.org/10.1109/ICPP.1994.158 https://doi.ieeecomputersociety.org/10.1109/ICPP.1994.158
Ashwini K. Nanda Laxmi N. Bhuyan Efficient Mapping of Applications on Cache Based Multiprocessors. 179-191 1993 19 J. Parallel Distributed Comput. 3 db/journals/jpdc/jpdc19.html#NandaB93 https://doi.org/10.1006/jpdc.1993.1103
Ashwini K. Nanda Laxmi N. Bhuyan Design and Analysis of Cache Coherent Multistage Interconnection Networks. 458-470 1993 42 IEEE Trans. Computers 4 db/journals/tc/tc42.html#NandaB93 https://doi.org/10.1109/12.214692 http://doi.ieeecomputersociety.org/10.1109/12.214692
Ashwini K. Nanda Hong Jiang Analysis of Directory Based Cache Coherence Schemes with Multistage Networks. 485-492 1992 conf/acm/1992 ACM Conference on Computer Science https://doi.org/10.1145/131214.131276 db/conf/acm/csc92.html#NandaJ92 Ashwini K. Nanda Doug DeGroot Daniel L. Stenger Scheduling Directed Task Graphs on Multiprocessors Using Simulated Annealing. 20-27 1992 conf/icdcs/1992 ICDCS db/conf/icdcs/icdcs92.html#NandaDS92 https://doi.org/10.1109/ICDCS.1992.235059 https://doi.ieeecomputersociety.org/10.1109/ICDCS.1992.235059 Ashwini K. Nanda Laxmi N. Bhuyan A Formal Specification and Verification Technique for Cache Coherence Protocols. 22-26 1992 conf/icpp/1992-1 ICPP (1) db/conf/icpp/icpp1992-1.html#NandaB92 Ashwini K. Nanda Laxmi N. Bhuyan Mapping Applications onto a Cache Coherent Multiprocessor. 368-377 1992 conf/sc/1992 SC db/conf/sc/sc1992.html#NandaB92 https://doi.org/10.1109/SUPERC.1992.236666 https://doi.ieeecomputersociety.org/10.1109/SUPERC.1992.236666 http://dl.acm.org/citation.cfm?id=148028 Laxmi N. Bhuyan Ashwini K. Nanda Multistage bus network (MBN): an interconnection network for cache coherent multiprocessors. 780-787 1991 SPDP https://doi.org/10.1109/SPDP.1991.218241 https://doi.ieeecomputersociety.org/10.1109/SPDP.1991.218241 conf/spdp/1991 db/conf/spdp/spdp1991.html#BhuyanN91 Tahsin Askar Poras T. Balsara Caroline Benveniste Laxmi N. Bhuyan Atman Binstock James O. Bondi Pradip Bose Russell M. Clapp Bruce D'Amora Bruce D. D'Amora Michael N. Day Doug DeGroot Michel Dubois 0001 Simonjit Dutta Kattamuri Ekanadham Mark Giampapa Gottfried Goldrian Robert E. Hanson H. Peter Hofstee Yiming Hu Ravi R. Iyer 0001 Jaeheon Jeong Hong Jiang Holger Jones Douglas J. Joseph Kimberly Keeton Sreeni Kesavarapu Uming Ko Mohan Kumar Beng-Hong Lim Yang Liu Karen A. Magerlein Kwok-Ken Mak Maged M. Michael J. Randal Moulic Anthony-Trung Nguyen Moriyoshi Ohara Michael Perrone John J. Ritsko Ramendra K. Sahoo Michael L. Scott T. Basil Smith Vijayaraghavan Soundararajan Daniel L. Stenger Krishnan Sugavanam Josep Torrellas Borivoj Tydlitát Sheila Vaidya Qing Yang 0001 Bernard Yee