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ORCIDAshwini K. Nanda
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2000 – 2009
- 2007
[j14]H. Peter Hofstee, Ashwini K. Nanda, John J. Ritsko:
Preface. IBM J. Res. Dev. 51(5): 501-502 (2007)- [j13]Ashwini K. Nanda, J. Randal Moulic, Robert E. Hanson, Gottfried Goldrian, Michael N. Day, Bruce D. D'Amora, Sreeni Kesavarapu:
Cell/B.E. blades: Building blocks for scalable, real-time, interactive, and digital media servers. IBM J. Res. Dev. 51(5): 573-582 (2007) - [j12]Yang Liu, Holger Jones, Sheila Vaidya, Michael Perrone, Borivoj Tydlitát, Ashwini K. Nanda:
Speech recognition systems on the Cell Broadband Engine processor. IBM J. Res. Dev. 51(5): 583-592 (2007) - 2006
- [j11]Bruce D'Amora, Ashwini K. Nanda, Karen A. Magerlein, Atman Binstock, Bernard Yee:
High-performance server systems and the next generation of online games. IBM Syst. J. 45(1): 103-118 (2006) - 2003
- [j10]Kimberly Keeton
, Russell M. Clapp, Ashwini K. Nanda:
Guest Editors' Introduction: Evaluating Servers with Commercial Workloads. Computer 36(2): 29-32 (2003) - 2002
- [j9]Michel Dubois, Jaeheon Jeong, Ashwini K. Nanda:
Shared cache architectures for decision support systems. Perform. Evaluation 49(1/4): 283-298 (2002) - 2001
- [j8]Ashwini K. Nanda, Anthony-Trung Nguyen, Maged M. Michael, Douglas J. Joseph:
High-throughout coherence control and hardware messaging in Everest. IBM J. Res. Dev. 45(2): 229-244 (2001) - [j7]Yiming Hu, Ashwini K. Nanda, Qing Yang:
Measurement, Analysis and Performance Improvement of the Apache Web Server. Int. J. Comput. Their Appl. 8(4) (2001) - 2000
- [c17]Ashwini K. Nanda, Kwok-Ken Mak, Krishnan Sugavanam, Ramendra K. Sahoo, Vijayaraghavan Soundararajan, T. Basil Smith:
MemorIES: A Programmable, Real-Time Hardware Emulation Tool for Multiprocessor Server Design. ASPLOS 2000: 37-48 - [c16]Ashwini K. Nanda, Anthony-Trung Nguyen, Maged M. Michael, Douglas J. Joseph:
High-Throughput Coherence Controllers. HPCA 2000: 145-155 - [c15]Ravi R. Iyer, Laxmi N. Bhuyan, Ashwini K. Nanda:
Using Switch Directories to Speed Up Cache-to-Cache Transfers in CC-NUMA Multiprocessors. IPDPS 2000: 721-728
1990 – 1999
- 1999
- [j6]Maged M. Michael, Ashwini K. Nanda, Beng-Hong Lim:
Coherence Controller Architectures for Scalable Shared-Memory Multiprocessors. IEEE Trans. Computers 48(2): 245-255 (1999) - [c14]Maged M. Michael, Ashwini K. Nanda:
Design and Performance of Directory Caches for Scalable Shared Memory Multiprocessors. HPCA 1999: 142-151 - [c13]Russell M. Clapp, Ashwini K. Nanda, Josep Torrellas:
Second Workshop on Computer Architecture Evaluation Using Commercial Workloads. HPCA 1999: 322 - [c12]Yiming Hu, Ashwini K. Nanda, Qing Yang:
Measurement, analysis and performance improvement of the Apache Web server. IPCCC 1999: 261-267 - 1998
- [j5]Ashwini K. Nanda, James O. Bondi, Simonjit Dutta:
The Misprediction Recovery Cache. Int. J. Parallel Program. 26(4): 383-415 (1998) - [j4]Uming Ko, Poras T. Balsara, Ashwini K. Nanda:
Energy optimization of multilevel cache architectures for RISC and CISC processors. IEEE Trans. Very Large Scale Integr. Syst. 6(2): 299-308 (1998) - [c11]Ashwini K. Nanda, Yiming Hu, Moriyoshi Ohara, Caroline Benveniste, Mark Giampapa, Maged M. Michael:
The Design of COMPASS: An Execution Driven Simulator for Commercial Applications Running on Shared Memory Multiprocessors. IPPS/SPDP 1998: 503-509 - 1997
- [j3]Laxmi N. Bhuyan, Ravi R. Iyer, Tahsin Askar, Ashwini K. Nanda, Mohan Kumar:
Performance of Multistage Bus Networks for a Distributed Shared Memory Multiprocessor. IEEE Trans. Parallel Distributed Syst. 8(1): 82-95 (1997) - [c10]Anthony-Trung Nguyen, Pradip Bose, Kattamuri Ekanadham, Ashwini K. Nanda, Maged M. Michael:
Accuracy and Speedup of Parallel Trace-Driven Architectural Simulation. IPPS 1997: 39-44 - [c9]Maged M. Michael, Ashwini K. Nanda, Beng-Hong Lim, Michael L. Scott:
Coherence Controller Architectures for SMP-Based CC-NUMA Multiprocessors. ISCA 1997: 219-228 - 1996
- [c8]James O. Bondi, Ashwini K. Nanda, Simonjit Dutta:
Integrating a Misprediction Recovery Cache (MRC) into a Superscalar Pipeline. MICRO 1996: 14-23 - 1995
- [c7]Uming Ko, Poras T. Balsara, Ashwini K. Nanda:
Energy optimization of multi-level processor cache architectures. ISLPD 1995: 45-49 - 1994
- [c6]Laxmi N. Bhuyan, Ashwini K. Nanda, Tahsin Askar:
Performance and Reliability of the Multistage Bus Network. ICPP (1) 1994: 26-33 - 1993
- [j2]Ashwini K. Nanda, Laxmi N. Bhuyan:
Efficient Mapping of Applications on Cache Based Multiprocessors. J. Parallel Distributed Comput. 19(3): 179-191 (1993) - [j1]Ashwini K. Nanda, Laxmi N. Bhuyan:
Design and Analysis of Cache Coherent Multistage Interconnection Networks. IEEE Trans. Computers 42(4): 458-470 (1993) - 1992
- [c5]Ashwini K. Nanda, Hong Jiang:
Analysis of Directory Based Cache Coherence Schemes with Multistage Networks. ACM Conference on Computer Science 1992: 485-492 - [c4]Ashwini K. Nanda, Doug DeGroot, Daniel L. Stenger:
Scheduling Directed Task Graphs on Multiprocessors Using Simulated Annealing. ICDCS 1992: 20-27 - [c3]Ashwini K. Nanda, Laxmi N. Bhuyan:
A Formal Specification and Verification Technique for Cache Coherence Protocols. ICPP (1) 1992: 22-26 - [c2]Ashwini K. Nanda, Laxmi N. Bhuyan:
Mapping Applications onto a Cache Coherent Multiprocessor. SC 1992: 368-377 - 1991
- [c1]Laxmi N. Bhuyan, Ashwini K. Nanda:
Multistage bus network (MBN): an interconnection network for cache coherent multiprocessors. SPDP 1991: 780-787
Coauthor Index
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