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ORCIDWolfgang Roesner
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2020 – today
- 2024
[j7]Arun Joseph
, Pretty Mariam Jacob, Matthias Klein, Wolfgang Roesner:
Efficient Aspect Verification and Debugging of High-Performance Microprocessor Designs. IEEE Des. Test 41(3): 36-46 (2024)
2010 – 2019
- 2019
- [j6]Maya H. Safieddine, Fadi A. Zaraket, Rouwaida Kanj, Ali S. Elzein, Wolfgang Roesner:
Verification at RTL Using Separation of Design Concerns. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 38(8): 1529-1542 (2019) - 2015
- [c5]Stephen Bergman, Gabor Bobok, Walter Kowalski, Shlomit Koyfman, Shiri Moran, Ziv Nevo, Avigail Orni, Viresh Paruthi, Wolfgang Roesner, Gil Shurek, Vasantha Vuyyuru:
Designer-level verification: an industrial experience story. DATE 2015: 410-411 - 2014
- [c4]Amir Nahir, Manoj Dusanapudi, Shakti Kapoor, Kevin Reick, Wolfgang Roesner, Klaus-Dieter Schubert, Keith Sharp, Greg Wetli:
Post-Silicon Validation of the IBM POWER8 Processor. DAC 2014: 56:1-56:6
2000 – 2009
- 2009
- [j5]Christopher A. Krygowski, Dean G. Bair, Rebecca M. Gott, M. H. Decker, A. V. Giri, Christian Habermann, Matthias Heizmann, Stefan Letz, William J. Lewis, Steven M. Licker, H. Mallar, Edward C. McCain, Wolfgang Roesner, N. Siddique, A. E. Seigler, Brian W. Thompto, K. Weber, Ralf Winkelmann:
Functional verification of the IBM System z10 processor chipset. IBM J. Res. Dev. 53(1): 3 (2009) - 2008
- [c3]Hiroyuki Yagi, Wolfgang Roesner, Tim Kogel, Eshel Haritan, Hidekazu Tangi, Michael McNamara, Gary Smith, Nikil D. Dutt, Giovanni Mancini:
ESL hand-off: fact or EDA fiction? DAC 2008: 310-312 - 2004
- [j4]Hans-Werner Anderson, Hans Kriese, Wolfgang Roesner, Klaus-Dieter Schubert:
Configurable system simulation model build comprising packaging design data. IBM J. Res. Dev. 48(3-4): 367-378 (2004) - 2003
- [c2]Wolfgang Roesner:
What Is beyond the RTL Horizon for Microprocessor and System Design? CHARME 2003: 1 - 2002
- [j3]John M. Ludden, Wolfgang Roesner, Gerry M. Heiling, John R. Reysa, Jonathan R. Jackson, Bing-Lun Chu, Michael L. Behm, Jason Baumgartner, Richard D. Peterson, Jamee Abdulhafiz, William E. Bucy, John H. Klaus, Danny J. Klema, Tien N. Le, F. Danette Lewis, Philip E. Milling, Lawrence A. McConville, Bradley S. Nelson, Viresh Paruthi, Travis W. Pouarz, Audre D. Romonosky, Jeff Stuecheli, Kent D. Thompson, Dave W. Victor, Bruce Wile:
Functional verification of the POWER4 microprocessor and POWER4 multiprocessor system. IBM J. Res. Dev. 46(1): 53-76 (2002) - 2000
- [j2]John A. Darringer, Evan E. Davidson, David J. Hathaway, Bernd Koenemann, Mark A. Lavin, Joseph K. Morrell, Khalid Rahmat, Wolfgang Roesner, Erich C. Schanzenbach, Gustavo E. Téllez, Louise Trevillyan:
EDA in IBM: past, present, and future. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 19(12): 1476-1497 (2000)
1980 – 1989
- 1988
- [j1]Wolfgang Roesner:
The logic design language and verification environment for the VLSI-/370. Microprocess. Microprogramming 24(1-5): 35-42 (1988) - 1985
- [c1]Wolfgang Roesner:
SESPATH: An ER Manipulation Language. ER 1985: 72-81
Coauthor Index
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