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ORCIDShankar Balachandran
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2020 – today
- 2022
[c27]Rahul Bera
, Konstantinos Kanellopoulos, Shankar Balachandran, David Novo, Ataberk Olgun, Mohammad Sadrosadati, Onur Mutlu:
Hermes: Accelerating Long-Latency Load Requests via Perceptron-Based Off-Chip Load Prediction. MICRO 2022: 1-18- [i5]Rahul Bera, Konstantinos Kanellopoulos, Shankar Balachandran, David Novo, Ataberk Olgun, Mohammad Sadrosadati, Onur Mutlu:
Hermes: Accelerating Long-Latency Load Requests via Perceptron-Based Off-Chip Load Prediction. CoRR abs/2209.00188 (2022) - 2021
- [c26]Anant V. Nori, Rahul Bera, Shankar Balachandran, Joydeep Rakshit, Om Ji Omer, Avishaii Abuhatzera, Belliappa Kuttanna, Sreenivas Subramoney:
REDUCT: Keep it Close, Keep it Cool! : Efficient Scaling of DNN Inference on Multi-core CPUs with Near-Cache Compute. ISCA 2021: 167-180 - 2020
- [c25]Antara Ganguly, Shankar Balachandran, Anant V. Nori, Virendra Singh, Sreenivas Subramoney:
Characterization of Data Generating Neural Network Applications on x86 CPU Architecture. ISPASS 2020: 121-122 - [i4]Anant V. Nori, Rahul Bera, Shankar Balachandran, Joydeep Rakshit, Om Ji Omer, Avishaii Abuhatzera, Belliappa Kuttanna, Sreenivas Subramoney:
Proximu: Efficiently Scaling DNN Inference in Multi-core CPUs through Near-Cache Compute. CoRR abs/2011.11695 (2020)
2010 – 2019
- 2018
- [j9]Jyothi Krishna Viswakaran Sreelatha, Shankar Balachandran, Rupesh Nasre:
CHOAMP: Cost Based Hardware Optimization for Asymmetric Multicore Processors. IEEE Trans. Multi Scale Comput. Syst. 4(2): 163-176 (2018) - [i3]Jyothi Krishna V. S, Shankar Balachandran:
Compiler Enhanced Scheduling for OpenMP for Heterogeneous Multiprocessors. CoRR abs/1808.06074 (2018) - 2016
- [j8]Biswabandan Panda, Shankar Balachandran:
Expert Prefetch Prediction: An Expert Predicting the Usefulness of Hardware Prefetchers. IEEE Comput. Archit. Lett. 15(1): 13-16 (2016) - [c24]Shankar Balachandran, Sajin Koroth:
Subclasses of Baxter Permutations Based on Pattern Avoidance. CSR 2016: 192-206 - 2015
- [j7]Aditya Pratapa, Shankar Balachandran, Karthik Raman:
Fast-SL: an efficient algorithm to identify synthetic lethal sets in metabolic networks. Bioinform. 31(20): 3299-3305 (2015) - [j6]Milan Patnaik, Chidhambaranathan Rajamanikkam, Chirag Garg, Arnab Roy, V. R. Devanathan, Shankar Balachandran, V. Kamakoti:
ProWATCh: A Proactive Cross-Layer Workload-Aware Temperature Management Framework for Low-Power Chip Multi-Processors. ACM J. Emerg. Technol. Comput. Syst. 12(3): 22:1-22:25 (2015) - [j5]Biswabandan Panda, Shankar Balachandran:
CAFFEINE: A Utility-Driven Prefetcher Aggressiveness Engine for Multicores. ACM Trans. Archit. Code Optim. 12(3): 30:1-30:25 (2015) - [c23]Adithyalal P. M, Shankar Balachandran, Virendra Singh:
A Soft Error Resilient Low Leakage SRAM Cell Design. ATS 2015: 133-138 - [c22]Parth Lathigara, Shankar Balachandran, Virendra Singh:
Application behavior aware re-reference interval prediction for shared LLC. ICCD 2015: 172-179 - [c21]B. N. Bhramar Ray, Shankar Balachandran:
A Recursive Model for Smooth Approximation to Wirelength and Its Impact on Analytical Placement. VLSID 2015: 417-422 - 2014
- [j4]Satya Trinadh, Seetal Potluri, Shankar Balachandran, Ch. Sobhan Babu, V. Kamakoti:
XStat: Statistical X-Filling Algorithm for Peak Capture Power Reduction in Scan Tests. J. Low Power Electron. 10(1): 107-115 (2014) - [c20]Biswabandan Panda, Shankar Balachandran:
XStream: cross-core spatial streaming based MLC prefetchers for parallel applications in CMPs. PACT 2014: 87-98 - [c19]Biswabandan Panda, Shankar Balachandran:
Introducing Thread Criticality awareness in Prefetcher Aggressiveness Control. DATE 2014: 1-6 - [c18]Nihar Rathod, Shankar Balachandran, Neel Gala:
CAERUS: an effective arbitration and ejection policy for routing in an unidirectional torus. INA-OCMC@HiPEAC 2014: 1:1-1:4 - 2013
- [c17]Biswabandan Panda, Shankar Balachandran:
TCPT - Thread criticality-driven prefetcher throttling. PACT 2013: 399 - [c16]B. N. Bhramar Ray, Shankar Balachandran:
An efficient wirelength model for analytical placement. DATE 2013: 1711-1714 - [c15]Seetal Potluri, Satya Trinadh Adireddy, Chidhambaranathan Rajamanikkam, Shankar Balachandran:
LPScan: An algorithm for supply scaling and switching activity minimization during test. ICCD 2013: 463-466 - [c14]Madhur Amilkanthwar, Shankar Balachandran:
CUPL: a compile-time uncoalesced memory access pattern locator for CUDA. ICS 2013: 459-460 - [c13]Ankit Kagliwal, Shankar Balachandran:
Measuring Area-Complexity Using Boolean Difference. VLSI Design 2013: 245-250 - 2012
- [c12]Biswabandan Panda, Shankar Balachandran:
Hardware prefetchers for emerging parallel applications. PACT 2012: 485-486 - [c11]Sharmistha, Madhur Amilkanthwar, Shankar Balachandran:
Augmentation of Programs with CUDA Streams. ISPA 2012: 855-856 - [c10]Ashok Gautham, Kunal Korgaonkar, Patanjali SLPSK, Shankar Balachandran, Kamakoti Veezhinathan:
The Implications of Shared Data Synchronization Techniques on Multi-Core Energy Efficiency. HotPower 2012 - [c9]Biswabandan Panda, Shankar Balachandran:
CSHARP: Coherence and SHaring Aware Cache Replacement Policies for Parallel Applications. SBAC-PAD 2012: 252-259 - [c8]Ankit Kagliwal, Shankar Balachandran:
Set-Cover Heuristics for Two-Level Logic Minimization. VLSI Design 2012: 197-202 - 2011
- [j3]Nitin Chandrachoodan, Shankar Balachandran:
24th "IEEE International Conference on VLSI Design" Chennai, India, 2-7 January 2011. J. Low Power Electron. 7(4): 459 (2011) - [c7]B. N. Bhramar Ray, Shankar Balachandran:
A New Wirelength Model for Analytical Placement. ISVLSI 2011: 90-95 - [i2]Shankar Balachandran, Sajin Koroth:
A study on the number of Hierarchical Rectangular Partitions of Order k. CoRR abs/1112.1374 (2011) - [i1]Shankar Balachandran, Sajin Koroth:
A Study on Hierarchical Floorplans of Order k. CoRR abs/1112.1396 (2011)
2000 – 2009
- 2005
- [j2]Shankar Balachandran, Dinesh Bhatia:
A priori wirelength and interconnect estimation based on circuit characteristic. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 24(7): 1054-1065 (2005) - [c6]Shankar Balachandran, Dinesh Bhatia:
Timing Aware Interconnect Prediction Models for FPGAs. FPL 2005: 167-172 - 2004
- [j1]PariVallal Kannan, Shankar Balachandran, Dinesh Bhatia:
On metrics for comparing interconnect estimation methods for FPGAs. IEEE Trans. Very Large Scale Integr. Syst. 12(4): 381-385 (2004) - 2003
- [c5]Shankar Balachandran, Dinesh Bhatia:
A-priori wirelength and interconnect estimation based on circuit characteristics. SLIP 2003: 77-84 - 2002
- [c4]PariVallal Kannan, Shankar Balachandran, Dinesh Bhatia:
On metrics for comparing routability estimation methods for FPGAs. DAC 2002: 70-75 - [c3]PariVallal Kannan, Shankar Balachandran, Dinesh Bhatia:
Rapid and Reliable Routability Estimation for FPGAs. FPL 2002: 242-252 - [c2]Shankar Balachandran, PariVallal Kannan, Dinesh Bhatia:
On Routing Demand and Congestion Estimation for FPGAs. ASP-DAC/VLSI Design 2002: 639-646 - 2001
- [c1]PariVallal Kannan, Shankar Balachandran, Dinesh Bhatia:
fGREP - Fast Generic Routing Demand Estimation for Placed FPGA Circuits. FPL 2001: 37-47
Coauthor Index
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