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Zhuoyu Dai
Chaojie He Zi Wang Feibin Xiang Zhuoyu Dai Yifan He Jinshan Yue Yongpan Liu LSAC: A Low-Power Adder Tree for Digital Computing-in-Memory by Sparsity and Approximate Circuits Co-Design. 852-856 2024 February 71 IEEE Trans. Circuits Syst. II Express Briefs 2 https://doi.org/10.1109/TCSII.2023.3304752 db/journals/tcasII/tcasII71.html#HeWXDHYL24
Zhuoyu Dai Shengzhe Yan Zhaori Cong Zeyu Guo 0002 Yifan He Wenyu Sun Chunmeng Dou Feng Zhang 0014 Jinshan Yue Yongpan Liu Ming Liu 0022 A 41.7TOPS/W@INT8 Computing-in-Memory Processor with Zig-Zag Backbone-Systolic CIM and Block/Self-Gating CAM for NN/Recommendation Applications. 1-2 2024 VLSI Technology and Circuits https://doi.org/10.1109/VLSITechnologyandCir46783.2024.10631368 conf/vlsit/2024 db/conf/vlsit/vlsit2024.html#DaiYC0HSDZYLL24
Zhuoyu Dai Feibin Xiang Chaojie He Zi Wang Woyu Zhang Yi Li Jinshan Yue Dashan Shang A Scalable Small-Footprint Time-Space-Pipelined Architecture for Reservoir Computing. 3069-3073 2023 August 70 IEEE Trans. Circuits Syst. II Express Briefs 8 https://doi.org/10.1109/TCSII.2023.3252802 db/journals/tcasII/tcasII70.html#DaiXHWZLYS23
Zi Wang Jinshan Yue Chaojie He Zhuoyu Dai Feibin Xiang Zhaori Cong Yifan He Xiaoyu Feng Yongpan Liu A User-Friendly Fast and Accurate Simulation Framework for Non-Ideal Factors in Computing-in-Memory Architecture. 1-5 2023 ISCAS https://doi.org/10.1109/ISCAS46773.2023.10182131 conf/iscas/2023 db/conf/iscas/iscas2023.html#WangYHDXCHFL23 Zhaori Cong Chunmeng Dou Xiaoyu Feng Zeyu Guo 0002 Chaojie He Yifan He Yi Li Ming Liu 0022 Yongpan Liu Dashan Shang Wenyu Sun Zi Wang Feibin Xiang Shengzhe Yan Jinshan Yue Feng Zhang 0014 Woyu Zhang