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2020 – today
- 2023
[c4]Li-Chen Wang, Shao-Yun Fang:
Mitigating Layout Dependent Effect-induced Timing Risk in Multi-Row-Height Detailed Placement. DATE 2023: 1-2- [c3]Li-Chen Wang, W. Li, Nirmaan Shanker, Suraj S. Cheema, Shang-Lin Hsu, S. Volkman, U. Sikder, C. Garg, J.-H. Park, Y.-H. Liao, Yen-Kai Lin, Chenming Hu, Sayeef S. Salahuddin:
Record Transconductance in Leff~30 nm Self-Aligned Replacement Gate ETSOI nFETs Using Low EOT Negative Capacitance HfO2-ZrO2 Superlattice Gate Stack. VLSI Technology and Circuits 2023: 1-2 - 2022
- [c2]Nirmaan Shanker, Li-Chen Wang, Suraj S. Cheema, Wenshen Li, Nilotpal Choudhury, Chenming Hu, Souvik Mahapatra, Sayeef S. Salahuddin:
On the PBTI Reliability of Low EOT Negative Capacitance 1.8 nm HfO2-ZrO2 Superlattice Gate Stack on Lg=90 nm nFETs. VLSI Technology and Circuits 2022: 421-422 - 2020
- [c1]Ava J. Tan, Li-Chen Wang, Yu-Hung Liao, Jong-Ho Bae, Chenming Hu, Sayeef S. Salahuddin:
Reliability of Ferroelectric HfO2-based Memories: From MOS Capacitor to FeFET. DRC 2020: 1-2
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